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1. 发明授权

US08527820B2 Semiconductor device and test method thereof 有权
标题翻译：半导体器件及其测试方法
公开(公告)号：US08527820B2
公开(公告)日：2013-09-03
申请号：US13022194
申请日：2011-02-07
申请人： Shin Ito
发明人： Shin Ito
IPC分类号： G11C29/00
CPC分类号： G11C29/765 , G11C29/56 , G11C29/883 , G11C2029/4402 , G11C2229/723
摘要： A semiconductor device includes a first management area storing a plurality of inspection results, the plurality of inspection results being obtained by executing inspections for each of a plurality of storage areas which store a plurality of data; and a second management area storing the plurality of inspection results. The first and second management areas are independent from each other.
摘要翻译：半导体器件包括存储多个检查结果的第一管理区域，通过对存储多个数据的多个存储区域中的每一个执行检查而获得多个检查结果; 以及存储多个检查结果的第二管理区域。第一和第二个管理区域彼此独立。

2. 发明申请

US20110026326A1 MEMORY SYSTEM INCLUDING FLASH MEMORY AND METHOD OF OPERATING THE SAME 审中-公开
标题翻译：包括闪速存储器的存储器系统及其操作方法
公开(公告)号：US20110026326A1
公开(公告)日：2011-02-03
申请号：US12897869
申请日：2010-10-05
申请人： Kyoong-Han LEE , Young-Joon CHOI , Yang-Sup LEE
发明人： Kyoong-Han LEE , Young-Joon CHOI , Yang-Sup LEE
IPC分类号： G11C16/06 , G11C29/52
CPC分类号： G06F11/1068 , G11C16/04 , G11C29/76 , G11C2029/0409 , G11C2029/0411 , G11C2229/723
摘要： A method for operating a memory system including a flash memory device having a plurality of memory blocks includes determining whether a read error generated during a read operation of the flash memory device is caused by read disturbance and replacing a memory block which includes the read error, with a spare memory block if the read error is caused by read disturbance.
摘要翻译：一种用于操作包括具有多个存储器块的闪速存储器件的存储器系统的方法，包括：确定在闪速存储器件的读取操作期间产生的读取错误是否由读取干扰引起，并且更换包括读取错误的存储器块，如果读取错误是由读取干扰引起的，则会带有备用存储器块。

3. 发明授权

US07624329B2 Programming a memory device having error correction logic 有权
标题翻译：编程具有纠错逻辑的存储器件
公开(公告)号：US07624329B2
公开(公告)日：2009-11-24
申请号：US11468638
申请日：2006-08-30
申请人： Ronald J. Syzdek , Timothy J. Strauss
发明人： Ronald J. Syzdek , Timothy J. Strauss
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G06F11/1068 , G11C16/04 , G11C16/22 , G11C16/3454 , G11C29/52 , G11C2029/0411 , G11C2029/4402 , G11C2229/723
摘要： Methods and apparatus for programming a non-volatile memory array comprising addressable units are provided. The addressable units are configured to store at least a main portion and an error correction portion. An exemplary method for programming the non-volatile memory array includes, in response to a first condition, switching from an error correction enabled mode to an error correction disabled mode and programming at least the main portion of at least one addressable unit of the non-volatile memory array in the error correction disabled mode. The exemplary method further includes, in response to a second condition, switching from the error correction disabled mode to an error correction fill mode and programming at least the error correction portion of the at least one addressable unit of the non-volatile memory array in the error correction fill mode.
摘要翻译：提供了用于编程包括可寻址单元的非易失性存储器阵列的方法和装置。可寻址单元被配置为至少存储主要部分和纠错部分。用于对非易失性存储器阵列进行编程的示例性方法包括响应于第一条件从错误校正允许模式切换到纠错禁止模式，并且至少编程非易失性存储器阵列的至少一个可寻址单元的主要部分，易失性存储器阵列处于纠错禁用模式。该示例性方法还包括响应于第二条件，从误差校正禁用模式切换到纠错填充模式，并且至少编程非易失性存储器阵列的至少一个可寻址单元的纠错部分纠错填充模式。

4. 发明授权

US07570526B2 Memory device and method of repairing the same 有权
标题翻译：内存装置及其修复方法
公开(公告)号：US07570526B2
公开(公告)日：2009-08-04
申请号：US11617226
申请日：2006-12-28
申请人： Jung Chul Han
发明人： Jung Chul Han
IPC分类号： G11C29/00
CPC分类号： G11C17/18 , G11C29/76 , G11C29/802 , G11C2229/723
摘要： A memory device includes a main memory cell having a plurality of first memory cells for storing data, wherein a special block for storing a column address corresponding to a first memory cell having at least one failure is disposed in a part of area of the main memory cell; a start address block configured to store address information initiated by the special block of the main memory cell; and a repair information block configured to provisionally store the column address stored in the special block, and to output a repair controlling signal when operating the memory device.
摘要翻译：一种存储装置包括具有多个用于存储数据的第一存储单元的主存储单元，其中存储与具有至少一个故障的第一存储单元对应的列地址的特殊块设置在主存储器的一部分区域中细胞; 开始地址块，被配置为存储由所述主存储单元的特殊块发起的地址信息; 以及修复信息块，被配置为临时存储存储在特殊块中的列地址，并且在操作存储器件时输出修复控制信号。

5. 发明授权

US07551488B2 Semiconductor nonvolatile memory trimming technique for output characteristic control and redundancy repair 有权
标题翻译：用于输出特性控制和冗余修复的半导体非易失性存储器修整技术
公开(公告)号：US07551488B2
公开(公告)日：2009-06-23
申请号：US11748001
申请日：2007-05-14
申请人： Hiroyuki Tanikawa , Teruhiro Harada , Nobukazu Murata
发明人： Hiroyuki Tanikawa , Teruhiro Harada , Nobukazu Murata
IPC分类号： G11C16/06
CPC分类号： G11C16/10 , G06F11/1004 , G11C16/04 , G11C16/0475 , G11C29/02 , G11C29/027 , G11C29/028 , G11C29/42 , G11C29/72 , G11C2029/0407 , G11C2229/723
摘要： In a semiconductor nonvolatile memory, plural first nonvolatile memory cells are arranged in the memory array. Plural memory areas are arranged in the memory array and have plural second nonvolatile memory cells which store the same predetermined information. A sequence circuit generates a memory address, a latch selection signal, and a control signal at predetermined timings when a power is turned on. A write-read unit writes and reads information to and from the memory array and the memory areas based on the memory address and the control signal. A latch circuit latches the predetermined information, read by the write-read unit, based on the latch selection signal. A selection-drive unit selects the first or second nonvolatile memory cells based on the memory address and the predetermined information latched by the latch circuit, and applies a predetermined voltage to drive the selected first or second nonvolatile memory cells.
摘要翻译：在半导体非易失性存储器中，多个第一非易失性存储单元布置在存储器阵列中。多个存储器区域被布置在存储器阵列中，并且具有存储相同的预定信息的多个第二非易失性存储器单元。当电源接通时，序列电路产生存储器地址，锁存选择信号和预定定时的控制信号。写入单元基于存储器地址和控制信号向存储器阵列和存储器区域写入信息和从存储器区域读取信息。锁存电路基于锁存选择信号来锁存由写入单元读取的预定信息。选择驱动单元基于存储器地址和由锁存电路锁存的预定信息来选择第一或第二非易失性存储单元，并施加预定电压以驱动所选择的第一或第二非易失性存储单元。

6. 发明申请

US20080072117A1 PROGRAMMING A MEMORY DEVICE HAVING ERROR CORRECTION LOGIC 有权
标题翻译：编程具有错误校正逻辑的存储器件
公开(公告)号：US20080072117A1
公开(公告)日：2008-03-20
申请号：US11468638
申请日：2006-08-30
申请人： Ronald J. Syzdek , Timothy J. Strauss
发明人： Ronald J. Syzdek , Timothy J. Strauss
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G06F11/1068 , G11C16/04 , G11C16/22 , G11C16/3454 , G11C29/52 , G11C2029/0411 , G11C2029/4402 , G11C2229/723
摘要： Methods and apparatus for programming a non-volatile memory array comprising addressable units are provided. The addressable units are configured to store at least a main portion and an error correction portion. An exemplary method for programming the non-volatile memory array includes, in response to a first condition, switching from an error correction enabled mode to an error correction disabled mode and programming at least the main portion of at least one addressable unit of the non-volatile memory array in the error correction disabled mode. The exemplary method further includes, in response to a second condition, switching from the error correction disabled mode to an error correction fill mode and programming at least the error correction portion of the at least one addressable unit of the non-volatile memory array in the error correction fill mode.
摘要翻译：提供了用于编程包括可寻址单元的非易失性存储器阵列的方法和装置。可寻址单元被配置为至少存储主要部分和纠错部分。用于对非易失性存储器阵列进行编程的示例性方法包括响应于第一条件从错误校正允许模式切换到纠错禁止模式，并且至少编程非易失性存储器阵列的至少一个可寻址单元的主要部分，易失性存储器阵列处于纠错禁用模式。该示例性方法还包括响应于第二条件，从误差校正禁用模式切换到纠错填充模式，并且至少编程非易失性存储器阵列的至少一个可寻址单元的纠错部分纠错填充模式。

7. 发明申请

US20080043537A1 Semiconductor Nonvolatile Memory 有权
标题翻译：半导体非易失性存储器
公开(公告)号：US20080043537A1
公开(公告)日：2008-02-21
申请号：US11748001
申请日：2007-05-14
申请人： Hiroyuki Tanikawa , Teruhiro Harada , Nobukazu Murata
发明人： Hiroyuki Tanikawa , Teruhiro Harada , Nobukazu Murata
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G06F11/1004 , G11C16/04 , G11C16/0475 , G11C29/02 , G11C29/027 , G11C29/028 , G11C29/42 , G11C29/72 , G11C2029/0407 , G11C2229/723
摘要： In a semiconductor nonvolatile memory, plural first nonvolatile memory cells are arranged in the memory array. Plural memory areas are arranged in the memory array and have plural second nonvolatile memory cells which store the same predetermined information. A sequence circuit generates a memory address, a latch selection signal, and a control signal at predetermined timings when a power is turned on. A write-read unit writes and reads information to and from the memory array and the memory areas based on the memory address and the control signal. A latch circuit latches the predetermined information, read by the write-read unit, based on the latch selection signal. A selection-drive unit selects the first or second nonvolatile memory cells based on the memory address and the predetermined information latched by the latch circuit, and applies a predetermined voltage to drive the selected first or second nonvolatile memory cells.
摘要翻译：在半导体非易失性存储器中，多个第一非易失性存储单元布置在存储器阵列中。多个存储器区域被布置在存储器阵列中，并且具有存储相同的预定信息的多个第二非易失性存储器单元。当电源接通时，序列电路产生存储器地址，锁存选择信号和预定定时的控制信号。写入单元基于存储器地址和控制信号向存储器阵列和存储器区域写入信息和从存储器区域读取信息。锁存电路基于锁存选择信号来锁存由写入单元读取的预定信息。选择驱动单元基于存储器地址和由锁存电路锁存的预定信息来选择第一或第二非易失性存储单元，并施加预定电压以驱动所选择的第一或第二非易失性存储单元。

8. 发明申请

US20070147150A1 Nonvolatile memory 有权
公开(公告)号：US20070147150A1
公开(公告)日：2007-06-28
申请号：US11711085
申请日：2007-02-27
申请人： Hirofumi Shibuya , Fumio Hara , Hiroyuki Goto , Shigemasa Shiota
发明人： Hirofumi Shibuya , Fumio Hara , Hiroyuki Goto , Shigemasa Shiota
IPC分类号： G11C29/00
CPC分类号： G06F11/1666 , G06F11/004 , G06F11/20 , G06F11/2053 , G11C16/04 , G11C29/44 , G11C29/4401 , G11C29/76 , G11C2029/0407 , G11C2029/0409 , G11C2229/723
摘要： It is aimed to detect, notify, and save an abnormal area in semiconductor memory for greatly improving reliability. An inside of semiconductor memories provided for a memory card comprises a user area, a substitution area, an area substitution information storage area, and a management area. An inside of semiconductor memories comprises a user area, a substitution area, and a management area. The user area is a data area a user can use. The substitution area is substituted when an error occurs in the user area. The area substitution information storage area stores area substitution area information. The management area stores substitution information. The information processing section performs substitution on two levels as follows. When detecting an operation indicating a symptom of failure in a semiconductor memory area, the information processing section performs area substitution during an idle state of the memory card. When detecting a faulty operation in an area, the information processing section immediately performs area substitution.

9. 发明授权

US6091650A Redundancy for low remanence memory cells 失效
标题翻译：低残留记忆细胞的冗余
公开(公告)号：US6091650A
公开(公告)日：2000-07-18
申请号：US321023
申请日：1999-05-27
申请人： Richard Ferrant
发明人： Richard Ferrant
IPC分类号： G06F11/20 , G11C7/00
CPC分类号： G11C29/846 , G11C29/44 , G11C29/4401 , G11C2029/4402 , G11C2229/723
摘要： A memory device includes a defect memory, a test circuit, and a spare memory. The defect memory and the spare memory have as many rows as the array, and each row of the defect memory and the spare memory are selected when the corresponding row of the array is selected. A test circuit locates defective cells of the array and writes addresses in the defect memory to indicate locations of the defective cells. Additionally, a control circuit selects a row of the array based on a selected row address and redirects access to the corresponding row of the spare memory whenever a selected column address corresponds to one of the addresses stored in the defect memory. In one preferred embodiment, each of the rows of the defect memory stores information indicating if there is a defective cell in the corresponding row of the array and the column address of the defective cell. A computer system including such a memory device is also provided.
摘要翻译：存储器件包括缺陷存储器，测试电路和备用存储器。缺陷存储器和备用存储器具有与阵列一样多的行，并且当选择阵列的相应行时，选择缺陷存储器和备用存储器的每一行。测试电路定位阵列的故障单元，并将缺陷存储器中的地址写入以指示故障单元的位置。另外，只要选择的列地址对应于存储在缺陷存储器中的一个地址，控制电路就基于所选择的行地址选择一行阵列，并重定向到备用存储器的相应行的访问。在一个优选实施例中，缺陷存储器的每行都存储指示阵列的相应行中是否存在缺陷单元的信息以及有缺陷单元的列地址。还提供了包括这种存储装置的计算机系统。

10. 发明申请

US20150161002A1 DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT 有权
标题翻译：解码方法，存储器存储器和存储器控制电路单元
公开(公告)号：US20150161002A1
公开(公告)日：2015-06-11
申请号：US14166781
申请日：2014-01-28
申请人： PHISON ELECTRONICS CORP.
发明人： Chih-Hsuan Chiang
IPC分类号： G06F11/10 , G11C29/52 , G11C29/00
CPC分类号： H03M13/255 , G06F11/1008 , G06F11/1012 , G11B2020/185 , G11C2029/0411 , G11C2229/723 , H03M13/09 , H03M13/11 , H03M13/13
摘要： A decoding method for a parity check code, a memory storage device and a memory controlling circuit unit are provided. The decoding method includes: reading a codeword belonging to the parity check code from a rewritable non-volatile memory module, wherein the codeword includes message bits and first parity bits; performing an encoding procedure of the parity check code on the message bits to generate second parity bits; and generating a plurality of syndromes corresponding to the codeword according to the first parity bits and the second parity bits, wherein the syndromes are used to determine whether the codeword is a valid codeword. Accordingly, a complexity of a decoding circuit is decreased.
摘要翻译：提供奇偶校验码的解码方法，存储器存储装置和存储器控制电路单元。解码方法包括：从可重写非易失性存储器模块读取属于奇偶校验码的码字，其中码字包括消息比特和第一奇偶校验位; 对消息比特执行奇偶校验码的编码过程以产生第二奇偶校验位; 以及根据所述第一奇偶校验位和所述第二奇偶校验位生成对应于所述码字的多个校正子，其中所述校正子用于确定所述码字是否是有效码字。因此，解码电路的复杂度降低。

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