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1. 发明授权

US5594687A Completely complementary MOS memory cell with tunneling through the NMOS and PMOS transistors during program and erase 失效
标题翻译：完全互补的MOS存储单元，在编程和擦除期间通过NMOS和PMOS晶体管隧穿
公开(公告)号：US5594687A
公开(公告)日：1997-01-14
申请号：US447991
申请日：1995-05-23
申请人： Jonathan Lin , Radu Barsan , Bradley A. Sharpe-Geisler
发明人： Jonathan Lin , Radu Barsan , Bradley A. Sharpe-Geisler
IPC分类号： G11C16/04 , H01L27/115
CPC分类号： G11C16/045 , G11C16/0441 , H01L27/115 , G11C2216/10
摘要： Circuitry added to CMOS memory cell configured to enable tunneling through its PMOS and NMOS transistors, the circuitry preventing leakage current during programming. The circuitry includes a separate NMOS pass gate for connecting the source of the NMOS transistor of the CMOS cell to Vss. The gate of the NMOS pass gate is controlled to turn off the NMOS transistor during programming through the PMOS transistor to prevent current loss on the Vss line. The NMOS pass gate further provides a means for enabling or disabling the NMOS transistor making the CMOS cell useful as an array cell for a PAL device.
摘要翻译：电路添加到CMOS存储器单元中，配置为能够通过其PMOS和NMOS晶体管进行隧穿，该电路可防止编程期间的漏电流。该电路包括用于将CMOS单元的NMOS晶体管的源极连接到Vss的单独的NMOS通孔。在通过PMOS晶体管的编程期间，NMOS栅极的栅极被控制为关闭NMOS晶体管，以防止Vss线上的电流损耗。 NMOS栅极进一步提供用于启用或禁用NMOS晶体管的装置，其使得CMOS单元可用作PAL器件的阵列单元。

2. 发明授权

US5646901A CMOS memory cell with tunneling during program and erase through the NMOS and PMOS transistors and a pass gate separating the NMOS and PMOS transistors 失效
标题翻译：在通过NMOS和PMOS晶体管编程和擦除期间具有隧穿的CMOS存储器单元以及分离NMOS和PMOS晶体管的通过栅极
公开(公告)号：US5646901A
公开(公告)日：1997-07-08
申请号：US625403
申请日：1996-03-26
申请人： Bradley A. Sharpe-Geisler , Jonathan Lin , Radu Barsan
发明人： Bradley A. Sharpe-Geisler , Jonathan Lin , Radu Barsan
IPC分类号： G11C16/04 , H01L27/115 , G11C7/00
CPC分类号： G11C16/045 , G11C16/0441 , H01L27/115 , G11C2216/10
摘要： An apparatus and method, the apparatus including an NMOS pass gate separating NMOS and PMOS transistors of a CMOS memory cell configured for tunneling during program and erase through the NMOS and PMOS transistors. The additional NMOS pass gate enables the CMOS memory cell to be utilized as a memory cell in a programmable logic device (PLD). The method includes steps for programming and erasing CMOS memory cells to prevent current leakage. The steps include applying specific voltages to the sources of the NMOS and PMOS transistors during program and erase, rather than leaving either source floating. Such voltages can be applied during program or erase without additional pass gates being connected to the sources of the PMOS or NMOS transistors of individual CMOS cells, or the additional pass gate provided between the drains of the PMOS and NMOS as in the described apparatus.
摘要翻译：一种装置和方法，该装置包括分离CMOS存储器单元的NMOS和NMOS晶体管的NMOS栅极，配置用于在编程和擦除期间通过NMOS和PMOS晶体管进行隧穿。附加的NMOS通道栅极使CMOS存储器单元可以用作可编程逻辑器件（PLD）中的存储器单元。该方法包括编程和擦除CMOS存储器单元以防止电流泄漏的步骤。这些步骤包括在编程和擦除期间将特定电压施加到NMOS和PMOS晶体管的源，而不是将源浮置。可以在编程或擦除期间施加这样的电压，而不需要在单独的CMOS单元的PMOS或NMOS晶体管的源极上连接附加的通路栅极，或者如所描述的装置中那样在PMOS和NMOS的漏极之间提供附加的通过栅极。

3. 发明授权

US06211022B1 Field leakage by using a thin layer of nitride deposited by chemical vapor deposition 有权
标题翻译：通过使用通过化学气相沉积沉积的薄层氮化物来改善漏电
公开(公告)号：US06211022B1
公开(公告)日：2001-04-03
申请号：US09241265
申请日：1999-02-01
申请人： Jonathan Lin , Radu Barsan , Sunil Mehta
发明人： Jonathan Lin , Radu Barsan , Sunil Mehta
IPC分类号： H01L21336
CPC分类号： H01L21/823481 , H01L21/3185 , H01L21/76202 , H01L21/823418
摘要： A nitride layer is deposited over a field oxide layer used to separate transistors formed in a substrate, the nitride layer serving to decrease transistor current leakage. The nitride layer has a dense lattice, effectively blocking H+ and Na+ penetration from overlying layers into the field oxide. Positive ions such as H+ and Na+ penetrating into the field oxide layer cause a p-substrate under the field oxide layer to become inverted or act like an n-type substrate, creating leakage current between source and drain regions of transistors which the field oxide layer separates. When high transistor threshold voltages such as 12 volts or more are desired, the nitride layer provides a significant reduction in current leakage.
摘要翻译：氮化物层沉积在用于分离形成在衬底中的晶体管的场氧化物层上，氮化物层用于减小晶体管电流泄漏。氮化物层具有致密的晶格，有效地阻止H +和Na +从上覆层渗透到场氧化物中。渗透到场氧化物层中的正离子如H +和Na +导致场氧化物层下的p衬底变为反相或类似于n型衬底，在晶体管的源极和漏极区域之间产生漏电流，其中场氧化物层分开。当需要诸如12伏特或更高的高晶体管阈值电压时，氮化物层显着降低电流泄漏。

4. 发明授权

US5700698A Method for screening non-volatile memory and programmable logic devices 失效
标题翻译：非易失性存储器和可编程逻辑器件的筛选方法
公开(公告)号：US5700698A
公开(公告)日：1997-12-23
申请号：US500295
申请日：1995-07-10
申请人： Radu Barsan , Jonathan Lin
发明人： Radu Barsan , Jonathan Lin
IPC分类号： G01R31/30 , G11C29/50 , H01L21/8247 , H01L27/118 , H01L21/8217 , H01L21/66
CPC分类号： H01L27/11517 , G01R31/30 , G11C29/50 , G11C29/50016 , H01L27/118 , G11C16/04 , G11C2029/5004
摘要： An improved method for screening a non-volatile memory device or programmable logic device including the steps of initially programming and then erasing a device for a predetermined number of cycles thereby providing a stressed device. Next, the stressed device is erased, providing an erased device. A first voltage value is measured across the floating gate of each cell of the erased device which is then stored for a predetermined period of time at a first predetermined temperature, providing a stored device. Next, the stored device is baked at a second predetermined temperature resulting in a baked device. Then, a second voltage value is measured across the floating gate of each cell of the baked device. Each of the first and the second voltage values are subtracted to provide a plurality of measured voltage drop values each of which are compared to an acceptable predetermined voltage drop value. The baked device is identified as defective and is discarded if any of the measured voltage drop values are greater than the acceptable predetermined voltage drop value. The first predetermined temperature is room temperature (i.e., 0.degree.-50.degree. C.), and the second predetermined temperature is greater than or equal to 250.degree. C.
摘要翻译：一种用于筛选非易失性存储器件或可编程逻辑器件的改进方法，包括以下步骤：首先对预定数量的循环进行编程，然后擦除器件，从而提供受压器件。接下来，应力装置被擦除，提供一个已擦除的装置。在擦除装置的每个单元的浮动栅极上测量第一电压值，然后在第一预定温度下存储预定时间段，从而提供存储的装置。接下来，将所存储的装置以第二预定温度进行烘烤，得到烘烤装置。然后，在烘烤设备的每个单元的浮动栅极上测量第二电压值。减去第一和第二电压值中的每一个以提供多个测量的电压降值，每个电压降与可接受的预定电压降值进行比较。被烘烤的装置被识别为有缺陷的，并且如果测量的电压降值中的任一个大于可接受的预定电压降值，则将其丢弃。第一预定温度为室温（即0℃-50℃），第二预定温度为大于或等于250℃。

5. 发明授权

US5908308A Use of borophosphorous tetraethyl orthosilicate (BPTEOS) to improve isolation in a transistor array 失效
标题翻译：使用硼磷酸四乙酯（BPTEOS）来改善晶体管阵列中的隔离
公开(公告)号：US5908308A
公开(公告)日：1999-06-01
申请号：US980883
申请日：1997-11-26
申请人： Radu Barsan , Jonathan Lin , Sunil Mehta
发明人： Radu Barsan , Jonathan Lin , Sunil Mehta
IPC分类号： H01L21/316 , H01L21/762 , H01L21/768 , H01L21/8234 , H11L21/8238 , H01L21/31 , H01L21/336 , H01L21/469 , H01L21/76
CPC分类号： H01L21/02129 , H01L21/31625 , H01L21/76202 , H01L21/76834 , H01L21/823475
摘要： Controlling the thickness of borophosphorous tetraethyl orthosilicate (BPTEOS) used as all or part of the first inter-layer dielectric (ILD0) in manufacturing a semiconductor device containing an array of transistors to control the field leakage between transistors. Reducing field leakage enables the thickness of field oxide, typically used to reduce field leakage, to be reduced to increase device density in the transistor array.
摘要翻译：控制在制造包含晶体管阵列以控制晶体管之间的场漏电的半导体器件中用作全部或部分第一层间电介质（ILD0）的硼磷酸四乙基原硅酸盐（BPTEOS）的厚度。减小场漏电流使得通常用于减少场漏电的场氧化物的厚度减小以增加晶体管阵列中的器件密度。

6. 发明授权

US5615150A Control gate-addressed CMOS non-volatile cell that programs through gates of CMOS transistors 失效
标题翻译：通过CMOS晶体管栅极编程的控制门寻址CMOS非易失性单元
公开(公告)号：US5615150A
公开(公告)日：1997-03-25
申请号：US551974
申请日：1995-11-02
申请人： Jonathan Lin , Radu Barsan
发明人： Jonathan Lin , Radu Barsan
IPC分类号： G11C16/04 , H01L27/115 , G11C11/34
CPC分类号： G11C16/045 , G11C16/0441 , H01L27/115 , G11C2216/10
摘要： An improved control gate-addressed CMOS memory cell is provided which allows for programming and erasing by tunneling through the gate oxides of the PMOS and NMOS transistors. The CMOS memory cell (400) includes a PMOS transistor (402), an NMOS transistor (403), and an NMOS pass transistor (405). A capacitor (430) has a first terminal coupled to a common floating gate (416) of the PMOS and NMOS transistors and has a second terminal coupled to a control gate node.
摘要翻译：提供了一种改进的控制栅极寻址CMOS存储单元，其允许通过穿过PMOS和NMOS晶体管的栅极氧化物的隧道编程和擦除。 CMOS存储单元（400）包括PMOS晶体管（402），NMOS晶体管（403）和NMOS传输晶体管（405）。电容器（430）具有耦合到PMOS和NMOS晶体管的公共浮动栅极（416）的第一端子，并且具有耦合到控制栅极节点的第二端子。

7. 发明授权

US5587945A CMOS EEPROM cell with tunneling window in the read path 失效
标题翻译： CMOS EEPROM单元在通道中具有隧道窗口
公开(公告)号：US5587945A
公开(公告)日：1996-12-24
申请号：US554092
申请日：1995-11-06
申请人： Jonathan Lin , Jack Z. Peng , Radu Barsan , Sunil Mehta
发明人： Jonathan Lin , Jack Z. Peng , Radu Barsan , Sunil Mehta
IPC分类号： G11C16/04 , H01L27/115 , G11C16/02
CPC分类号： G11C16/045 , G11C16/0441 , H01L27/115 , G11C2216/10
摘要： A CMOS memory cell including PMOS and NMOS transistors with a common floating gate. The CMOS memory cell includes a first capacitor connecting a first control voltage to the common floating gate and a second tunneling capacitor connected from the common floating gate to the source of the NMOS transistor. The tunneling capacitor includes a tunneling oxide region utilized to charge or discharge the floating gate during program or erase. The CMOS cell further includes a pass transistor with a source to drain path connecting the source of the NMOS transistor to a second control voltage.
摘要翻译： CMOS存储单元包括具有公共浮动栅极的PMOS和NMOS晶体管。 CMOS存储单元包括将第一控制电压连接到公共浮置栅极的第一电容器和从公共浮置栅极连接到NMOS晶体管的源极的第二隧穿电容器。隧道电容器包括用于在编程或擦除期间对浮动栅极充电或放电的隧道氧化物区域。 CMOS单元还包括具有将NMOS晶体管的源极连接到第二控制电压的源极到漏极路径的传输晶体管。

8. 发明授权

US08358889B2 Device fabrication with planar bragg gratings suppressing parasitic effects 有权
标题翻译：具有抑制寄生效应的平面布拉格光栅的器件制造
公开(公告)号：US08358889B2
公开(公告)日：2013-01-22
申请号：US12787652
申请日：2010-05-26
申请人： Radu Barsan , Lew Stolpner
发明人： Radu Barsan , Lew Stolpner
IPC分类号： G02B6/34
CPC分类号： G02B6/124 , B82Y20/00 , G02B6/12007 , G02B6/1225 , G02B6/132 , G02B6/134
摘要： The present invention relates to various methods of fabricating Planar Bragg Gratings (PBG) in a doped waveguide in a Planar Lightwave Circuit (PLC) device, suppressing unwanted parasitic grating effects during fabrication of the device. One approach to reduce parasitic gratings is to use a hard mask before the waveguide photolithography and etch, that results in a steeper sidewall angle that reduces or eliminates the parasitic grating effect. Another method of reducing parasitic grating effect is to deposit a layer of developable Bottom Anti Reflective Coating (BARC) prior to depositing the photo resist for waveguide etch. A third method of resisting parasitic gratings comprises using a planarizing undoped silica layer as a barrier layer on top of the core. During subsequent high temperature annealing germanium outdiffuses laterally into the cladding. The net effect is an optical waveguide with improved lateral uniformity because germanium diffusion smoothes out the sidewall roughness created during the waveguide reactive ion etch process. The undoped silica (SiO2) layer on top of the grating also serves the purpose of significantly reducing germanium outdiffusion from the core in the upward direction.
摘要翻译：本发明涉及在平面光波电路（PLC）器件中的掺杂波导中制造平面布拉格光栅（PBG）的各种方法，其在器件制造期间抑制不期望的寄生光栅效应。减少寄生光栅的一种方法是在波导光刻和蚀刻之前使用硬掩模，这导致更陡峭的侧壁角度，其减小或消除寄生光栅效应。减少寄生光栅效应的另一种方法是在淀积用于波导蚀刻的光致抗蚀剂之前沉积一层可显影的底部防反射涂层（BARC）。抵抗寄生光栅的第三种方法包括使用平坦化未掺杂的二氧化硅层作为核心顶部上的阻挡层。在随后的高温退火中锗向外扩散到包层中。净效应是具有改进的横向均匀性的光波导，因为锗扩散平滑了在波导反应离子蚀刻工艺期间产生的侧壁粗糙度。光栅顶部的未掺杂的二氧化硅（SiO 2）层也用于在向上的方向上显着地减少核的锗扩散。

9. 发明申请

US20100303411A1 DEVICE FABRICATION WITH PLANAR BRAGG GRATINGS SUPPRESSING PARASITIC EFFECTS 有权
标题翻译：具有平面布拉格光栅的器件制造抑制PARASITIC效应
公开(公告)号：US20100303411A1
公开(公告)日：2010-12-02
申请号：US12787652
申请日：2010-05-26
申请人： Radu Barsan , Lew Stolpner
发明人： Radu Barsan , Lew Stolpner
IPC分类号： G02B6/34 , G02B6/10
CPC分类号： G02B6/124 , B82Y20/00 , G02B6/12007 , G02B6/1225 , G02B6/132 , G02B6/134
摘要： The present invention relates to various methods of fabricating Planar Bragg Gratings (PBG) in a doped waveguide in a Planar Lightwave Circuit (PLC) device, suppressing unwanted parasitic grating effects during fabrication of the device. One approach to reduce parasitic gratings is to use a hard mask before the waveguide photolithography and etch, that results in a steeper sidewall angle that reduces or eliminates the parasitic grating effect. Another method of reducing parasitic grating effect is to deposit a layer of developable Bottom Anti Reflective Coating (BARC) prior to depositing the photo resist for waveguide etch. A third method of resisting parasitic gratings comprises using a planarizing undoped silica layer as a barrier layer on top of the core. During subsequent high temperature annealing germanium outdiffuses laterally into the cladding. The net effect is an optical waveguide with improved lateral uniformity because germanium diffusion smoothes out the sidewall roughness created during the waveguide reactive ion etch process. The undoped silica (SiO2) layer on top of the grating also serves the purpose of significantly reducing germanium outdiffusion from the core in the upward direction.
摘要翻译：本发明涉及在平面光波电路（PLC）器件中的掺杂波导中制造平面布拉格光栅（PBG）的各种方法，其在器件制造期间抑制不期望的寄生光栅效应。减少寄生光栅的一种方法是在波导光刻和蚀刻之前使用硬掩模，这导致更陡峭的侧壁角度，其减小或消除寄生光栅效应。减少寄生光栅效应的另一种方法是在淀积用于波导蚀刻的光致抗蚀剂之前沉积一层可显影的底部防反射涂层（BARC）。抵抗寄生光栅的第三种方法包括使用平坦化未掺杂的二氧化硅层作为核心顶部上的阻挡层。在随后的高温退火中锗向外扩散到包层中。净效应是具有改进的横向均匀性的光波导，因为锗扩散平滑了在波导反应离子蚀刻工艺期间产生的侧壁粗糙度。光栅顶部的未掺杂的二氧化硅（SiO 2）层也用于在向上的方向上显着地减少核的锗扩散。

10. 发明授权

US5854114A Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide 失效
公开(公告)号：US5854114A
公开(公告)日：1998-12-29
申请号：US947888
申请日：1997-10-09
申请人： Xiao-Yu Li , Radu Barsan , Sunil D. Mehta
发明人： Xiao-Yu Li , Radu Barsan , Sunil D. Mehta
IPC分类号： H01L21/762 , H01L21/8239 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11517 , H01L21/76229 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11526
摘要： A shallow trench isolation structure and a method for forming the same for use with non-volatile memory devices is provided so as to maintain sufficient data retention thereof. An epitaxial layer is formed on a top surface of a semiconductor substrate. A barrier oxide layer is formed on a top surface of the epitaxial layer. A nitride layer is deposited on a top surface of the barrier oxide layer. Trenches are formed through the epitaxial layer and the barrier oxide layer to a depth greater than 4000 .ANG. below the surface of the epitaxial layer so as to create isolation regions in order to electrically isolate active regions in the epitaxial layer. A liner oxide is formed on sidewalls and bottom of the trenches to a thickness between 750 .ANG. to 1500 .ANG.. As a result, leakage current in the sidewalls are prevented due to less thinning of the liner oxide layer by subsequent fabrication process steps.

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