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1. 发明申请

US20110299344A1 A NEW LOW VOLTAGE AND LOW POWER MEMORY CELL BASED ON NANO CURRENT VOLTAGE DIVIDER CONTROLLED LOW VOLTAGE SENSE MOSFET 有权
标题翻译：基于纳米电流分压器控制低电压感温MOSFET的新型低电压和低功耗存储器单元
公开(公告)号：US20110299344A1
公开(公告)日：2011-12-08
申请号：US12796031
申请日：2010-06-08
申请人： Jack Z. Peng , David Fong
发明人： Jack Z. Peng , David Fong
IPC分类号： G11C7/00
CPC分类号： G11C17/16 , G11C13/0004 , G11C13/0026 , G11C13/003 , G11C17/18 , G11C2213/74 , G11C2213/79
摘要： A memory cell has at least two word lines and at least two bit lines. The cell also has a first select device being connected to at least one word line and one bit line and a gate capacitor element connected to at least one word line and the first select device. The cell also has a sense device being connected in series to the gate capacitor element and the first select device. The sense device is connected to at least two bit lines.
摘要翻译：存储单元具有至少两个字线和至少两个位线。该单元还具有连接到至少一个字线和一个位线的第一选择器件以及连接到至少一个字线和第一选择器件的栅极电容器元件。该单元还具有与栅极电容器元件和第一选择器件串联连接的检测器件。感测装置连接到至少两个位线。

2. 发明授权

US5587945A CMOS EEPROM cell with tunneling window in the read path 失效
标题翻译： CMOS EEPROM单元在通道中具有隧道窗口
公开(公告)号：US5587945A
公开(公告)日：1996-12-24
申请号：US554092
申请日：1995-11-06
申请人： Jonathan Lin , Jack Z. Peng , Radu Barsan , Sunil Mehta
发明人： Jonathan Lin , Jack Z. Peng , Radu Barsan , Sunil Mehta
IPC分类号： G11C16/04 , H01L27/115 , G11C16/02
CPC分类号： G11C16/045 , G11C16/0441 , H01L27/115 , G11C2216/10
摘要： A CMOS memory cell including PMOS and NMOS transistors with a common floating gate. The CMOS memory cell includes a first capacitor connecting a first control voltage to the common floating gate and a second tunneling capacitor connected from the common floating gate to the source of the NMOS transistor. The tunneling capacitor includes a tunneling oxide region utilized to charge or discharge the floating gate during program or erase. The CMOS cell further includes a pass transistor with a source to drain path connecting the source of the NMOS transistor to a second control voltage.
摘要翻译： CMOS存储单元包括具有公共浮动栅极的PMOS和NMOS晶体管。 CMOS存储单元包括将第一控制电压连接到公共浮置栅极的第一电容器和从公共浮置栅极连接到NMOS晶体管的源极的第二隧穿电容器。隧道电容器包括用于在编程或擦除期间对浮动栅极充电或放电的隧道氧化物区域。 CMOS单元还包括具有将NMOS晶体管的源极连接到第二控制电压的源极到漏极路径的传输晶体管。

3. 发明授权

US08797820B2 Soft breakdown mode, low voltage, low power antifuse-based non-volatile memory cell 有权
标题翻译：软击穿模式，低电压，低功耗基于反熔丝的非易失性存储单元
公开(公告)号：US08797820B2
公开(公告)日：2014-08-05
申请号：US13563665
申请日：2012-07-31
申请人： Jack Z. Peng , David Fong
发明人： Jack Z. Peng , David Fong
IPC分类号： G11C17/18 , G11C17/16
CPC分类号： G11C17/165 , G11C17/16 , G11C17/18
摘要： A non-volatile memory cell using two transistors, a bit select and a sense device and an antifuse device. The antifuse device is implemented with a field-effect transistor operated to behave like an antifuse when the cell is selected and a modest programming voltage under 5.5 volts and a current under 5-μA is applied. Only a soft breakdown is needed in the thin gate oxide because a local sense transistor is used during read operations to detect the programming and amplify it for column sense amplifiers. Reading also only requires low voltages of about one volt.
摘要翻译：使用两个晶体管的非易失性存储单元，位选择和感测装置以及反熔丝装置。反熔断器件采用场效应晶体管来实现，当选择电池时，该场效应晶体管的工作方式就像反熔丝，并且施加5.5伏以下的适当编程电压和5-μA以下的电流。因为在读取操作期间使用局部检测晶体管来检测编程并将其放大为列读出放大器，所以在薄栅氧化层中仅需要软的击穿。读数也只需要约一伏特的低电压。

4. 发明申请

US20130208525A1 SOFT BREAKDOWN MODE, LOW VOLTAGE, LOW POWER ANTIFUSE-BASED NON-VOLATILE MEMORY CELL 有权
标题翻译：软断开模式，低电压，低功耗抗体基于非易失性存储器单元
公开(公告)号：US20130208525A1
公开(公告)日：2013-08-15
申请号：US13563665
申请日：2012-07-31
申请人： Jack Z. Peng , David Fong
发明人： Jack Z. Peng , David Fong
IPC分类号： G11C17/16
CPC分类号： G11C17/165 , G11C17/16 , G11C17/18
摘要： A non-volatile memory cell uses two transistors only, a bit select and a sense device. Each cell further comprises an antifuse device implemented, for example, with a field-effect transistor operated to behave like an antifuse when the cell is selected and a modest programming voltage under 5.5 volts and under 5-μA is applied. Only a soft breakdown is needed in the thin gate oxide because a local sense transistor is used during read operations to detect the programming and amplify it for column sense amplifiers. Reading also only requires low voltages of about one volt.
摘要翻译：非易失性存储单元仅使用两个晶体管，位选择和感测器件。每个单元进一步包括反熔丝装置，例如，当选择单元时，实施了场效应晶体管，该场效应晶体管被操作为表现得像反熔丝，并且施加了5.5伏和5-μA以下的适度的编程电压。因为在读取操作期间使用局部检测晶体管来检测编程并将其放大为列读出放大器，所以在薄栅氧化层中仅需要软的击穿。读数也只需要约一伏特的低电压。

5. 发明授权

US07907465B2 Electrically programmable fuse bit 有权
标题翻译：电可编程熔丝位
公开(公告)号：US07907465B2
公开(公告)日：2011-03-15
申请号：US12577084
申请日：2009-10-09
申请人： Jack Z. Peng , David Fong , Glen A. Rosendale
发明人： Jack Z. Peng , David Fong , Glen A. Rosendale
IPC分类号： G11C17/18 , G11C17/00 , H01H85/00
CPC分类号： G11C17/18
摘要： One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories, and as individual fuse bits for ID (identification), trimming, and other post-fabrication System-on-Chip (SoC) customization needs. Means are also provided for temporary data storage for design testing, etc. In alternative embodiments, using two differentially programmed fuses in a single memory cell, the selection and programming circuitry are merged.
摘要翻译：公开了一次性可编程（OTP）非易失性熔丝存储器单元，其不需要用于读取其数据内容的解码或寻址。每个保险丝存储单元的内容在其输出端被锁存并且始终可用，并且可以用于例如代码存储存储器，串行配置存储器，以及作为用于ID（识别），修整和其他后期处理的单个保险丝位。制造片上系统（SoC）定制需求。还提供了用于设计测试等的临时数据存储的手段。在替代实施例中，在单个存储器单元中使用两个差分编程的熔丝，合并选择和编程电路。

6. 发明申请

US20100091545A1 ELECTICALLY PROGRAMMABLE FUSE BIT 有权
标题翻译：可选可编程保险丝位
公开(公告)号：US20100091545A1
公开(公告)日：2010-04-15
申请号：US12577084
申请日：2009-10-09
申请人： Jack Z. Peng , David Fong , Glen A. Rosendale
发明人： Jack Z. Peng , David Fong , Glen A. Rosendale
IPC分类号： G11C17/16 , G11C7/10 , G11C8/00
CPC分类号： G11C17/18
摘要： One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories, and as individual fuse bits for ID (identification), trimming, and other post-fabrication System-on-Chip (SoC) customization needs. Means are also provided for temporary data storage for design testing, etc. In alternative embodiments, using two differentially programmed fuses in a single memory cell, the selection and programming circuitry are merged.
摘要翻译：公开了一次性可编程（OTP）非易失性熔丝存储器单元，其不需要用于读取其数据内容的解码或寻址。每个保险丝存储单元的内容在其输出端被锁存并且始终可用，并且可以用于例如代码存储存储器，串行配置存储器，以及作为用于ID（识别），修整和其他后期处理的单个保险丝位。制造片上系统（SoC）定制需求。还提供了用于设计测试等的临时数据存储的手段。在替代实施例中，在单个存储器单元中使用两个差分编程的熔丝，合并选择和编程电路。

7. 发明授权

US08780660B2 Spurious induced charge cleanup for one time programmable (OTP) memory 有权
标题翻译：一次可编程（OTP）存储器的杂散感应电荷清除
公开(公告)号：US08780660B2
公开(公告)日：2014-07-15
申请号：US13563657
申请日：2012-07-31
申请人： Jack Z. Peng
发明人： Jack Z. Peng
IPC分类号： G11C7/02
CPC分类号： G11C7/02 , G11C17/16 , G11C17/18
摘要： A high density, low voltage, and low-power one time programmable (OTP) memory is based on core cells with a one transistor design. A CLEAN pulse is directed to a single shunt device at the output of the column decoder so spurious charges that may have been stored in the floating nodes can be cleaned up. Such arrangement also allows for the simultaneous initialization of bit lines, data lines, and sensing lines to zero. Core area layout size is substantially reduced, and operational power requirements are exceeding low making these particularly suitable in HF and UHF RFID applications.
摘要翻译：高密度，低电压和低功耗一次可编程（OTP）存储器基于具有一个晶体管设计的核心单元。 CLEAN脉冲被引导到列解码器的输出处的单个分流装置，因此可以清除可能已经存储在浮动节点中的杂散电荷。这种布置还允许位线，数据线和感测线的同时初始化为零。核心区域布局尺寸大大降低，运行功率要求低，使得这些特别适用于HF和UHF RFID应用。

8. 发明授权

US08259518B2 Low voltage and low power memory cell based on nano current voltage divider controlled low voltage sense MOSFET 有权
标题翻译：基于纳米电流分压器的低压和低功率存储单元控制低电压感测MOSFET
公开(公告)号：US08259518B2
公开(公告)日：2012-09-04
申请号：US12796031
申请日：2010-06-08
申请人： Jack Z. Peng , David Fong
发明人： Jack Z. Peng , David Fong
IPC分类号： G11C7/00
CPC分类号： G11C17/16 , G11C13/0004 , G11C13/0026 , G11C13/003 , G11C17/18 , G11C2213/74 , G11C2213/79
摘要： A memory cell has at least two word lines and at least two bit lines. The cell also has a first select device being connected to at least one word line and one bit line and a gate capacitor element connected to at least one word line and the first select device. The cell also has a sense device being connected in series to the gate capacitor element and the first select device. The sense device is connected to at least two bit lines.
摘要翻译：存储单元具有至少两个字线和至少两个位线。该单元还具有连接到至少一个字线和一个位线的第一选择器件以及连接到至少一个字线和第一选择器件的栅极电容器元件。该单元还具有与栅极电容器元件和第一选择器件串联连接的检测器件。感测装置连接到至少两个位线。

9. 发明申请

US20130194885A1 SPURIOUS INDUCED CHARGE CLEANUP FOR ONE TIME PROGRAMMABLE (OTP) MEMORY 有权
标题翻译：用于一次可编程（OTP）存储器的SPURIOUS诱导电荷清除
公开(公告)号：US20130194885A1
公开(公告)日：2013-08-01
申请号：US13563657
申请日：2012-07-31
申请人： Jack Z. Peng
发明人： Jack Z. Peng
IPC分类号： G11C7/02
CPC分类号： G11C7/02 , G11C17/16 , G11C17/18
摘要： A high density, low voltage, and low-power one time programmable (OTP) memory is based on core cells with a one transistor design. A CLEAN pulse is directed to a single shunt device at the output of the column decoder so spurious charges that may have been stored in the floating nodes can be cleaned up. Such arrangement also allows for the simultaneous initialization of bit lines, data lines, and sensing lines to zero. Core area layout size is substantially reduced, and operational power requirements are exceeding low making these particularly suitable in HF and UHF RFID applications.
摘要翻译：高密度，低电压和低功耗一次可编程（OTP）存储器基于具有一个晶体管设计的核心单元。 CLEAN脉冲被引导到列解码器的输出处的单个分流装置，因此可以清除可能已经存储在浮动节点中的杂散电荷。这种布置还允许位线，数据线和感测线的同时初始化为零。核心区域布局尺寸大大降低，运行功率要求低，使得这些特别适用于HF和UHF RFID应用。

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