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1. 发明授权

US5546052A Phase locked loop circuit with phase/frequency detector which eliminates dead zones 失效
标题翻译：具有相位/频率检测器的锁相环电路，可消除死区
公开(公告)号：US5546052A
公开(公告)日：1996-08-13
申请号：US298639
申请日：1994-11-10
申请人： John S. Austin , Ilya I. Novof , Donald E. Strayer , Stephen D. Wyatt
发明人： John S. Austin , Ilya I. Novof , Donald E. Strayer , Stephen D. Wyatt
IPC分类号： H03D13/00 , H03K3/0231 , H03L7/089 , H03L7/093 , H03L7/095 , H03L7/10
CPC分类号： H03L7/095 , H03K3/0231 , H03L7/0893 , H03D13/004 , H03L2207/06 , H03L7/0896 , H03L7/0898 , Y10S331/02
摘要： A phase locked loop circuit is provided which includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which do not have "dead zones". A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has a voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is also provided which reduces jitter in the current controlled oscillator output in the locked phase. Also, a lock indicator is provided which is time independent, and provides a lock indication when the loop enters the locked condition.
摘要翻译：提供了一种锁相环电路，其包括相位/频率检测器，其使用分频器电路和来自时钟分配树的反馈来产生不具有“死区”的INC和DEC脉冲。一对电荷泵接收INC和DEC脉冲。一个电荷泵是差分泵，并具有电压控制的共模反馈电路，以保持共模控制电压。通过该电荷泵将差分电流输出到环路滤波电容器。另一个电荷泵是一个单端输出泵，它向电流控制振荡器提供电流，该电流控制振荡器也接收电压到电流转换器的输入。电流控制振荡器包括与输入电流的大小成反比变化的可变电阻负载。还提供了抖动控制电路，其减少锁定相中的电流控制振荡器输出中的抖动。而且，提供了与时间无关的锁定指示器，并且当环路进入锁定状态时提供锁定指示。

2. 发明授权

US5513225A Resistorless phase locked loop circuit employing direct current injection 失效
标题翻译：采用直流注入的无电阻锁相环电路
公开(公告)号：US5513225A
公开(公告)日：1996-04-30
申请号：US298632
申请日：1994-08-31
申请人： Ram Kelkar , Ilya I. Novof , Donald E. Strayer , Stephen D. Wyatt
发明人： Ram Kelkar , Ilya I. Novof , Donald E. Strayer , Stephen D. Wyatt
IPC分类号： H03L7/093 , H03L7/089 , H03L7/095 , H03L7/099 , H03L7/10 , H03D3/24
CPC分类号： H03L7/0995 , H03L7/0893 , H03L7/095 , H03L2207/06 , H03L7/0896 , H03L7/0898
摘要： A phase locked loop circuit includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which have no "dead zone". A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is provided which reduces jitter in the current controlled oscillator output in the locked phase. Also, a lock indicator is provided which is time independent, and provides a lock indication when the loop enters the locked condition. The circuits for these components are described in detail.
摘要翻译：锁相环电路包括相位/频率检测器，该相位/频率检测器使用分频器电路和来自时钟分配树的反馈来产生没有“死区”的INC和DEC脉冲。一对电荷泵接收INC和DEC脉冲。一个电荷泵是差分泵，并具有电压控制的共模反馈电路，以保持共模控制电压。通过该电荷泵将差分电流输出到环路滤波电容器。另一个电荷泵是一个单端输出泵，它向电流控制振荡器提供电流，该电流控制振荡器也接收电压到电流转换器的输入。电流控制振荡器包括与输入电流的大小成反比变化的可变电阻负载。提供了一种抖动控制电路，可减少锁定相中当前受控振荡器输出的抖动。而且，提供了与时间无关的锁定指示器，并且当环路进入锁定状态时提供锁定指示。详细描述这些部件的电路。

3. 发明授权

US5491439A Method and apparatus for reducing jitter in a phase locked loop circuit 失效
标题翻译：减少锁相环电路抖动的方法和装置
公开(公告)号：US5491439A
公开(公告)日：1996-02-13
申请号：US298695
申请日：1994-08-31
申请人： Ram Kelkar , Ilya I Novof , Stephen D. Wyatt
发明人： Ram Kelkar , Ilya I Novof , Stephen D. Wyatt
IPC分类号： H03D13/00 , H03K3/0231 , H03L7/089 , H03L7/093 , H03L7/095 , H03L7/10 , H03L7/06
CPC分类号： H03L7/095 , H03K3/0231 , H03L7/0893 , H03D13/004 , H03L2207/06 , H03L7/0896 , H03L7/0898 , Y10S331/02
摘要： A phase locked loop circuit includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which have no "dead zone". A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is provided which reduces jitter in the current controlled oscillator output in the locked phase. Also, a lock indicator is provided which is time independent, and provides a lock indication when the loop enters the locked condition.
摘要翻译：锁相环电路包括相位/频率检测器，该相位/频率检测器使用分频器电路和来自时钟分配树的反馈来产生没有“死区”的INC和DEC脉冲。一对电荷泵接收INC和DEC脉冲。一个电荷泵是差分泵，并具有电压控制的共模反馈电路，以保持共模控制电压。通过该电荷泵将差分电流输出到环路滤波电容器。另一个电荷泵是一个单端输出泵，它向电流控制振荡器提供电流，该电流控制振荡器也接收电压到电流转换器的输入。电流控制振荡器包括与输入电流的大小成反比变化的可变电阻负载。提供了一种抖动控制电路，可减少锁定相中当前受控振荡器输出的抖动。而且，提供了与时间无关的锁定指示器，并且当环路进入锁定状态时提供锁定指示。

4. 发明授权

US5541442A Integrated compact capacitor-resistor/inductor configuration 失效
标题翻译：集成紧凑型电容电阻/电感器配置
公开(公告)号：US5541442A
公开(公告)日：1996-07-30
申请号：US298685
申请日：1994-08-31
申请人： Richard F. Keil , Ram Kelkar , Ilya I. Novof , Jeffery H. Oppold , Kenneth D. Short , Stephen D. Wyatt
发明人： Richard F. Keil , Ram Kelkar , Ilya I. Novof , Jeffery H. Oppold , Kenneth D. Short , Stephen D. Wyatt
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/08 , H01L27/108 , H01L29/00
CPC分类号： H01L27/08
摘要： An improved configuration of a capacitor formed with FET technology and a resistor and/or conductor is provided. In this configuration a capacitor is formed in which the diffusion zone of the substrate is used as one plate of the capacitor and what would normally be the gate electrode of an FET is used as the other plate of the capacitor, with the two plates being separated by a conventional thin dielectric gate oxide layer. An insulator, such as silicon dioxide overlays the gate electrode, and electrical connections to the gate electrode and diffusion zone are made through the insulator to allow the two plates of the capacitor to be connected to various devices or components as required. The top surface of this insulation layer is also used to form metal resistors. Depending on the value of required resistance, a second insulating layer may be used and a second level of metal used to connect segments of the resistors formed on the first layer of metal to form a longer resistor. This second layer of metal may also be used to form inductors. Moreover both inductors and resistors can be formed; however this may require a third layer of metal for connection purposes.
摘要翻译：提供了由FET技术形成的电容器和电阻器和/或导体的改进配置。在该配置中，形成电容器，其中衬底的扩散区被用作电容器的一个板，并且通常将FET的栅电极用作电容器的另一个板，两个板被分离通过常规的薄介电栅极氧化物层。诸如二氧化硅的绝缘体覆盖栅电极，并且通过绝缘体制造到栅电极和扩散区的电连接，以允许电容器的两个板根据需要连接到各种装置或部件。该绝缘层的顶表面也用于形成金属电阻。根据所需电阻的值，可以使用第二绝缘层，并且使用第二级金属来连接形成在第一金属层上的电阻器的部分，以形成更长的电阻。该第二层金属也可用于形成电感器。此外，可以形成电感器和电阻器; 然而，这可能需要用于连接目的的第三层金属。

5. 发明授权

US07583116B2 High output resistance, wide swing charge pump 失效
标题翻译：高输出电阻，宽摆电荷泵
公开(公告)号：US07583116B2
公开(公告)日：2009-09-01
申请号：US11833500
申请日：2007-08-03
申请人： Stephen D. Wyatt , Tian Xia
发明人： Stephen D. Wyatt , Tian Xia
IPC分类号： H03L7/06
CPC分类号： H03L7/0896 , H02M3/07 , H03L7/18
摘要： Disclosed are current sink and source circuits, a charge pump that incorporates them, and a phase locked loop that incorporates the charge pump. The current sink and source circuits each have a current mirror that biases a transistor connected to an output node. These circuits each further have a two-stage feedback amplifier to sense the current mirror drain voltage and to control the transistor gate voltage in order to stabilize the current mirror drain voltage independent of output voltage at the output node. The amplifier also increases output resistance at the output node. This configuration allows for a wide operation voltage range and ensures good circuit performance under a very low power supply. A charge pump that incorporates these circuits generates highly matched charging and discharging currents. A PLL that incorporates this charge pump exhibits minimal bandwidth shifts and minimal locking speed and jitter performance degradation.
摘要翻译：公开了当前的电流源和源极电路，它们组合的电荷泵以及结合电荷泵的锁相环。电流源和电源电路各自具有偏置连接到输出节点的晶体管的电流镜。这些电路还具有两级反馈放大器以感测电流镜漏极电压并控制晶体管栅极电压，以便稳定电流镜漏极电压，而与输出节点处的输出电压无关。放大器还增加输出节点的输出电阻。该配置允许宽的工作电压范围，并在非常低的电源下确保良好的电路性能。集成这些电路的电荷泵产生高度匹配的充电和放电电流。集成该电荷泵的PLL具有最小的带宽偏移和最小的锁定速度和抖动性能下降。

6. 发明申请

US20090033407A1 STRUCTURE FOR A HIGH OUTPUT RESISTANCE, WIDE SWING CHARGE PUMP 失效
标题翻译：高输出电阻结构，宽摆动充电泵
公开(公告)号：US20090033407A1
公开(公告)日：2009-02-05
申请号：US11845249
申请日：2007-08-27
申请人： Stephen D. Wyatt , Tian Xia
发明人： Stephen D. Wyatt , Tian Xia
IPC分类号： G05F1/10
CPC分类号： H03L7/0896 , H02M3/07 , H03L7/18
摘要： Disclosed are design structures for current sink and source circuits, a charge pump, and a phase locked loop. The current sink and source circuits each have a current mirror that biases a transistor connected to an output node. These circuits each further have a two-stage feedback amplifier to sense the current mirror drain voltage and to control the transistor gate voltage in order to stabilize the current mirror drain voltage independent of output voltage at the output node. The amplifier also increases output resistance at the output node. This configuration allows for a wide operation voltage range and ensures good circuit performance under a very low power supply. A charge pump that incorporates these circuits generates highly matched charging and discharging currents. A PLL that incorporates this charge pump exhibits minimal bandwidth shifts and minimal locking speed and jitter performance degradation.
摘要翻译：公开了电流吸收和电源电路，电荷泵和锁相环的设计结构。电流源和电源电路各自具有偏置连接到输出节点的晶体管的电流镜。这些电路还具有两级反馈放大器以感测电流镜漏极电压并控制晶体管栅极电压，以便稳定电流镜漏极电压，而与输出节点处的输出电压无关。放大器还增加输出节点的输出电阻。该配置允许宽的工作电压范围，并在非常低的电源下确保良好的电路性能。集成这些电路的电荷泵产生高度匹配的充电和放电电流。集成该电荷泵的PLL具有最小的带宽偏移和最小的锁定速度和抖动性能下降。

7. 发明申请

US20080012549A1 CIRCUIT AND METHOD FOR ON-CHIP JITTER MEASUREMENT 有权
标题翻译：芯片抖动测量的电路和方法
公开(公告)号：US20080012549A1
公开(公告)日：2008-01-17
申请号：US11424881
申请日：2006-06-19
申请人： Brandon R. Kam , Stephen D. Wyatt
发明人： Brandon R. Kam , Stephen D. Wyatt
IPC分类号： G01R23/175 , H03L7/06
CPC分类号： G01R31/31709 , G01R29/26 , H03L7/07 , H03L7/0814
摘要： Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.
摘要翻译：本文公开了改进的内置自测试（BIST）电路和用于测量时钟信号的相位和/或周期到周期抖动的相关方法的实施例。 BIST电路的实施例实现了可变游标数字延迟锁定线方法。具体地，BIST电路的实施例包括数字延迟锁定环和游标延迟线，分别用于电路的粗调和微调部分。此外，BIST电路是可变的，因为电路的分辨率由芯片变为芯片，而数字是由标准数字逻辑元件实现的。

8. 发明授权

US08126041B2 Circuit and method for on-chip jitter measurement 有权
标题翻译：用于片上抖动测量的电路和方法
公开(公告)号：US08126041B2
公开(公告)日：2012-02-28
申请号：US11874960
申请日：2007-10-19
申请人： Brandon R. Kam , Stephen D. Wyatt
发明人： Brandon R. Kam , Stephen D. Wyatt
IPC分类号： H04B17/00
CPC分类号： G01R31/31709 , G01R29/26 , H03L7/07 , H03L7/0814
摘要： Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.
摘要翻译：本文公开了改进的内置自测试（BIST）电路和用于测量时钟信号的相位和/或周期到周期抖动的相关方法的实施例。 BIST电路的实施例实现了可变游标数字延迟锁定线方法。具体地，BIST电路的实施例包括数字延迟锁定环和游标延迟线，分别用于电路的粗调和微调部分。此外，BIST电路是可变的，因为电路的分辨率由芯片变为芯片，而数字是由标准数字逻辑元件实现的。

9. 发明授权

US07932774B2 Structure for intrinsic RC power distribution for noise filtering of analog supplies 有权
标题翻译：用于模拟电源噪声滤波的固有RC功率分配的结构
公开(公告)号：US07932774B2
公开(公告)日：2011-04-26
申请号：US12053958
申请日：2008-03-24
申请人： Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
发明人： Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
IPC分类号： H03K5/00
CPC分类号： G05F1/56
摘要： A design structure for intrinsic RC power distribution for noise filtering of analog supplies. The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes a voltage regulator; a variable resistor coupled to the voltage regulator; and a performance monitor and control circuit providing a feedback loop to the variable resistor.
摘要翻译：用于模拟电源噪声滤波的固有RC功率分配的设计结构。该设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。设计结构包括电压调节器; 耦合到电压调节器的可变电阻器; 以及向可变电阻器提供反馈回路的性能监视和控制电路。

10. 发明授权

US07701270B2 Structure for a high output resistance, wide swing charge pump 失效
标题翻译：结构为高输出电阻，宽摆电荷泵
公开(公告)号：US07701270B2
公开(公告)日：2010-04-20
申请号：US11845249
申请日：2007-08-27
申请人： Stephen D. Wyatt , Tian Xia
发明人： Stephen D. Wyatt , Tian Xia
IPC分类号： H03L7/06
CPC分类号： H03L7/0896 , H02M3/07 , H03L7/18
摘要： Disclosed are design structures for current sink and source circuits, a charge pump, and a phase locked loop. The current sink and source circuits each have a current mirror that biases a transistor connected to an output node. These circuits each further have a two-stage feedback amplifier to sense the current mirror drain voltage and to control the transistor gate voltage in order to stabilize the current mirror drain voltage independent of output voltage at the output node. The amplifier also increases output resistance at the output node. This configuration allows for a wide operation voltage range and ensures good circuit performance under a very low power supply. A charge pump that incorporates these circuits generates highly matched charging and discharging currents. A PLL that incorporates this charge pump exhibits minimal bandwidth shifts and minimal locking speed and jitter performance degradation.
摘要翻译：公开了电流吸收和电源电路，电荷泵和锁相环的设计结构。电流源和电源电路各自具有偏置连接到输出节点的晶体管的电流镜。这些电路还具有两级反馈放大器以感测电流镜漏极电压并控制晶体管栅极电压，以便稳定电流镜漏极电压，而与输出节点处的输出电压无关。放大器还增加输出节点的输出电阻。该配置允许宽的工作电压范围，并在非常低的电源下确保良好的电路性能。集成这些电路的电荷泵产生高度匹配的充电和放电电流。集成该电荷泵的PLL具有最小的带宽偏移和最小的锁定速度和抖动性能下降。

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