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1. 发明授权

US06284669B1 Power transistor with silicided gate and contacts 有权
标题翻译：功率晶体管采用硅化栅和触点
公开(公告)号：US06284669B1
公开(公告)日：2001-09-04
申请号：US09168194
申请日：1998-10-07
申请人： John P. Erdeljac , Louis N. Hutter , Jeffrey P. Smith , Han-Tzong Yuan , Jau-Yuann Yang , Taylor R. Efland , C. Matthew Thompson , John K. Arch , Mary Ann Murphy
发明人： John P. Erdeljac , Louis N. Hutter , Jeffrey P. Smith , Han-Tzong Yuan , Jau-Yuann Yang , Taylor R. Efland , C. Matthew Thompson , John K. Arch , Mary Ann Murphy
IPC分类号： H01L21302
CPC分类号： H01L29/66659 , H01L29/456 , H01L29/7835
摘要： A power field effect transistor is disclosed that includes polysilicon gate bodies (40) and (42), which includes platinum silicide contact layers (74) and (78) disposed on the outer surfaces of bodies (40) and (42), respectively. In addition, the device comprises an n+drain region (64) which also has a platinum silicide drain contact layer (76) formed on its outer surface and platinum silicide source contact layers (75) and (77). During formation, sidewall spacers (50) and (52), as well as mask bodies (70) and (72) are used to ensure that platinum silicide layer (76) spaced apart from both gate bodies (40) and (42) and platinum silicide gate contact layers (74) and (78).
摘要翻译：公开了一种功率场效应晶体管，其包括分别设置在主体（40）和（42）的外表面上的铂硅化物接触层（74）和（78）的多晶硅栅极体（40）和（42）。另外，该器件还包括在其外表面上形成有铂硅化物漏极接触层（76）和铂硅化物源极接触层（75）和（77）的n +漏极区域（64）。在形成期间，侧壁间隔物（50）和（52）以及掩模体（70）和（72）用于确保与两个闸门体（40）和（42）间隔开的铂硅化物层（76）和铂硅化物栅极接触层（74）和（78）。

2. 发明授权

US5342795A Method of fabricating power VFET gate-refill 失效
标题翻译：制造功率VFET栅极补充的方法
公开(公告)号：US5342795A
公开(公告)日：1994-08-30
申请号：US153121
申请日：1993-11-15
申请人： Han-Tzong Yuan , Donald L. Plumton , Tae S. Kim , Jau-Yuann Yang
发明人： Han-Tzong Yuan , Donald L. Plumton , Tae S. Kim , Jau-Yuann Yang
IPC分类号： H01L21/335 , H01L21/337 , H01L29/207 , H01L29/772 , H01L21/44
CPC分类号： H01L29/66454 , H01L29/207 , H01L29/66924 , H01L29/7722 , Y10S148/04
摘要： This is a method of forming a vertical transistor device comprising: forming an n-type first drain/source layer 42; patterning a portion of the first drain/source layer 42 to form a channel 44 and a trench; forming a p-type gate structure 46 in the trench; and forming a n-type second drain/source layer 48 over the gate structure 46 and the channel 44; contacting the gate structure 54; forming p-ohmic contact to the gate structure 56; forming n-ohmic source contact 54; and forming n-ohmic drain contact 58. Other devices and methods are also disclosed.
摘要翻译：这是形成垂直晶体管器件的方法，包括：形成n型第一漏极/源极层42; 图案化第一漏极/源极层42的一部分以形成沟道44和沟槽; 在沟槽中形成p型栅极结构46; 以及在栅极结构46和沟道44上形成n型第二漏极/源极层48; 接触门结构54; 与门结构56形成p欧姆接触; 形成n-欧姆源触点54; 并形成n欧姆漏极触点58.还公开了其它装置和方法。

3. 发明授权

US5223449A Method of making an integrated circuit composed of group III-V compound field effect and bipolar semiconductors 失效
标题翻译：制备由III-V族化合物场效应和双极半导体组成的集成电路的方法
公开(公告)号：US5223449A
公开(公告)日：1993-06-29
申请号：US692326
申请日：1991-04-26
申请人： Francis J. Morris , Donald L. Plumton , Jau-Yuann Yang , Han-Tzong Yuan
发明人： Francis J. Morris , Donald L. Plumton , Jau-Yuann Yang , Han-Tzong Yuan
IPC分类号： H01L27/06 , H01L27/082
CPC分类号： H01L27/0623 , H01L27/0605 , H01L27/0826 , Y10S148/009 , Y10S148/072
摘要： Integrated circuits and fabrication methods incorporating both NPN (192, 194, 210) and PNP (196, 121, 124) heterojunction bipolar transistors together with N channel (198, 200, 216, 218) and P channel (202, 204, 220, 222) JFETs on a single substrate as illustrated in FIG. 10. MESFETs may be also be integrated on the substrate.
摘要翻译：集成电路和制造方法将NPN（192,194,210）和PNP（196,121,124）异构双极晶体管与N沟道（198,200,216,218）和P沟道（202,204,220） 222）如图1所示的单个衬底上的JFET。 MESFET也可以集成在衬底上。

4. 发明授权

US6008519A Vertical transistor and method 失效
标题翻译：垂直晶体管和方法
公开(公告)号：US6008519A
公开(公告)日：1999-12-28
申请号：US990549
申请日：1997-12-15
申请人： Han-Tzong Yuan , Donald L. Plumpton , Jau-Yuann Yang , Tae S. Kim
发明人： Han-Tzong Yuan , Donald L. Plumpton , Jau-Yuann Yang , Tae S. Kim
IPC分类号： H01L21/335 , H01L29/772 , H01L29/76 , H01L29/74 , H01L29/80
CPC分类号： H01L29/66416 , H01L29/7722
摘要： A vertical transistor (70) comprising a first semiconductor layer (14) of a first conductive type. A gate structure (32) of a second conductive type disposed on the first semiconductor layer (14). The gate structure (32) may include a plurality of gates (38) separated by channels (40). A second semiconductor layer (50) of the first conductive type may be disposed over the gate structure (32) and in the channels (40). An arresting element (36) may be disposed between and upper surface of the gates (38) and the second semiconductor layer (50). A void (52) may be formed in the second semiconductor layer (50) over the gate (38).
摘要翻译：一种包括第一导电类型的第一半导体层（14）的垂直晶体管（70）。设置在第一半导体层（14）上的第二导电类型的栅极结构（32）。栅极结构（32）可以包括由通道（40）分开的多个栅极（38）。第一导电类型的第二半导体层（50）可以设置在栅极结构（32）上和通道（40）中。止动元件（36）可以设置在栅极（38）和第二半导体层（50）的上表面之间。可以在栅极（38）上的第二半导体层（50）中形成空穴（52）。

5. 发明授权

US5548141A Bipolar transistor having a self emitter contact aligned 失效
标题翻译：具有自发射体触点对准的双极晶体管
公开(公告)号：US5548141A
公开(公告)日：1996-08-20
申请号：US441847
申请日：1995-05-16
申请人： Francis J. Morris , Jau-Yuann Yang , Donald L. Plumton , Han-Tzong Yuan
发明人： Francis J. Morris , Jau-Yuann Yang , Donald L. Plumton , Han-Tzong Yuan
IPC分类号： H01L29/73 , H01L21/331 , H01L29/205 , H01L29/737 , H01L29/161
CPC分类号： H01L29/66318 , H01L29/7371 , Y10S148/011 , Y10S148/072
摘要： A method of self aligning an emitter contact includes forming a base layer (18) on a portion of a collector layer (16). An interface layer (22) is formed on the base layer (18) such that a portion of the base layer (18) remains exposed. An emitter layer (24) is formed on the collector layer (16), the interface layer (22), and the exposed portion of the base layer (18). An emitter cap layer (26) is formed on the emitter layer (24) over the previously exposed area of the base layer (18). An insulating layer (28) is formed on the interface layer (22). An emitter contact (36) is formed on the emitter cap layer (26) at the previously exposed area of the base layer (18). The insulating layer (28) isolates the emitter contact (36) from the base layer (18) and a subsequently formed base contact (38). The insulating layer (28) ensures isolation between the emitter contact (36) and the base contact (38) despite misalignment of the emitter contact (36) during formation.
摘要翻译：自发对准发射极接触的方法包括在集电极层（16）的一部分上形成基极层（18）。界面层（22）形成在基底层（18）上，使得基底层（18）的一部分保持暴露。发射极层（24）形成在集电层（16），界面层（22）和基层（18）的露出部分上。在基底层（18）的预先暴露的区域上的发射极层（24）上形成发射极覆盖层（26）。绝缘层（28）形成在界面层（22）上。在基底层（18）的预先暴露的区域处，在发射极盖层（26）上形成发射极触点（36）。绝缘层（28）将发射极触点（36）与基底层（18）和随后形成的基部触点（38）隔离开来。绝缘层（28）确保发射极触点（36）和基极触点（38）之间的隔离，尽管发射极触点（36）在形成期间未对准。

6. 发明授权

US5420052A Method of fabricating a semiplanar heterojunction bipolar transistor 失效
标题翻译：制造半平面异质结双极晶体管的方法
公开(公告)号：US5420052A
公开(公告)日：1995-05-30
申请号：US230357
申请日：1994-04-19
申请人： Francis J. Morris , Jau-Yuann Yang , Donald L. Plumton , Han-Tzong Yuan
发明人： Francis J. Morris , Jau-Yuann Yang , Donald L. Plumton , Han-Tzong Yuan
IPC分类号： H01L29/73 , H01L21/331 , H01L29/205 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66318 , H01L29/7371 , Y10S148/072
摘要： A method of fabricating a semiplanar heterojunction bipolar transistor (10) includes forming a subcollector layer (12) and a collector layer (16) onto a substrate layer (14). A collector implant plug (18) is selectively implanted to connect the subcollector layer (12) to the surface of the heterojunction bipolar transistor (10). A second epitaxial growth process causes a base layer (22), an emitter layer (24), and an emitter cap layer (26) to form on the collector layer (16) and the collector implant plug (18). By this process, the base layer (22) is not exposed to subsequent harmful fabrication steps. A base plug region (28) is selectively implanted to connect the base layer (22) to the surface of the heterojunction bipolar transistor (10). A base contact (32) and an emitter contact (30) are selectively formed within the heterojunction region on the base plug region (28) and the emitter cap layer (26), respectively. Lateral parasitic diodes between the base contact (32) and the emitter contact (30) are etched away to isolate the base contact (32) from the emitter contact (30). The emitter cap layer (26), the emitter layer (24), and the base layer (22) are removed from the vicinity of the collector implant plug (18) to allow formation of the collector contact (34).
摘要翻译：制造半平面异质结双极晶体管（10）的方法包括在衬底层（14）上形成子集电极层（12）和集电极层（16）。选择性地注入集电极注入插头（18）以将子集电极层（12）连接到异质结双极晶体管（10）的表面。第二外延生长工艺使得在集电极层（16）和集电极植入插头（18）上形成基极层（22），发射极层（24）和发射极盖层（26）。通过该过程，基层（22）不暴露于随后的有害制造步骤。选择性地注入基座区域（28）以将基极层（22）连接到异质结双极晶体管（10）的表面。基极触点（32）和发射极触点（30）分别选择性地形成在基插塞区域（28）和发射极盖层（26）上的异质结区域内。基极触点（32）和发射极触点（30）之间的侧向寄生二极管被蚀刻掉以将基极触点（32）与发射极触点（30）隔离。发射极帽层（26），发射极层（24）和基底层（22）从集电极植入插头（18）的附近被去除，以形成集电极触点（34）。

7. 发明授权

US5407842A Enhanced performance bipolar transistor process 失效
标题翻译：增强性能双极晶体管工艺
公开(公告)号：US5407842A
公开(公告)日：1995-04-18
申请号：US255502
申请日：1994-06-08
申请人： Francis J. Morris , Jau-Yuann Yang , Donald L. Plumton , Han-Tzong Yuan
发明人： Francis J. Morris , Jau-Yuann Yang , Donald L. Plumton , Han-Tzong Yuan
IPC分类号： H01L21/331 , H01L27/06 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66318 , H01L27/0605 , H01L29/7371 , Y10S148/01 , Y10S148/072
摘要： This is a method of forming a bipolar transistor comprising: forming a subcollector layer, having a doping type and a doping level, on a substrate; forming a first layer, of the same doping type and a lower doping level than the subcollector layer, over the subcollector layer; increasing the doping level of first and second regions of the first layer; forming a second layer, of the same doping type and a lower doping level than the subcollector layer, over the first layer; increasing the doping level of a first region of the second layer which is over the first region of the first layer, whereby the subcollector layer, the first region of the first layer and the first region of the second layer are the collector of the transistor; forming a base layer over the second layer of an opposite doping type than the subcollector layer; and forming an emitter layer of the same doping type as the subcollector layer over the base layer. Other devices and methods are also disclosed.
摘要翻译：这是一种形成双极晶体管的方法，包括：在衬底上形成具有掺杂类型和掺杂水平的子集电极层; 在子集电极层上形成与子集电极层相同的掺杂类型和较低掺杂水平的第一层; 增加第一层的第一和第二区域的掺杂水平; 在第一层上形成与子集电极层相同的掺杂类型和较低掺杂水平的第二层; 增加在第一层的第一区域之上的第二层的第一区域的掺杂水平，由此子集电极层，第一层的第一区域和第二层的第一区域是晶体管的集电极; 在与所述子集电极层相反的掺杂类型的第二层上形成基底层; 并且在基底层上形成与子集电极层相同的掺杂类型的发射极层。还公开了其它装置和方法。

8. 发明授权

US5909110A Integrated voltage regulator circuit with vertical transistor 失效
标题翻译：具有垂直晶体管的集成稳压电路
公开(公告)号：US5909110A
公开(公告)日：1999-06-01
申请号：US989840
申请日：1997-12-12
申请人： Han-Tzong Yuan , Albert H. Taddiken , Donald L. Plumton , Jau-Yuann Yang
发明人： Han-Tzong Yuan , Albert H. Taddiken , Donald L. Plumton , Jau-Yuann Yang
IPC分类号： G05F1/56 , G05F1/40
CPC分类号： G05F1/56
摘要： A voltage regulator (10) comprising a vertical channel transistor (12). The vertical channel transistor (12) may have a gate (16), a voltage input terminal (18), and a voltage output terminal (20). A reference voltage supply (14) may be coupled to the gate (16).
摘要翻译：一种包括垂直沟道晶体管（12）的电压调节器（10）。垂直沟道晶体管（12）可以具有栅极（16），电压输入端子（18）和电压输出端子（20）。参考电压源（14）可以耦合到栅极（16）。

9. 发明授权

US5822473A Integrated microchip chemical sensor 失效
标题翻译：集成微芯片化学传感器
公开(公告)号：US5822473A
公开(公告)日：1998-10-13
申请号：US808816
申请日：1997-02-28
申请人： Gregory Anton Magel , Terrance Gus McDonald , Jau-Yuann Yang , Han-Tzong Yuan
发明人： Gregory Anton Magel , Terrance Gus McDonald , Jau-Yuann Yang , Han-Tzong Yuan
IPC分类号： G01N21/77 , G02B6/12 , G02B6/26
CPC分类号： G01N21/7703 , G02B6/12004
摘要： An optical device for sensing properties in an environment such as the presence of a substance or chemical in the zone to be monitored using optical components integrated on a microchip base or substrate. A preferred embodiment introduces a method for fabricating a miniature microchip chemical sensor by integrating a GaAs LED 14 with a polyimide waveguide 48 and a silicon photosensor 16 on the same chip. Light 18 is emitted at the edge of the GaAs LED 14. A portion of the light propagates is detected by a PIN diode 16. A chemical sensitive material 50 is coated on top of a polyimide waveguide 48. When the gas or chemical to which the material is sensitive appears, the light transmitted from the polyimide to air increases, thus the total signal sensed by the photodetector decreases, whereby the change in light signal indicates detection.
摘要翻译：一种光学装置，用于使用集成在微芯片基座或基板上的光学元件在诸如物体或化学物质存在的环境中感测特性。优选实施例通过在同一芯片上集成GaAs LED 14与聚酰亚胺波导48和硅光电传感器16来引入制造微型微芯片化学传感器的方法。灯18在GaAs LED 14的边缘处发射。一部分光传播由PIN二极管16检测。化学敏感材料50涂覆在聚酰亚胺波导48的顶部。当气体或化学物质材料敏感出现，从聚酰亚胺向空气传播的光线增加，光电探测器感测到的总信号减小，光信号变化表示检测。

10. 发明授权

US5436181A Method of self aligning an emitter contact in a heterojunction bipolar transistor 失效
标题翻译：在异质结双极晶体管中自发对准发射极接触的方法
公开(公告)号：US5436181A
公开(公告)日：1995-07-25
申请号：US229044
申请日：1994-04-18
申请人： Francis J. Morris , Jau-Yuann Yang , Donald L. Plumton , Han-Tzong Yuan
发明人： Francis J. Morris , Jau-Yuann Yang , Donald L. Plumton , Han-Tzong Yuan
IPC分类号： H01L29/73 , H01L21/331 , H01L29/205 , H01L29/737
CPC分类号： H01L29/66318 , H01L29/7371 , Y10S148/011 , Y10S148/072
摘要： A method of self aligning an emitter contact includes forming a base layer (18) on a portion of a collector layer (16). An interface layer (22) is formed on the base layer (18) such that a portion of the base layer (18) remains exposed. An emitter layer (24) is formed on the collector layer (16), the interface layer (22), and the exposed portion of the base layer (18). An emitter cap layer (26) is formed on the emitter layer (24) over the previously exposed area of the base layer (18). An insulating layer (28) is formed on the interface layer (22). An emitter contact (36) is formed on the emitter cap layer (26) at the previously exposed area of the base layer (18). The insulating layer (28) isolates the emitter contact (36) from the base layer (18) and a subsequently formed base contact (38). The insulating layer (28) ensures isolation between the emitter contact ( 36) and the base contact (38) despite misalignment of the emitter contact (36) during formation.
摘要翻译：自发对准发射极接触的方法包括在集电极层（16）的一部分上形成基极层（18）。界面层（22）形成在基底层（18）上，使得基底层（18）的一部分保持暴露。发射极层（24）形成在集电层（16），界面层（22）和基层（18）的露出部分上。在基底层（18）的预先暴露的区域上的发射极层（24）上形成发射极覆盖层（26）。绝缘层（28）形成在界面层（22）上。在基底层（18）的预先暴露的区域处，在发射极盖层（26）上形成发射极触点（36）。绝缘层（28）将发射极触点（36）与基底层（18）和随后形成的基部触点（38）隔离开来。绝缘层（28）确保发射极触点（36）和基极触点（38）之间的隔离，尽管发射极触点（36）在形成期间未对准。

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