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1. 发明授权

US6008519A Vertical transistor and method 失效
标题翻译：垂直晶体管和方法
公开(公告)号：US6008519A
公开(公告)日：1999-12-28
申请号：US990549
申请日：1997-12-15
申请人： Han-Tzong Yuan , Donald L. Plumpton , Jau-Yuann Yang , Tae S. Kim
发明人： Han-Tzong Yuan , Donald L. Plumpton , Jau-Yuann Yang , Tae S. Kim
IPC分类号： H01L21/335 , H01L29/772 , H01L29/76 , H01L29/74 , H01L29/80
CPC分类号： H01L29/66416 , H01L29/7722
摘要： A vertical transistor (70) comprising a first semiconductor layer (14) of a first conductive type. A gate structure (32) of a second conductive type disposed on the first semiconductor layer (14). The gate structure (32) may include a plurality of gates (38) separated by channels (40). A second semiconductor layer (50) of the first conductive type may be disposed over the gate structure (32) and in the channels (40). An arresting element (36) may be disposed between and upper surface of the gates (38) and the second semiconductor layer (50). A void (52) may be formed in the second semiconductor layer (50) over the gate (38).
摘要翻译：一种包括第一导电类型的第一半导体层（14）的垂直晶体管（70）。设置在第一半导体层（14）上的第二导电类型的栅极结构（32）。栅极结构（32）可以包括由通道（40）分开的多个栅极（38）。第一导电类型的第二半导体层（50）可以设置在栅极结构（32）上和通道（40）中。止动元件（36）可以设置在栅极（38）和第二半导体层（50）的上表面之间。可以在栅极（38）上的第二半导体层（50）中形成空穴（52）。

2. 发明授权

US5342795A Method of fabricating power VFET gate-refill 失效
标题翻译：制造功率VFET栅极补充的方法
公开(公告)号：US5342795A
公开(公告)日：1994-08-30
申请号：US153121
申请日：1993-11-15
申请人： Han-Tzong Yuan , Donald L. Plumton , Tae S. Kim , Jau-Yuann Yang
发明人： Han-Tzong Yuan , Donald L. Plumton , Tae S. Kim , Jau-Yuann Yang
IPC分类号： H01L21/335 , H01L21/337 , H01L29/207 , H01L29/772 , H01L21/44
CPC分类号： H01L29/66454 , H01L29/207 , H01L29/66924 , H01L29/7722 , Y10S148/04
摘要： This is a method of forming a vertical transistor device comprising: forming an n-type first drain/source layer 42; patterning a portion of the first drain/source layer 42 to form a channel 44 and a trench; forming a p-type gate structure 46 in the trench; and forming a n-type second drain/source layer 48 over the gate structure 46 and the channel 44; contacting the gate structure 54; forming p-ohmic contact to the gate structure 56; forming n-ohmic source contact 54; and forming n-ohmic drain contact 58. Other devices and methods are also disclosed.
摘要翻译：这是形成垂直晶体管器件的方法，包括：形成n型第一漏极/源极层42; 图案化第一漏极/源极层42的一部分以形成沟道44和沟槽; 在沟槽中形成p型栅极结构46; 以及在栅极结构46和沟道44上形成n型第二漏极/源极层48; 接触门结构54; 与门结构56形成p欧姆接触; 形成n-欧姆源触点54; 并形成n欧姆漏极触点58.还公开了其它装置和方法。

3. 发明授权

US5468661A Method of making power VFET device 失效
标题翻译：制造电源VFET器件的方法
公开(公告)号：US5468661A
公开(公告)日：1995-11-21
申请号：US78388
申请日：1993-06-17
申请人： Han-Tzong Yuan , Donald L. Plumton , Tae S. Kim , Jau-Yuann Yang
发明人： Han-Tzong Yuan , Donald L. Plumton , Tae S. Kim , Jau-Yuann Yang
IPC分类号： H01L21/335 , H01L21/337 , H01L29/808 , H01L21/8258
CPC分类号： H01L29/66454 , H01L29/66924 , H01L29/8083
摘要： This is a method of forming a vertical transistor device comprising: forming an n-type first drain/source layer 42; patterning a portion of the first drain/source layer 42 to form a channel 44 and a trench; forming a p-type gate structure 46 in the trench; and forming a n-type second drain/source layer 48 over the gate structure 46 and the channel 44. Other devices and methods are also disclosed.
摘要翻译：这是形成垂直晶体管器件的方法，包括：形成n型第一漏极/源极层42; 图案化第一漏极/源极层42的一部分以形成沟道44和沟槽; 在沟槽中形成p型栅极结构46; 以及在栅极结构46和沟道44上形成n型第二漏极/源极层48.还公开了其它器件和方法。

4. 发明授权

US5610085A Method of making a vertical FET using epitaxial overgrowth 失效
标题翻译：使用外延生长制造垂直FET的方法
公开(公告)号：US5610085A
公开(公告)日：1997-03-11
申请号：US483028
申请日：1995-06-07
申请人： Han-Tzong Yuan , Tae S. Kim , Donald L. Plumton
发明人： Han-Tzong Yuan , Tae S. Kim , Donald L. Plumton
IPC分类号： H01L21/335 , H01L27/06 , H01L29/04 , H01L29/10 , H01L29/808 , H01L21/265
CPC分类号： H01L29/66454 , H01L27/0605 , H01L29/045 , H01L29/1066 , H01L29/1075 , H01L29/8083
摘要： A vertical field effect transistor (1700) and fabrication method with buried gates (1704) having spaced apart gate fingers and connecting structure and overgrown with source and channel epilayer followed by a doping connection of the gate fingers and connecting structure is disclosed. The vertical field effect transistor elements (1702, 1704, 1706, 1708, 1720, 1724) are made of III-V semiconductor compound grown on a germanium substrate (1726).
摘要翻译：公开了一种垂直场效应晶体管（1700）和具有间隔开的栅极指和连接结构的掩埋栅极（1704）的制造方法，并且随着源极和沟道外延层上覆盖，随后是栅极指状物和连接结构的掺杂连接。垂直场效应晶体管元件（1702,1704,1706,1708,1720,1724）由在锗衬底（1726）上生长的III-V半导体化合物制成。

5. 发明授权

US5231037A Method of making a power VFET device using a p+ carbon doped gate layer 失效
标题翻译：使用p +碳掺杂栅极层制造功率VFET器件的方法
公开(公告)号：US5231037A
公开(公告)日：1993-07-27
申请号：US876252
申请日：1992-04-30
申请人： Han-Tzong Yuan , Tae S. Kim , Francis J. Morris
发明人： Han-Tzong Yuan , Tae S. Kim , Francis J. Morris
IPC分类号： H01L29/80 , H01L21/335 , H01L21/337 , H01L29/207 , H01L29/772
CPC分类号： H01L29/66454 , H01L29/207 , H01L29/66924 , H01L29/7722 , Y10S148/04
摘要： This is a method of forming a vertical transistor device. The method comprises: forming a n-type source layer 12; forming a p+ carbon doped gate layer 14; forming a gate structure from the gate layer; and forming a n-type drain layer 16 over the gate structure to provide a buried carbon doped gate structure. The buried carbon doped gate structure provides a very small device with favorable on-resistance, junction capacitance, gate resistance, and gate driving voltage. Other devices and methods are also disclosed.

6. 发明授权

US06509574B2 Optocouplers having integrated organic light-emitting diodes 有权
公开(公告)号：US06509574B2
公开(公告)日：2003-01-21
申请号：US09728155
申请日：2000-12-04
申请人： Han-Tzong Yuan , Tae S. Kim , Simon J. Jacobs , Francis G. Celii
发明人： Han-Tzong Yuan , Tae S. Kim , Simon J. Jacobs , Francis G. Celii
IPC分类号： G02B2700
CPC分类号： H01L31/173 , H01L27/3227
摘要： An optocoupler structure comprising a semiconductor chip having an integrated circuit and an optically transparent, electrically insulating layer having first and second surfaces; an organic diode integral with said first surface, said diode operable to emit electromagnetic radiation; and said circuit including a radiation-sensitive semiconductor device integral with said second surface, electrically isolated from said diode, and positioned in the path of said radiation.

7. 发明授权

US08514919B2 Synthetic instrument unit 有权
标题翻译：合成仪器单元
公开(公告)号：US08514919B2
公开(公告)日：2013-08-20
申请号：US13126127
申请日：2010-08-25
申请人： Anthony J. Estrada , Dana C. Ford , Tae S. Kim , Robert W. Lowdermilk , Dragan Vuletic
发明人： Anthony J. Estrada , Dana C. Ford , Tae S. Kim , Robert W. Lowdermilk , Dragan Vuletic
IPC分类号： H04B17/00
CPC分类号： G01R23/16 , G01R19/2516
摘要： Systems and other embodiments associated with synthetic instrumentation are presented. A reconfigurable synthetic instrumentation unit comprises an input module, with dual input/output ports and conditioning logic to condition an input signal. An RF down converter selectively down converts the conditioned input signal. A sampled RF down converter selectively samples the conditioned input signal. A pair of narrowband A/D converters are configured to convert one of the conditioned signal, the down converted signal and the sampled signal to produce a narrowband digital signal. A pair of broadband A/D converters convert at least one of the conditioned signal, the down converted signal and the sampled signal to produce a broadband digital signal. Signal processing logic selectively performs digital signal processing on the broadband digital signal or the narrow band digital signal.
摘要翻译：介绍了与合成仪器相关的系统和其他实施例。可重构的合成仪表单元包括具有双输入/输出端口和调节逻辑的输入模块，用于调节输入信号。 RF下变频器选择性地降低转换经调节的输入信号。采样的RF下变频器选择性地对经调节的输入信号进行采样。一对窄带A / D转换器被配置为转换调节信号，下变频信号和采样信号中的一个，以产生窄带数字信号。一对宽带A / D转换器将调节信号，下变频信号和采样信号中的至少一个转换成宽带数字信号。信号处理逻辑选择性地对宽带数字信号或窄带数字信号执行数字信号处理。

8. 发明申请

US20080153282A1 METHOD FOR PREPARING A METAL FEATURE SURFACE 审中-公开
标题翻译：制备金属特征表面的方法
公开(公告)号：US20080153282A1
公开(公告)日：2008-06-26
申请号：US11614185
申请日：2006-12-21
申请人： Manoj K. Jain , Tae S. Kim , Stephan Grunow
发明人： Manoj K. Jain , Tae S. Kim , Stephan Grunow
IPC分类号： H01L21/02
CPC分类号： H01L23/53238 , H01L21/02063 , H01L21/02068 , H01L21/76814 , H01L2924/0002 , Y10T29/49002 , H01L2924/00
摘要： Provided is a method for manufacturing an interconnect. The method for manufacturing the interconnect, in one embodiment, includes forming a first metal feature over or within a substrate, the first metal feature having an exposed surface. The method for manufacturing the interconnect may additionally include cleaning the exposed surface using a reactive system with a reducing agent, and subjecting the exposed surface to a plasma etch. The method for manufacturing the interconnect may further include contacting the first metal feature with a second metal feature.
摘要翻译：提供一种制造互连的方法。在一个实施例中，用于制造互连的方法包括在衬底上或衬底内形成第一金属特征，第一金属特征具有暴露表面。用于制造互连的方法可以另外包括使用具有还原剂的反应系统清洁暴露的表面，以及对暴露的表面进行等离子体蚀刻。用于制造互连的方法还可以包括使第一金属特征与第二金属特征接触。

9. 发明申请

US20120020397A1 SYNTHETIC INSTRUMENT UNIT 有权
标题翻译：合成仪器单元
公开(公告)号：US20120020397A1
公开(公告)日：2012-01-26
申请号：US13126127
申请日：2010-08-25
申请人： Anthony J. Estrada , Dana C. Ford , Tae S. Kim , Robert W. Lowdermilk , Dragan Vuletic
发明人： Anthony J. Estrada , Dana C. Ford , Tae S. Kim , Robert W. Lowdermilk , Dragan Vuletic
IPC分类号： H04B17/00
CPC分类号： G01R23/16 , G01R19/2516
摘要： Systems and other embodiments associated with synthetic instrumentation are presented. A reconfigurable synthetic instrumentation unit comprises an input module, with dual input/output ports and conditioning logic to condition an input signal. An RF down converter selectively down converts the conditioned input signal. A sampled RF down converter selectively samples the conditioned input signal. A pair of narrowband A/D converters are configured to convert one of the conditioned signal, the down converted signal and the sampled signal to produce a narrowband digital signal. A pair of broadband A/D converters convert at least one of the conditioned signal, the down converted signal and the sampled signal to produce a broadband digital signal. Signal processing logic selectively performs digital signal processing on the broadband digital signal or the narrow band digital signal.
摘要翻译：介绍了与合成仪器相关的系统和其他实施例。可重构的合成仪表单元包括具有双输入/输出端口和调节逻辑的输入模块，用于调节输入信号。 RF下变频器选择性地降低转换经调节的输入信号。采样的RF下变频器选择性地对经调节的输入信号进行采样。一对窄带A / D转换器被配置为转换调节信号，下变频信号和采样信号中的一个，以产生窄带数字信号。一对宽带A / D转换器将调节信号，下变频信号和采样信号中的至少一个转换成宽带数字信号。信号处理逻辑选择性地对宽带数字信号或窄带数字信号执行数字信号处理。

10. 发明授权

US06409828B1 Method and apparatus for achieving a desired thickness profile in a flow-flange reactor 失效
标题翻译：在流动法兰反应器中实现所需厚度分布的方法和装置
公开(公告)号：US06409828B1
公开(公告)日：2002-06-25
申请号：US08526828
申请日：1995-09-12
申请人： Tae S. Kim
发明人： Tae S. Kim
IPC分类号： C30B2516
CPC分类号： C30B25/02 , C23C16/455 , C23C16/52 , C30B25/14 , C30B29/40
摘要： A method and apparatus are disclosed for achieving a desired thickness profile in a semiconductor device (44) using a flow-flange reactor (10), by adjusting input flow ratios in the flow-flange (12) of the reactor (10). A target thickness profile is established. A first set of optimum input flow ratios are then determined in response to the target thickness profile, based upon a first plurality of sample thickness profiles and a first plurality of sets of sample input flow ratios, wherein each of the sample thickness profiles corresponds to one of the first plurality of sets of sample input flow ratios. The input flow ratios of the reactor (10) are then adjusted in response to the first optimum set of input flow ratios.
摘要翻译：公开了一种通过调节反应器（10）的流动凸缘（12）中的输入流量比来使用流动法兰反应器（10）在半导体器件（44）中实现所需厚度分布的方法和装置。建立目标厚度剖面。然后基于第一多个样品厚度分布和第一组多组样品输入流量比来响应于目标厚度分布来确定第一组最佳输入流量比，其中每个样品厚度分布对应于一个的第一组多组样本输入流量比。然后响应于第一最佳输入流量组而调节反应器（10）的输入流量比。

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