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1. 发明授权

US5223449A Method of making an integrated circuit composed of group III-V compound field effect and bipolar semiconductors 失效
标题翻译：制备由III-V族化合物场效应和双极半导体组成的集成电路的方法
公开(公告)号：US5223449A
公开(公告)日：1993-06-29
申请号：US692326
申请日：1991-04-26
申请人： Francis J. Morris , Donald L. Plumton , Jau-Yuann Yang , Han-Tzong Yuan
发明人： Francis J. Morris , Donald L. Plumton , Jau-Yuann Yang , Han-Tzong Yuan
IPC分类号： H01L27/06 , H01L27/082
CPC分类号： H01L27/0623 , H01L27/0605 , H01L27/0826 , Y10S148/009 , Y10S148/072
摘要： Integrated circuits and fabrication methods incorporating both NPN (192, 194, 210) and PNP (196, 121, 124) heterojunction bipolar transistors together with N channel (198, 200, 216, 218) and P channel (202, 204, 220, 222) JFETs on a single substrate as illustrated in FIG. 10. MESFETs may be also be integrated on the substrate.
摘要翻译：集成电路和制造方法将NPN（192,194,210）和PNP（196,121,124）异构双极晶体管与N沟道（198,200,216,218）和P沟道（202,204,220） 222）如图1所示的单个衬底上的JFET。 MESFET也可以集成在衬底上。

2. 发明授权

US5407842A Enhanced performance bipolar transistor process 失效
标题翻译：增强性能双极晶体管工艺
公开(公告)号：US5407842A
公开(公告)日：1995-04-18
申请号：US255502
申请日：1994-06-08
申请人： Francis J. Morris , Jau-Yuann Yang , Donald L. Plumton , Han-Tzong Yuan
发明人： Francis J. Morris , Jau-Yuann Yang , Donald L. Plumton , Han-Tzong Yuan
IPC分类号： H01L21/331 , H01L27/06 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66318 , H01L27/0605 , H01L29/7371 , Y10S148/01 , Y10S148/072
摘要： This is a method of forming a bipolar transistor comprising: forming a subcollector layer, having a doping type and a doping level, on a substrate; forming a first layer, of the same doping type and a lower doping level than the subcollector layer, over the subcollector layer; increasing the doping level of first and second regions of the first layer; forming a second layer, of the same doping type and a lower doping level than the subcollector layer, over the first layer; increasing the doping level of a first region of the second layer which is over the first region of the first layer, whereby the subcollector layer, the first region of the first layer and the first region of the second layer are the collector of the transistor; forming a base layer over the second layer of an opposite doping type than the subcollector layer; and forming an emitter layer of the same doping type as the subcollector layer over the base layer. Other devices and methods are also disclosed.
摘要翻译：这是一种形成双极晶体管的方法，包括：在衬底上形成具有掺杂类型和掺杂水平的子集电极层; 在子集电极层上形成与子集电极层相同的掺杂类型和较低掺杂水平的第一层; 增加第一层的第一和第二区域的掺杂水平; 在第一层上形成与子集电极层相同的掺杂类型和较低掺杂水平的第二层; 增加在第一层的第一区域之上的第二层的第一区域的掺杂水平，由此子集电极层，第一层的第一区域和第二层的第一区域是晶体管的集电极; 在与所述子集电极层相反的掺杂类型的第二层上形成基底层; 并且在基底层上形成与子集电极层相同的掺杂类型的发射极层。还公开了其它装置和方法。

3. 发明授权

US5548141A Bipolar transistor having a self emitter contact aligned 失效
标题翻译：具有自发射体触点对准的双极晶体管
公开(公告)号：US5548141A
公开(公告)日：1996-08-20
申请号：US441847
申请日：1995-05-16
申请人： Francis J. Morris , Jau-Yuann Yang , Donald L. Plumton , Han-Tzong Yuan
发明人： Francis J. Morris , Jau-Yuann Yang , Donald L. Plumton , Han-Tzong Yuan
IPC分类号： H01L29/73 , H01L21/331 , H01L29/205 , H01L29/737 , H01L29/161
CPC分类号： H01L29/66318 , H01L29/7371 , Y10S148/011 , Y10S148/072
摘要： A method of self aligning an emitter contact includes forming a base layer (18) on a portion of a collector layer (16). An interface layer (22) is formed on the base layer (18) such that a portion of the base layer (18) remains exposed. An emitter layer (24) is formed on the collector layer (16), the interface layer (22), and the exposed portion of the base layer (18). An emitter cap layer (26) is formed on the emitter layer (24) over the previously exposed area of the base layer (18). An insulating layer (28) is formed on the interface layer (22). An emitter contact (36) is formed on the emitter cap layer (26) at the previously exposed area of the base layer (18). The insulating layer (28) isolates the emitter contact (36) from the base layer (18) and a subsequently formed base contact (38). The insulating layer (28) ensures isolation between the emitter contact (36) and the base contact (38) despite misalignment of the emitter contact (36) during formation.
摘要翻译：自发对准发射极接触的方法包括在集电极层（16）的一部分上形成基极层（18）。界面层（22）形成在基底层（18）上，使得基底层（18）的一部分保持暴露。发射极层（24）形成在集电层（16），界面层（22）和基层（18）的露出部分上。在基底层（18）的预先暴露的区域上的发射极层（24）上形成发射极覆盖层（26）。绝缘层（28）形成在界面层（22）上。在基底层（18）的预先暴露的区域处，在发射极盖层（26）上形成发射极触点（36）。绝缘层（28）将发射极触点（36）与基底层（18）和随后形成的基部触点（38）隔离开来。绝缘层（28）确保发射极触点（36）和基极触点（38）之间的隔离，尽管发射极触点（36）在形成期间未对准。

4. 发明授权

US5420052A Method of fabricating a semiplanar heterojunction bipolar transistor 失效
标题翻译：制造半平面异质结双极晶体管的方法
公开(公告)号：US5420052A
公开(公告)日：1995-05-30
申请号：US230357
申请日：1994-04-19
申请人： Francis J. Morris , Jau-Yuann Yang , Donald L. Plumton , Han-Tzong Yuan
发明人： Francis J. Morris , Jau-Yuann Yang , Donald L. Plumton , Han-Tzong Yuan
IPC分类号： H01L29/73 , H01L21/331 , H01L29/205 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66318 , H01L29/7371 , Y10S148/072
摘要： A method of fabricating a semiplanar heterojunction bipolar transistor (10) includes forming a subcollector layer (12) and a collector layer (16) onto a substrate layer (14). A collector implant plug (18) is selectively implanted to connect the subcollector layer (12) to the surface of the heterojunction bipolar transistor (10). A second epitaxial growth process causes a base layer (22), an emitter layer (24), and an emitter cap layer (26) to form on the collector layer (16) and the collector implant plug (18). By this process, the base layer (22) is not exposed to subsequent harmful fabrication steps. A base plug region (28) is selectively implanted to connect the base layer (22) to the surface of the heterojunction bipolar transistor (10). A base contact (32) and an emitter contact (30) are selectively formed within the heterojunction region on the base plug region (28) and the emitter cap layer (26), respectively. Lateral parasitic diodes between the base contact (32) and the emitter contact (30) are etched away to isolate the base contact (32) from the emitter contact (30). The emitter cap layer (26), the emitter layer (24), and the base layer (22) are removed from the vicinity of the collector implant plug (18) to allow formation of the collector contact (34).
摘要翻译：制造半平面异质结双极晶体管（10）的方法包括在衬底层（14）上形成子集电极层（12）和集电极层（16）。选择性地注入集电极注入插头（18）以将子集电极层（12）连接到异质结双极晶体管（10）的表面。第二外延生长工艺使得在集电极层（16）和集电极植入插头（18）上形成基极层（22），发射极层（24）和发射极盖层（26）。通过该过程，基层（22）不暴露于随后的有害制造步骤。选择性地注入基座区域（28）以将基极层（22）连接到异质结双极晶体管（10）的表面。基极触点（32）和发射极触点（30）分别选择性地形成在基插塞区域（28）和发射极盖层（26）上的异质结区域内。基极触点（32）和发射极触点（30）之间的侧向寄生二极管被蚀刻掉以将基极触点（32）与发射极触点（30）隔离。发射极帽层（26），发射极层（24）和基底层（22）从集电极植入插头（18）的附近被去除，以形成集电极触点（34）。

5. 发明授权

US5369042A Enhanced performance bipolar transistor process 失效
标题翻译：增强性能双极晶体管工艺
公开(公告)号：US5369042A
公开(公告)日：1994-11-29
申请号：US26886
申请日：1993-03-05
申请人： Francis J. Morris , Jau-Yuann Yang , Donald L. Plumton , Han-Tzong Yuan
发明人： Francis J. Morris , Jau-Yuann Yang , Donald L. Plumton , Han-Tzong Yuan
IPC分类号： H01L21/331 , H01L27/06 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66318 , H01L27/0605 , H01L29/7371 , Y10S148/01 , Y10S148/072
摘要： This is a method of forming a bipolar transistor comprising: forming a subcollector layer, having a doping type and a doping level, on a substrate; forming a first layer, of the same doping type and a lower doping level than the subcollector layer, over the subcollector layer; increasing the doping level of first and second regions of the first layer; forming a second layer, of the same doping type and a lower doping level than the subcollector layer, over the first layer; increasing the doping level of a first region of the second layer which is over the first region of the first layer, whereby the subcollector layer, the first region of the first layer and the first region of the second layer are the collector of the transistor; forming a base layer over the second layer of an opposite doping type than the subcollector layer; and forming an emitter layer of the same doping type as the subcollector layer over the base layer. Other devices and methods are also disclosed.
摘要翻译：这是一种形成双极晶体管的方法，包括：在衬底上形成具有掺杂类型和掺杂水平的子集电极层; 在子集电极层上形成与子集电极层相同的掺杂类型和较低掺杂水平的第一层; 增加第一层的第一和第二区域的掺杂水平; 在第一层上形成与子集电极层相同的掺杂类型和较低掺杂水平的第二层; 增加在第一层的第一区域之上的第二层的第一区域的掺杂水平，由此子集电极层，第一层的第一区域和第二层的第一区域是晶体管的集电极; 在与所述子集电极层相反的掺杂类型的第二层上形成基底层; 并且在基底层上形成与子集电极层相同的掺杂类型的发射极层。还公开了其它装置和方法。

6. 发明授权

US5436181A Method of self aligning an emitter contact in a heterojunction bipolar transistor 失效
标题翻译：在异质结双极晶体管中自发对准发射极接触的方法
公开(公告)号：US5436181A
公开(公告)日：1995-07-25
申请号：US229044
申请日：1994-04-18
申请人： Francis J. Morris , Jau-Yuann Yang , Donald L. Plumton , Han-Tzong Yuan
发明人： Francis J. Morris , Jau-Yuann Yang , Donald L. Plumton , Han-Tzong Yuan
IPC分类号： H01L29/73 , H01L21/331 , H01L29/205 , H01L29/737
CPC分类号： H01L29/66318 , H01L29/7371 , Y10S148/011 , Y10S148/072
摘要： A method of self aligning an emitter contact includes forming a base layer (18) on a portion of a collector layer (16). An interface layer (22) is formed on the base layer (18) such that a portion of the base layer (18) remains exposed. An emitter layer (24) is formed on the collector layer (16), the interface layer (22), and the exposed portion of the base layer (18). An emitter cap layer (26) is formed on the emitter layer (24) over the previously exposed area of the base layer (18). An insulating layer (28) is formed on the interface layer (22). An emitter contact (36) is formed on the emitter cap layer (26) at the previously exposed area of the base layer (18). The insulating layer (28) isolates the emitter contact (36) from the base layer (18) and a subsequently formed base contact (38). The insulating layer (28) ensures isolation between the emitter contact ( 36) and the base contact (38) despite misalignment of the emitter contact (36) during formation.
摘要翻译：自发对准发射极接触的方法包括在集电极层（16）的一部分上形成基极层（18）。界面层（22）形成在基底层（18）上，使得基底层（18）的一部分保持暴露。发射极层（24）形成在集电层（16），界面层（22）和基层（18）的露出部分上。在基底层（18）的预先暴露的区域上的发射极层（24）上形成发射极覆盖层（26）。绝缘层（28）形成在界面层（22）上。在基底层（18）的预先暴露的区域处，在发射极盖层（26）上形成发射极触点（36）。绝缘层（28）将发射极触点（36）与基底层（18）和随后形成的基部触点（38）隔离开来。绝缘层（28）确保发射极触点（36）和基极触点（38）之间的隔离，尽管发射极触点（36）在形成期间未对准。

7. 发明授权

US5068756A Integrated circuit composed of group III-V compound field effect and bipolar semiconductors 失效
标题翻译：由III-V族复合场效应和双极半导体组成的集成电路
公开(公告)号：US5068756A
公开(公告)日：1991-11-26
申请号：US554116
申请日：1990-07-18
申请人： Francis J. Morris , Donald L. Plumton , Jau-Yuann Yang , Han-Tzong Yuan
发明人： Francis J. Morris , Donald L. Plumton , Jau-Yuann Yang , Han-Tzong Yuan
IPC分类号： H01L27/06 , H01L27/082
CPC分类号： H01L27/0623 , H01L27/0605 , H01L27/0826
摘要： Integrated circuits and fabrication methods incorporating both NPN (192, 194, 210) and PNP (196, 121, 124) heterojunction bipolar transistors together with N channel (198, 200, 216, 218) and P channel (202, 204, 220, 222) JFETs on a single substrate as illustrated in FIG. 10. MESFETs may also be integrated on the substrate.
摘要翻译：集成电路和制造方法将NPN（192,194,210）和PNP（196,121,124）异构双极晶体管与N沟道（198,200,216,218）和P沟道（202,204,220） 222）如图1所示的单个衬底上的JFET。 MESFET也可以集成在衬底上。

8. 发明授权

US5077231A Method to integrate HBTs and FETs 失效
标题翻译：集成HBT和FET的方法
公开(公告)号：US5077231A
公开(公告)日：1991-12-31
申请号：US670094
申请日：1991-03-15
申请人： Donald L. Plumton , Francis J. Morris , Jau-Yuann Yang
发明人： Donald L. Plumton , Francis J. Morris , Jau-Yuann Yang
IPC分类号： H01L27/06 , H01L21/331 , H01L21/338 , H01L21/76 , H01L21/8232 , H01L21/8252 , H01L27/095 , H01L29/205 , H01L29/73 , H01L29/737 , H01L29/778 , H01L29/812
CPC分类号： H01L27/0623 , H01L21/7605 , H01L21/8252 , Y10S148/009 , Y10S148/072
摘要： This is a method for fabricating integrated heterojunction bipolar transistors (HBTs) and heterojunction field effect transistors (HFETs) on a substrate. The method comprises: forming a subcollector layer 12 over the substrate 10; forming a collector layer 14 over the subcollector layer; forming a base layer 16 over the collector layer; etching the base layer to form one or more base pedestals 16 over a portion of the collector layer; forming a buffer region 18 in a portion of the collector layer over which one or more HFETs are fabricated; forming one or more channel regions 20,22 over the buffer region; forming a wide bandgap material emitter/gate layer 26 over the base pedestal and the channel region; forming isolation regions 30,32, whereby there is one or more separate HBTs and one or more separate HFETs over the substrate utilizing an epitaxially grown emitter/gate layer to form both an HBT emitter and an HFET gate. Other devices and methods are also disclosed.
摘要翻译：这是在衬底上制造集成异质结双极晶体管（HBT）和异质结场效应晶体管（HFET）的方法。该方法包括：在衬底10上形成子集电极层12; 在子集电极层上形成集电极层14; 在集电极层上形成基层16; 蚀刻基底层以在集电极层的一部分上形成一个或多个基座16; 在所述集电极层的一部分上形成缓冲区18，在所述集电极层中制造一个或多个HFET; 在所述缓冲区上形成一个或多个沟道区20,22; 在基座和通道区域上形成宽带隙材料发射极/栅极层26; 形成隔离区30,32，由此在衬底上存在一个或多个单独的HBT和一个或多个单独的HFET，利用外延生长的发射极/栅极层以形成HBT发射极和HFET栅极。还公开了其它装置和方法。

9. 发明授权

US5698460A Method of self-aligning an emitter contact in a planar heterojunction bipolar transistor and apparatus thereof 失效
标题翻译：在平面异质结双极晶体管中自发对准发射极接触的方法及其装置
公开(公告)号：US5698460A
公开(公告)日：1997-12-16
申请号：US480290
申请日：1995-06-07
申请人： Jau-Yuann Yang , Donald L. Plumton , Francis J. Morris
发明人： Jau-Yuann Yang , Donald L. Plumton , Francis J. Morris
IPC分类号： H01L21/331 , H01L29/06 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66318 , H01L29/0649 , H01L29/7371 , Y10S148/01 , Y10S148/072
摘要： A self-aligned planar heterojunction bipolar transistor (10) is fabricated by forming a base layer (18) and forming an emitter layer (20) on the base layer (18). An emitter cap layer (22) is formed on the emitter layer (20) and an interface layer (24) is formed on the emitter cap layer (22). A first implantation layer (26) is formed through the interface layer (24), the emitter cap layer (22), and the emitter layer (20) to the base layer (18). A second implantation layer (30) is formed through the interface layer (24), the emitter cap layer (22), and the emitter layer (20) to the base layer (18) and overlaps the first implantation layer (26). A portion of the interface layer (24), the emitter cap layer (22), and the implantation layers (26, 30) are removed and replaced by an insulating region (33). An emitter contact (38) is formed on the remaining emitter cap layer (22) and is isolated from the implantation layers (26, 30) by the insulating region (33). The insulating region (33) acts as a buffer to self-align the emitter contact (38) to the implantation layer (26, 30).
摘要翻译：通过形成基底层（18）并在基底层（18）上形成发射极层（20）来制造自对准的平面异质结双极晶体管（10）。在发射极层（20）上形成发射极盖层（22），在发射极盖层（22）上形成界面层（24）。通过界面层（24），发射极帽层（22）和发射极层（20）到基底层（18）形成第一注入层（26）。第二注入层（30）通过界面层（24），发射极覆盖层（22）和发射极层（20）形成到基底层（18）并与第一注入层（26）重叠。界面层（24）的一部分，发射极盖层（22）和注入层（26,30）被去除并由绝缘区域（33）代替。发射极触点（38）形成在剩余的发射极覆盖层（22）上，并通过绝缘区域（33）与注入层（26,30）隔离。绝缘区域（33）用作缓冲器以使发射极触点（38）自对准到注入层（26,30）。

10. 发明授权

US5243207A Method to integrate HBTs and FETs 失效
标题翻译：集成HBT和FET的方法
公开(公告)号：US5243207A
公开(公告)日：1993-09-07
申请号：US984006
申请日：1992-11-30
申请人： Donald L. Plumton , Francis J. Morris , Jau-Yuann Yang
发明人： Donald L. Plumton , Francis J. Morris , Jau-Yuann Yang
IPC分类号： H01L21/76 , H01L21/8252
CPC分类号： H01L21/8252 , H01L21/7605
摘要： This is a method for fabricating integrated heterojunction bipolar transistors (HBTs) and heterojunction field effect transistors (HFETs) on a substrate. The method comprises: forming a subcollector layer 12 over the substrate 10; forming a collector layer 14 over the subcollector layer; forming a base layer 16 over the collector layer; etching the base layer to form one or more base pedestals 16 over a portion of the collector layer; forming a buffer region 18 in a portion of the collector layer over which one or more HFETs are fabricated; forming one or more channel regions 20,22 over the buffer region; forming a wide bandgap material emitter/gate layer 26 over the base pedestal and the channel region; forming isolation regions 30,32, whereby there is one or more separate HBTs and one or more separate HFETs over the substrate utilizing an epitaxially grown emitter/gate layer to form both an HBT emitter and an HFET gate. Other devices and methods are also disclosed.
摘要翻译：这是在衬底上制造集成异质结双极晶体管（HBT）和异质结场效应晶体管（HFET）的方法。该方法包括：在衬底10上形成子集电极层12; 在子集电极层上形成集电极层14; 在集电极层上形成基层16; 蚀刻基底层以在集电极层的一部分上形成一个或多个基座16; 在所述集电极层的一部分上形成缓冲区18，在所述集电极层中制造一个或多个HFET; 在所述缓冲区上形成一个或多个沟道区20,22; 在基座和通道区域上形成宽带隙材料发射极/栅极层26; 形成隔离区30,32，由此在衬底上存在一个或多个单独的HBT和一个或多个单独的HFET，利用外延生长的发射极/栅极层以形成HBT发射极和HFET栅极。还公开了其它装置和方法。

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