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1. 发明授权

US06284669B1 Power transistor with silicided gate and contacts 有权
标题翻译：功率晶体管采用硅化栅和触点
公开(公告)号：US06284669B1
公开(公告)日：2001-09-04
申请号：US09168194
申请日：1998-10-07
申请人： John P. Erdeljac , Louis N. Hutter , Jeffrey P. Smith , Han-Tzong Yuan , Jau-Yuann Yang , Taylor R. Efland , C. Matthew Thompson , John K. Arch , Mary Ann Murphy
发明人： John P. Erdeljac , Louis N. Hutter , Jeffrey P. Smith , Han-Tzong Yuan , Jau-Yuann Yang , Taylor R. Efland , C. Matthew Thompson , John K. Arch , Mary Ann Murphy
IPC分类号： H01L21302
CPC分类号： H01L29/66659 , H01L29/456 , H01L29/7835
摘要： A power field effect transistor is disclosed that includes polysilicon gate bodies (40) and (42), which includes platinum silicide contact layers (74) and (78) disposed on the outer surfaces of bodies (40) and (42), respectively. In addition, the device comprises an n+drain region (64) which also has a platinum silicide drain contact layer (76) formed on its outer surface and platinum silicide source contact layers (75) and (77). During formation, sidewall spacers (50) and (52), as well as mask bodies (70) and (72) are used to ensure that platinum silicide layer (76) spaced apart from both gate bodies (40) and (42) and platinum silicide gate contact layers (74) and (78).
摘要翻译：公开了一种功率场效应晶体管，其包括分别设置在主体（40）和（42）的外表面上的铂硅化物接触层（74）和（78）的多晶硅栅极体（40）和（42）。另外，该器件还包括在其外表面上形成有铂硅化物漏极接触层（76）和铂硅化物源极接触层（75）和（77）的n +漏极区域（64）。在形成期间，侧壁间隔物（50）和（52）以及掩模体（70）和（72）用于确保与两个闸门体（40）和（42）间隔开的铂硅化物层（76）和铂硅化物栅极接触层（74）和（78）。

2. 发明授权

US06424005B1 LDMOS power device with oversized dwell 有权
标题翻译： LDMOS功率器件具有超大的驻留
公开(公告)号：US06424005B1
公开(公告)日：2002-07-23
申请号：US09205657
申请日：1998-12-03
申请人： Chin-Yu Tsai , Taylor R. Efland , Sameer Pendharkar , John P. Erdeljac , Jozef Mitros , Jeffrey P. Smith , Louis N. Hutter
发明人： Chin-Yu Tsai , Taylor R. Efland , Sameer Pendharkar , John P. Erdeljac , Jozef Mitros , Jeffrey P. Smith , Louis N. Hutter
IPC分类号： H01L31113
CPC分类号： H01L29/66689 , H01L29/086 , H01L29/0878 , H01L29/42368 , H01L29/7816
摘要： An LDMOS device (10, 20, 50, 60) that is made with minimal feature size fabrication methods, but overcomes potential problems of misaligned Dwells (13). The Dwell (13) is slightly overstated so that its n-type dopant is implanted past the source edge of the gate region (18), which permits the n-type region of the Dwell to diffuse under the gate region (18) an sufficient distance to eliminate misalignment effects.
摘要翻译： LDMOS器件（10,20,50,60）采用最小的特征尺寸制造方法制造，但克服了不对准Dwells的潜在问题（13）。驻留（13）略微夸大，使得其n型掺杂剂被注入超过栅极区域（18）的源极边缘，这允许Dwell的n型区域在栅极区域（18）下扩散到足够的距离消除不对准效应。

3. 发明授权

US06683380B2 Integrated circuit with bonding layer over active circuitry 有权
标题翻译：在有源电路上具有接合层的集成电路
公开(公告)号：US06683380B2
公开(公告)日：2004-01-27
申请号：US10191453
申请日：2002-07-10
申请人： Taylor R. Efland , Donald C. Abbott , Walter Bucksch , Marco Corsi , Chi-Cheong Shen , John P. Erdeljac , Louis N. Hutter , Quang X. Mai , Konrad Wagensohner , Charles E. Williams , Milton L. Buschbom
发明人： Taylor R. Efland , Donald C. Abbott , Walter Bucksch , Marco Corsi , Chi-Cheong Shen , John P. Erdeljac , Louis N. Hutter , Quang X. Mai , Konrad Wagensohner , Charles E. Williams , Milton L. Buschbom
IPC分类号： H01L2348
CPC分类号： H01L24/49 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05552 , H01L2224/05554 , H01L2224/05644 , H01L2224/05664 , H01L2224/0603 , H01L2224/1147 , H01L2224/13099 , H01L2224/131 , H01L2224/45124 , H01L2224/45144 , H01L2224/48463 , H01L2224/4847 , H01L2224/48644 , H01L2224/48664 , H01L2224/48764 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49175 , H01L2224/49431 , H01L2224/4945 , H01L2224/85191 , H01L2924/0001 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2224/48744
摘要： An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A-2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.
摘要翻译：一种具有直接在其有源电路上的接合表面（12）的集成电路器件（10），以及制造这种集成电路的方法（图2A-2E）。为了形成接合表面（12），晶片（20）在其金属化层（21）上设有通孔（24），然后涂覆有种子金属层（25）。电镀图案（26）形成在晶片（20）上，暴露种子金属层（25）的部分并阻挡种子金属层（25）的其余部分。这些暴露部分镀有连续的金属层（27,28,29），由此形成具有填充通孔（24）的多个层叠堆叠（200）的接合表面（12）。然后除去种子金属层（25）的电镀图案和非电镀部分。

4. 发明授权

US4994887A High voltage merged bipolar/CMOS technology 失效
标题翻译：高压合并双极/ CMOS技术
公开(公告)号：US4994887A
公开(公告)日：1991-02-19
申请号：US120558
申请日：1987-11-13
申请人： Louis N. Hutter , Mark E. Gibson , Jeffrey P. Smith , Shiu-Hang Yan , Arnold C. Conway , John P. Erdeljac , James D. Goon , AnhKim Duong , Mary A. Murphy , Susan S. Kearney
发明人： Louis N. Hutter , Mark E. Gibson , Jeffrey P. Smith , Shiu-Hang Yan , Arnold C. Conway , John P. Erdeljac , James D. Goon , AnhKim Duong , Mary A. Murphy , Susan S. Kearney
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/732
CPC分类号： H01L27/0623
摘要： An integrated circuit having PMOS, NMOS and NPN transistors is described for applications in which both digital and analog circuits are required. The integrated circuit is designed to allow standard CMOS cells to be used in the integrated circuit without redesign. A P+ substrate (48) is provided upon which a first P- epitaxy layer (46) is formed. N+ DUF regions (50,52) are provided for the PMOS and NPN transistors, respectively. The base region (68) is formed in an Nwell (58) by implantation and diffusion. Before diffusion, a nitride layer (70) is formed over the base (68) to provided an inert annealing thereof. The base diffusion and collector diffusion occurs before the CMOS channel stop and source/drain diffusions in order to prevent altering diffusion times for the MOS transistors.
摘要翻译：描述了具有PMOS，NMOS和NPN晶体管的集成电路用于需要数字和模拟电路的应用。该集成电路设计为允许在集成电路中使用标准CMOS单元，而无需重新设计。提供了P +衬底（48），其上形成有第一P-外延层（46）。分别为PMOS和NPN晶体管提供N + DUF区域（50,52）。基部区域（68）通过注入和扩散形成在N阱（58）中。在扩散之前，在基底（68）上形成氮化物层（70）以提供惰性退火。基极扩散和集电极扩散发生在CMOS沟道停止和源极/漏极扩散之前，以防止改变MOS晶体管的扩散时间。

5. 发明授权

US06153451A Transistor with increased operating voltage and method of fabrication 失效
标题翻译：具有增加的工作电压和制造方法的晶体管
公开(公告)号：US06153451A
公开(公告)日：2000-11-28
申请号：US2977
申请日：1998-01-05
申请人： Louis N. Hutter , John P. Erdeljac , Jeffrey P. Smith
发明人： Louis N. Hutter , John P. Erdeljac , Jeffrey P. Smith
IPC分类号： H01L21/336 , H01L29/06 , H01L29/08 , H01L29/423 , H01L29/45 , H01L29/78 , H01L21/366
CPC分类号： H01L29/7816 , H01L29/66689 , H01L29/0615 , H01L29/0638 , H01L29/086 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/456
摘要： A method for increasing the operating voltage of a transistor formed on a substrate of a first conductivity region of a second conductivity type in a surface of the substrate. An N-well adjust region of the first conductivity type is then formed in the N-well region. The N-well adjust region extends to a first depth in the N-well region. A double diffusion well of the first conductivity type is then formed in the N-well. The double diffusion well extends to a second depth greater than the first depth of the N-well adjust region, and contains a portion of the N-well. Two N- channel stop regions are then formed in the N-well. The two N-channel stop regions extending to a third depth greater than the depth of the N-well adjust region, and contain a portion of the N-well.
摘要翻译：一种在衬底的表面中增加形成在第二导电类型的第一导电区域的衬底上的晶体管的工作电压的方法。然后在N阱区域中形成第一导电类型的N阱调节区域。 N阱调整区域延伸到N阱区域中的第一深度。然后在N阱中形成第一导电类型的双扩散阱。双扩散阱延伸到大于N阱调节区域的第一深度的第二深度，并且包含N阱的一部分。然后在N阱中形成两个N-通道停止区。两个N沟道停止区延伸到大于N阱调整区的深度的第三深度，并且包含N阱的一部分。

6. 发明授权

US6025231A Self aligned DMOS transistor and method of fabrication 失效
标题翻译：自对准DMOS晶体管及其制造方法
公开(公告)号：US6025231A
公开(公告)日：2000-02-15
申请号：US25678
申请日：1998-02-18
申请人： Louis N. Hutter , John P. Erdeljac , James R. Todd
发明人： Louis N. Hutter , John P. Erdeljac , James R. Todd
IPC分类号： H01L29/06 , H01L29/10 , H01L29/423 , H01L29/78 , H01L21/336 , H01L21/8234
CPC分类号： H01L29/7835 , H01L29/0615 , H01L29/1083 , H01L29/42368
摘要： A method for fabricating a self-aligned DMOS transistor is provided. The method includes forming a passivation layer (18, 68) on an oxide layer (16, 66) of a substrate (12, 56). The oxide layer (16, 66) is then removed from the surface of the substrate (12, 56) where it is exposed through the passivation layer (18, 68). A reduced surface field region (36, 74) is then formed where the surface of the substrate (12, 56) is exposed through the passivation layer (18, 68). An oxide layer (38, 80) is then formed on the reduced surface field region (36, 74).
摘要翻译：提供一种制造自对准DMOS晶体管的方法。该方法包括在衬底（12,56）的氧化物层（16,66）上形成钝化层（18,68）。然后从衬底（12,56）的表面去除氧化物层（16,66），在衬底的表面上暴露于钝化层（18,68）。然后形成还原表面场区（36,74），其中衬底（12,56）的表面通过钝化层（18,68）暴露。然后在还原表面场区域（36,74）上形成氧化物层（38,80）。

7. 发明授权

US5554873A Semiconductor device having polysilicon resistor with low temperature coefficient 失效
标题翻译：具有低温系数的多晶硅电阻器的半导体装置
公开(公告)号：US5554873A
公开(公告)日：1996-09-10
申请号：US475116
申请日：1995-06-07
申请人： John P. Erdeljac , Louis N. Hutter
发明人： John P. Erdeljac , Louis N. Hutter
IPC分类号： H01L21/02 , H01L21/3215 , H01L27/06 , H01L27/02
CPC分类号： H01L28/20 , H01L21/32155 , H01L27/0688 , Y10S148/136 , Y10S148/146 , Y10S257/904 , Y10S438/934
摘要： A semiconductor device having a p type polysilicon resistor (56) with a moderate sheet resistance and low temperature coefficient of resistance is formed by a double-level polysilicon process. The process also produces n and p-channel transistors (44, 50), a capacitor having upper and lower n type polysilicon capacitor plates (36, 26), an n type polysilicon resistor (32) having a high sheet resistance, and an n type resistor (34) having a low sheet resistance. The p type doping used to form the source/drain regions (48) of p-channel transistor (50) counterdopes n type second level polysilicon to form p type polysilicon resistor (56) without effecting capacitor plates (36, 26) or the n type resistors (32, 34).
摘要翻译：具有中等薄层电阻和低电阻温度系数的p型多晶硅电阻器（56）的半导体器件通过双级多晶硅工艺形成。该工艺还产生n沟道晶体管和p沟道晶体管（44,50），具有上和下n型多晶硅电容器板（36,26）的电容器，具有高薄层电阻的n型多晶硅电阻器（32）和n 型电阻器（34）。用于形成p沟道晶体管（50）的源极/漏极区域（48）的p型掺杂反向型n型第二级多晶硅以形成p型多晶硅电阻器（56）而不影响电容器板（36,26）或n 型电阻器（32,34）。

8. 发明授权

US5436179A Semiconductor process for manufacturing semiconductor devices with increased operating voltages 失效
标题翻译：用于制造具有增加的工作电压的半导体器件的半导体工艺
公开(公告)号：US5436179A
公开(公告)日：1995-07-25
申请号：US177888
申请日：1994-01-05
申请人： John P. Erdeljac , Louis N. Hutter
发明人： John P. Erdeljac , Louis N. Hutter
IPC分类号： H01L27/06 , H01L21/331
CPC分类号： H01L27/0623 , Y10S148/01
摘要： A bipolar transistor is formed on a substrate of a first (P) conductivity type by: forming a collector region (20) of the second conductivity type (N) in the substrate; forming an adjust region (27) of the first (P) conductivity type in the collector region (20); forming a base region (36) of the first (P) conductivity type in the collector region (20), the base region (36) containing the adjust region (27); and forming an emitter region (11) of the second (N) conductivity type in the adjust region (27). The base region (36) is deeper than and more heavily doped than the adjust region (27). The adjust region (27) alters the doping profile of the base-collector junction on the collector (20) side of the junction to increase the breakdown voltage of the transistor.
摘要翻译：通过在衬底中形成第二导电类型（N）的集电极区域（20），在第一（P）导电类型的衬底上形成双极晶体管; 在所述集电区域（20）中形成所述第一（P）导电类型的调节区域（27）。在所述集电区域（20）中形成所述第一（P）导电类型的基极区域（36），所述基极区域（36）包含所述调整区域（27）; 以及在所述调节区域（27）中形成所述第二（N）导电类型的发射极区域（11）。基极区域（36）比调整区域（27）更深，并且掺杂得更多。调整区域（27）改变了结的集电极（20）侧的基极 - 集电极结的掺杂分布，以增加晶体管的击穿电压。

9. 发明授权

US5171699A Vertical DMOS transistor structure built in an N-well CMOS-based BiCMOS process and method of fabrication 失效
标题翻译：内置基于N阱CMOS的BiCMOS工艺和制造方法的垂直DMOS晶体管结构
公开(公告)号：US5171699A
公开(公告)日：1992-12-15
申请号：US592108
申请日：1990-10-03
申请人： Louis N. Hutter , John P. Erdeljac
发明人： Louis N. Hutter , John P. Erdeljac
IPC分类号： H01L21/336 , H01L21/761 , H01L21/8238 , H01L21/8249 , H01L27/06 , H01L27/088 , H01L29/78
CPC分类号： H01L29/66719 , H01L21/761 , H01L21/8238 , H01L21/8249 , H01L29/66712 , H01L29/7809 , H01L27/088
摘要： An integrated circuit is provided wherein bipolar, CMOS and DMOS devices are merged together on one chip with fabrication taking place from a CMOS point of view rather than from a bipolar point of view as in the prior art and p-type epitaxial silicon is used as opposed to n-type epitaxial silicon in the prior art. The integrated circuit uses a P+ substrate upon which a P-epitaxial layer is formed. N+ buried regions isolate the DMOS, PMOS and NPN bipolar devices from the P-epitaxial layer. Each of the devices is formed in a N-well with a first level of polysilicon gate layer providing both the gate and masking for the backgate diffusion of the DMOS device and a sidewall oxide later formed on the first level gate layer to control the diffusion of the source and drain regions of the DMOS device to control channel length. A second level of polysilicon layer provides the gate structures for the CMOS devices as well as one plate of a capacitor. The second level of polysilicon acts as a mask for the source and drain region implants of the CMOS devices. A sidewall oxide later formed on the second polysilicon level further controls the channel lengths of the CMOS structures. A third level of polysilicon provides the second capacitor plate for the capacitor. The DMOS device is isolated from the remaining circuitry by the p-type epitaxial layer and the peripheral portion of the DMOS device is terminated by a PN junction.
摘要翻译：提供了一种集成电路，其中双极性，CMOS和DMOS器件在一个芯片上合并在一起，其制造从CMOS观点而不是从现有技术的双极观点出发，并且p型外延硅被用作与现有技术中的n型外延硅相反。集成电路使用其上形成有P外延层的P +衬底。 N +掩埋区域从P-外延层隔离DMOS，PMOS和NPN双极器件。每个器件形成在具有第一级多晶硅栅极层的N阱中，其提供用于DMOS器件的背栅扩散的栅极和掩模，以及稍后形成在第一级栅极层上的侧壁氧化物以控制扩散 DMOS器件的源极和漏极区域来控制沟道长度。第二级多晶硅层提供CMOS器件的栅极结构以及电容器的一个板。第二级多晶硅作为CMOS器件的源极和漏极区域掩模的掩模。稍后形成在第二多晶硅层上的侧壁氧化物进一步控制CMOS结构的沟道长度。第三级多晶硅为电容器提供第二电容器板。 DMOS器件通过p型外延层与剩余电路隔离，并且DMOS器件的外围部分由PN结终止。

10. 发明授权

US5576233A Method for making an EEPROM with thermal oxide isolated floating gate 失效
标题翻译：制造具有热氧化隔离浮栅的EEPROM的方法
公开(公告)号：US5576233A
公开(公告)日：1996-11-19
申请号：US493377
申请日：1995-06-21
申请人： Louis N. Hutter , John P. Erdeljac
发明人： Louis N. Hutter , John P. Erdeljac
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , H01L27/11524
摘要： A method for making an EEPROM (10) in a semiconductor substrate (40) and EEPROM made according to the method includes forming a gate dielectric (38), such as oxide, nitride, multilayer dielectric, or the like, on a surface of the substrate (40) and forming a polysilicon floating gate (19) on the gate dielectric (38). A control gate (25) is formed at least partially overlying the floating gate (19), and a thermal oxide layer (56) is formed on the floating gate (19) in regions that are not covered by the control gate. Thus, the thermal oxide layer (56) encases any regions of the floating gate (19) uncovered by the control gate (25) and serves as a high quality dielectric to isolate the floating gate (19) from charge loss and other deleterious effects. Then, source and drain regions (21,27) are formed in the substrate (40).
摘要翻译：在半导体衬底（40）中制造EEPROM（10）的方法和根据该方法制造的EEPROM包括在该表面上形成诸如氧化物，氮化物，多层电介质等的栅极电介质（38）衬底（40）并且在栅极电介质（38）上形成多晶硅浮栅（19）。至少部分地覆盖浮置栅极（19）形成控制栅极（25），并且在未被控制栅极覆盖的区域中的浮动栅极（19）上形成热氧化物层（56）。因此，热氧化物层（56）包围由控制栅极（25）未覆盖的浮动栅极（19）的任何区域，并且用作高质量电介质以将浮动栅极（19）与电荷损失和其它有害影响隔离开来。然后，在衬底（40）中形成源区和漏区（21,27）。

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