专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5539753A Method and apparatus for output deselecting of data during test 失效
标题翻译：测试期间输出数据取消选择的方法和装置
公开(公告)号：US5539753A
公开(公告)日：1996-07-23
申请号：US512688
申请日：1995-08-10
申请人： John P. Connor , Stuart J. Hall , Marcel J. Robillard , Luigi Ternullo, Jr.
发明人： John P. Connor , Stuart J. Hall , Marcel J. Robillard , Luigi Ternullo, Jr.
IPC分类号： G11C29/00 , G01R31/3185 , G06F11/273 , G11C29/12 , G06F11/00
CPC分类号： G06F11/2733 , G01R31/318516
摘要： A circuit, as a logic circuit or a memory circuit, having testing latches. The testing latches include an input latch, a slave latch, and true and complement output latches. The output of the slave latch is NANDed with a DESELECT signal to deselect the output latches. The testing latches can be used in a method of characterizing or testing a memory or logic integrated circuit with scannable output latches. At least one output latch has an input latch, a slave latch, and an output latch which may contain a Complement Latch, and a True latch. In the testing process an output of the slave latch is NANDed with a deselect signal to allow testing or characterization by masking known "fail" signals.
摘要翻译：作为具有测试锁存器的逻辑电路或存储器电路的电路。测试锁存器包括输入锁存器，从锁存器，以及真和补输出锁存器。从锁存器的输出与DESELECT信号对准，以取消选择输出锁存器。测试锁存器可以用于表征或测试具有可扫描输出锁存器的存储器或逻辑集成电路的方法。至少一个输出锁存器具有输入锁存器，从锁存器和可包含补码锁存器和真锁存器的输出锁存器。在测试过程中，从锁存器的输出与取消选择信号NAND通过屏蔽已知的“故障”信号进行测试或表征。

2. 发明授权

US5553082A Built-in self-test for logic circuitry at memory array output 失效
标题翻译：用于存储器阵列输出的逻辑电路的内置自检
公开(公告)号：US5553082A
公开(公告)日：1996-09-03
申请号：US432310
申请日：1995-05-01
申请人： John P. Connor , Luigi Ternullo, Jr.
发明人： John P. Connor , Luigi Ternullo, Jr.
IPC分类号： G01R31/317 , G01R31/28 , G06F11/22 , G06F12/16 , G11C29/12 , G11C29/38
CPC分类号： G11C29/38
摘要： Built-in self-testing of embedded logic circuitry at the output of an on-chip memory array is presented. Testing is accomplished by generating on chip a test pattern which is provided to the logic circuitry by writing at least a portion thereof into the memory array and then reading that portion out of the memory array, to the embedded logic circuitry. Three specific embodiments are presented, each of which employs a deterministic looping test pattern that comprises a portion of the generated test pattern. The looping test pattern may be either written through the memory array to the embedded logic circuitry or written around the memory array directly to the logic circuitry.
摘要翻译：介绍了嵌入式逻辑电路在片上存储器阵列输出端的内置自检。通过在芯片上产生测试图案来实现测试，该测试图案通过将至少一部分写入存储器阵列然后将存储器阵列中的该部分读出到嵌入式逻辑电路而提供给逻辑电路。呈现了三个具体实施例，其中的每一个采用包括生成的测试图案的一部分的确定性循环测试图案。循环测试模式可以通过存储器阵列写入嵌入式逻辑电路，或者将存储器阵列直接写入逻辑电路。

3. 发明授权

US6016072A Regulator system for an on-chip supply voltage generator 失效
标题翻译：用于片内电源电压发生器的调节器系统
公开(公告)号：US6016072A
公开(公告)日：2000-01-18
申请号：US46408
申请日：1998-03-23
申请人： Luigi Ternullo, Jr. , Michael C. Stephens
发明人： Luigi Ternullo, Jr. , Michael C. Stephens
IPC分类号： H02M3/07 , G05F1/10
CPC分类号： H02M3/07
摘要： A regulator system includes first and second voltage sensing circuits coupled to a voltage generator control circuit. The first and second voltage sensing circuits are configured to monitor the voltage generated by the on-chip voltage generator (i.e., the on-chip supply voltage) and detect when the on-chip supply voltage reaches thresholds that are predetermined to define a desired range of the on-chip supply voltage. The voltage generator control circuit receives voltage sense signals from the voltage sense circuits and, in response, asserts or de-asserts a control signal received by the on-chip voltage generator so as to activate or de-activate the on-chip voltage generator to maintain the on-chip supply voltage within the desired range. The voltage generator control circuit introduces hysteresis in the generation of the control signal provided to the on-chip voltage generator. As a result of this hysteresis, once the on-chip voltage generator is activated, the voltage generator control circuit only de-activates the on-chip voltage generator when the on-chip supply voltage reaches the higher threshold. Conversely, once the on-chip voltage generator is de-activated, the voltage generator control circuit only activates the on-chip voltage generator when the on-chip supply voltage reaches the lower threshold.
摘要翻译：调节器系统包括耦合到电压发生器控制电路的第一和第二电压感测电路。第一和第二电压感测电路被配置为监视片上电压发生器产生的电压（即，片上电源电压），并且检测片上电源电压何时达到预定的阈值以限定期望的范围的片上电源电压。电压发生器控制电路接收来自电压检测电路的电压检测信号，并作为响应，断言或取消断言由片上电压发生器接收的控制信号，以激活或去激活片上电压发生器将片上电源电压保持在所需范围内。电压发生器控制电路在提供给片上电压发生器的控制信号的产生中引入滞后。作为这种滞后的结果，一旦芯片上的电压发生器被激活，当片上电源电压达到较高的阈值时，电压发生器控制电路仅仅去激活片上电压发生器。相反，一旦片上电压发生器被去激活，当片上电源电压达到较低阈值时，电压发生器控制电路仅激活片上电压发生器。

4. 发明授权

US06246619B1 Self-refresh test time reduction scheme 有权
标题翻译：自刷新测试时间缩短方案
公开(公告)号：US06246619B1
公开(公告)日：2001-06-12
申请号：US09498985
申请日：2000-02-07
申请人： Christopher Ematrudo , Jeffrey S. Earl , Michael C. Stephens, Jr. , Luigi Ternullo, Jr. , Michael F. Vincent
发明人： Christopher Ematrudo , Jeffrey S. Earl , Michael C. Stephens, Jr. , Luigi Ternullo, Jr. , Michael F. Vincent
IPC分类号： G11C2900
CPC分类号： G11C29/50 , G11C29/12
摘要： A circuit for a DRAM is described which, when in test mode, notifies a tester when the self-refresh operation of a dynamic random access memory (DRAM) reaches various stages of completion. By signaling the tester when, i.e., ⅛, ¼, ½, etc. of the self-refresh cycle is reached, the amount of time needed for verification of the self-refresh oscillator frequency is reduced correspondingly by a factor of 8, 4, 2 etc. The signaling of a partial test time is achieved by adding self-refresh status logic circuits which decode the high order most significant bits of the refresh address counter. The activation of the third most significant bit signals completion of ⅛th of the self-refresh cycle, the activation of the second most significant bit signals completion of ¼th of the self-refresh cycle, the activation of the most significant bit signals completion of ½ of the self-refresh cycle, and deactivation of the most significant bit signals completion of the self-refresh cycle.
摘要翻译：描述了用于DRAM的电路，当处于测试模式时，当动态随机存取存储器（DRAM）的自刷新操作达到各种完成阶段时，通知测试者。当达到自刷新周期的⅛，¼，½等时，通过信号通知测试仪，验证自刷新振荡器频率所需的时间相应减少了8倍，4倍， 2等等。通过添加对刷新地址计数器的高阶最高有效位进行解码的自刷新状态逻辑电路来实现部分测试时间的信令。第三最高有效位的激活信号完成自刷新周期的第‧秒，第二最高有效位信号的激活完成自刷新周期的第1/4，最高有效位信号的激活完成为1/2的自刷新周期，以及最高有效位信号的去激活完成自刷新周期。

5. 发明授权

US6061296A Multiple data clock activation with programmable delay for use in multiple CAS latency memory devices 有权
标题翻译：多个数据时钟激活与可编程延迟，用于多个CAS延迟存储器件
公开(公告)号：US6061296A
公开(公告)日：2000-05-09
申请号：US135252
申请日：1998-08-17
申请人： Luigi Ternullo, Jr. , Christopher Ematrudo , Michael C. Stephens, Jr.
发明人： Luigi Ternullo, Jr. , Christopher Ematrudo , Michael C. Stephens, Jr.
IPC分类号： G11C7/10 , G11C8/18
CPC分类号： G11C7/1039 , G11C7/1045 , G11C7/1051 , G11C7/1072
摘要： A timing scheme for multiple data clock activation with programmable delay for use in accessing a multiple CAS latency memory device. A multi-stage data propagation path is used to propagate a bit being accessed from a memory array of the device to an output line. Timing signals are generated so that in a CAS latency three mode, the timing signal that activates the next to last stage of the propagation path is triggered by an output clock signal that activates the last stage of the propagation path so that pulse from the output clock signal does not overlap with pulses of the timing signal that activates the previous stage. This timing scheme ensures the data lines feeding the last stage are not being restored while the last stage is sensing these data lines. A programmable delay circuit is used to adjust the timing of the output clock signal.
摘要翻译：具有可编程延迟的多数据时钟激活的定时方案，用于访问多个CAS延迟存储器设备。多级数据传播路径用于将正在访问的位从设备的存储器阵列传播到输出线。产生定时信号，使得在CAS等待三个模式中，激活传播路径的最后一级的定时信号由激活传播路径的最后一级的输出时钟信号触发，使得来自输出时钟的脉冲信号与激活前一级的定时信号的脉冲不重叠。该定时方案确保在最后一级感测这些数据线时，馈送最后一级的数据线不被恢复。可编程延迟电路用于调整输出时钟信号的时序。

6. 发明授权

US5790564A Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor 失效
标题翻译：具有可编程模式发生器的内存自检电路的存储器阵列，用于允许对相邻存储单元的唯一的读/写操作及其方法
公开(公告)号：US5790564A
公开(公告)日：1998-08-04
申请号：US485296
申请日：1995-06-07
申请人： Robert Dean Adams , John Connor , Garrett Stephen Koch , Luigi Ternullo, Jr.
发明人： Robert Dean Adams , John Connor , Garrett Stephen Koch , Luigi Ternullo, Jr.
IPC分类号： G11C29/12 , G11C29/10 , G11C29/36 , G01R31/28
CPC分类号： G11C29/36
摘要： An ABIST circuit for testing a memory array has a blanket write subcycle (WC), an RC3 subcycle, and an RC4 subcycle. The ABIST circuit includes a programmable pattern generator that provides eight programmable data bits, eight programmable read/write bits, and two programmable address frequency bits to determine the specific test patterns applied to the memory array. The address frequency bits determine how many memory cycles will be performed on each cell of the memory array. In X1 mode, only one memory cycle is performed on each cell during any given subcycle. In X2 mode, two memory cycles are performed on each cell, allowing a cell to be written, then subsequently read in the same subcycle. In X4 mode, four memory cycles are performed on each cell, and in X8 mode, all eight bits of read/write and data are used on each cell, resulting in eight memory cycles for each cell within the memory array.
摘要翻译：用于测试存储器阵列的ABIST电路具有毯子写入子周期（WC），RC3子周期和RC4子周期。 ABIST电路包括一个可编程模式发生器，提供八个可编程数据位，八个可编程读/写位和两个可编程地址频率位，以确定应用于存储器阵列的特定测试模式。地址频率位决定在存储器阵列的每个单元上执行多少个内存周期。在X1模式下，在任何给定的子周期内，每个单元只执行一个存储周期。在X2模式下，对每个单元执行两个存储周期，允许单元写入，然后在相同的子周期中读取。在X4模式下，对每个单元执行四个存储周期，在X8模式下，每个单元都使用8位读/写和数据，从而为存储器阵列内的每个单元提供8个存储周期。

7. 发明授权

US5745498A Rapid compare of two binary numbers 失效
标题翻译：快速比较两个二进制数
公开(公告)号：US5745498A
公开(公告)日：1998-04-28
申请号：US661575
申请日：1996-06-11
申请人： Robert Dean Adams , John Connor , Garrett Stephen Koch , Luigi Ternullo, Jr.
发明人： Robert Dean Adams , John Connor , Garrett Stephen Koch , Luigi Ternullo, Jr.
IPC分类号： G01R31/26 , G01R31/28 , G01R31/3185 , G06F7/02 , G11C29/00 , G11C29/12 , G11C29/26 , G11C29/40 , G11C29/56 , H01L21/66 , G06F11/00
CPC分类号： G11C29/26 , G01R31/318527 , G06F7/02 , G11C29/40
摘要： A test method and structure is provided to determine the end count of a predetermined succession or series of binary numbers wherein one number and its relation in the succession to the end count number is known. The structure includes a circuit for generating a binary digit output and a device for storing at least a portion of the said one number which preferably is the penultimate number in a sequential series. A succession of binary numbers is generated as output of the circuit. the outputted numbers are compared to the portion of the stored number. A READY signal is outputted when the stored number compares with the outputted number. On a subsequent cycle, a control signal is generated when the generated number following the READY signal corresponds to the end count number. The inventor also contemplates programmable end count numbers.
摘要翻译：提供了一种测试方法和结构来确定预定的一系列二进制数的结束计数，其中一个数目及其在终止计数序列中的关系是已知的。该结构包括用于产生二进制数字输出的电路和用于存储所述一个数字的至少一部分的装置，其优选地是顺序序列中的倒数第二个数字。产生一系列二进制数作为电路的输出。将输出的数字与存储的数字的部分进行比较。当存储的数字与输出的数字进行比较时，输出READY信号。在随后的周期中，当READY信号之后的生成数字对应于结束计数号时，产生控制信号。发明人还考虑了可编程的终端计数。

8. 发明授权

US5740098A Using one memory to supply addresses to an associated memory during testing 失效
公开(公告)号：US5740098A
公开(公告)日：1998-04-14
申请号：US671279
申请日：1996-06-27
申请人： Robert Dean Adams , John Connor , James J. Covino , Roy Childs Flaker , Garrett Stephen Koch , Alan Lee Roberts , Jose Roriz Sousa , Luigi Ternullo, Jr.
发明人： Robert Dean Adams , John Connor , James J. Covino , Roy Childs Flaker , Garrett Stephen Koch , Alan Lee Roberts , Jose Roriz Sousa , Luigi Ternullo, Jr.
IPC分类号： G06F12/16 , G06F12/08 , G11C8/10 , G11C15/00 , G11C15/04 , G11C29/00 , G11C29/02 , G11C29/10 , G11C29/12 , G11C29/56
CPC分类号： G11C29/12 , G06F12/0893 , G11C15/00 , G11C8/10 , G11C29/10
摘要： An associated memory structure having a plurality of memories amenable for testing and a method of testing the memories is provided. First and second memories are formed, wherein data in the first memory provides a basis for at least a portion of the input to the second memory during functional operation of two memories. Preferably, an output latch for receiving the output test data from the first memory is provided. Means are provided for loading the first memory with data which is utilized as a basis for providing at least a portion of the input to the second memory. An access path from the output port of the first memory to the input port of the second memory allows use of the data in the first memory to generate at least a portion of the input to the second memory. The first memory is first tested independently of the second memory. Thereafter, the first memory is loaded with preconditioned data that is used as a basis for inputs to the second memory during testing of the second memory. The second memory is then tested by generating inputs to the first memory during testing of the second memory. Thus, outputs of the first memory constitute at least a portion of test data inputted to the second memory. A latch is provided to capture the output of the test data from the second memory.

9. 发明授权

US5582703A Method of fabricating an ultra-high resolution three-color screen 失效
标题翻译：制造超高分辨率三色荧光屏的方法
公开(公告)号：US5582703A
公开(公告)日：1996-12-10
申请号：US354342
申请日：1994-12-12
申请人： Esther Sluzky , Santosh K. Kurinec , Kenneth R. Hesse , Luigi Ternullo, Jr.
发明人： Esther Sluzky , Santosh K. Kurinec , Kenneth R. Hesse , Luigi Ternullo, Jr.
IPC分类号： C25D13/02 , C25D13/22
CPC分类号： C25D13/02 , C25D13/22
摘要： Phosphor color screens with triad pitches of 150 .mu.m and less are fabricated by a combination of modified microelectronic processing techniques and electrophoretic coating of the phosphors and black screen. Indeed, triad pitches based on 15 .mu.m color line width and 5 .mu.m black matrix between colors are achievable. The method of the invention for fabricating a three-color screen comprises (a) forming a conductive coating on a major surface of the substrate; (b) forming multiple masking layers on the conductive coating; (c) patterning the masking layers in a prescribed pattern to form a first plurality of openings therein to expose first portions of the conductive coating; (d) electrophoretically depositing a first phosphor on the exposed first portions of the conductive coating; and (e) repeating steps (b) through (d) three times (1) to deposit a second phosphor on second portions of the conductive coating, (2) to deposit a third phosphor on third portions of the conductive coating, and (3) to deposit a black layer around all three color portions, to thereby define a plurality of triads of said first, second, and third colors in spaced relationship, separated by the black layer.
摘要翻译：通过改进的微电子处理技术和荧光体和黑色屏幕的电泳涂层的组合制造具有150μm或更小的三单位分数的荧光体彩色滤光片。实际上，可以实现基于15μm色线宽度和5μm黑色矩阵之间的三色组间距。用于制造三色屏的本发明的方法包括：（a）在所述基材的主表面上形成导电涂层; （b）在导电涂层上形成多个掩模层; （c）以规定的图案图案化掩模层以在其中形成第一多个开口以暴露导电涂层的第一部分; （d）在导电涂层的暴露的第一部分上电泳沉积第一荧光体; 和（e）重复步骤（b）至（d）三次（1）以在导电涂层的第二部分上沉积第二荧光体，（2）在导电涂层的第三部分上沉积第三荧光体，和（3 ）以在所有三个颜色部分周围沉积黑色层，从而以间隔的关系限定由黑色层隔开的所述第一，第二和第三颜色的多个三元组。

10. 发明授权

US06208197B1 Internal charge pump voltage limit control 有权
标题翻译：内部电荷泵电压限制控制
公开(公告)号：US06208197B1
公开(公告)日：2001-03-27
申请号：US09262503
申请日：1999-03-04
申请人： Luigi Ternullo, Jr. , Michael C. Stephens, Jr.
发明人： Luigi Ternullo, Jr. , Michael C. Stephens, Jr.
IPC分类号： G05F110
CPC分类号： H02M3/07
摘要： A charge pump limits the voltages at nodes internal to the charge pump to reduce the risk of junction breakdown in the charge pump. The charge pump includes a first pump circuit, a second pump circuit, a first clamp and a second clamp. The first clamp limits the voltage level of a well by providing a current path from the well to the output lead when the voltage level of the well reaches a first predetermined limit. The voltage level at a node from which charge is redistributed to the well is limited by the second clamp, which is configured to provide a conductive path from the node to the output lead when the voltage level of the node reaches a second predetermined limit. The pump circuits can each include a logic circuit that is configured, depending on the level of an external supply voltage, to reduce the rate at which the capacitor node is boosted when the external supply voltage is relatively high. The logic circuit can also vary the voltage difference between the capacitor node and the external supply voltage to decrease the relative voltage level at the capacitor node relative to the level of the external supply voltage. These features also help reduce the risk of junction breakdown in the charge pump.
摘要翻译：电荷泵限制电荷泵内部节点处的电压，以降低电荷泵中结点破裂的风险。电荷泵包括第一泵电路，第二泵电路，第一夹具和第二夹具。当阱的电压水平达到第一预定极限时，第一钳位器通过提供从井到输出引线的电流路径来限制阱的电压电平。电荷再分配到阱的节点处的电压电平受到第二钳位限制，第二钳位器被配置为当节点的电压电平达到第二预定极限时，提供从节点到输出引线的导电路径。泵电路可以各自包括根据外部电源电压的电平配置的逻辑电路，以在外部电源电压相对较高时降低电容器节点升压的速率。逻辑电路还可以改变电容器节点和外部电源电压之间的电压差，以降低电容器节点处的相对电压相对于外部电源电压的电平。这些功能还有助于降低电荷泵中结点破裂的风险。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式