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1. 发明授权

US06246619B1 Self-refresh test time reduction scheme 有权
标题翻译：自刷新测试时间缩短方案
公开(公告)号：US06246619B1
公开(公告)日：2001-06-12
申请号：US09498985
申请日：2000-02-07
申请人： Christopher Ematrudo , Jeffrey S. Earl , Michael C. Stephens, Jr. , Luigi Ternullo, Jr. , Michael F. Vincent
发明人： Christopher Ematrudo , Jeffrey S. Earl , Michael C. Stephens, Jr. , Luigi Ternullo, Jr. , Michael F. Vincent
IPC分类号： G11C2900
CPC分类号： G11C29/50 , G11C29/12
摘要： A circuit for a DRAM is described which, when in test mode, notifies a tester when the self-refresh operation of a dynamic random access memory (DRAM) reaches various stages of completion. By signaling the tester when, i.e., ⅛, ¼, ½, etc. of the self-refresh cycle is reached, the amount of time needed for verification of the self-refresh oscillator frequency is reduced correspondingly by a factor of 8, 4, 2 etc. The signaling of a partial test time is achieved by adding self-refresh status logic circuits which decode the high order most significant bits of the refresh address counter. The activation of the third most significant bit signals completion of ⅛th of the self-refresh cycle, the activation of the second most significant bit signals completion of ¼th of the self-refresh cycle, the activation of the most significant bit signals completion of ½ of the self-refresh cycle, and deactivation of the most significant bit signals completion of the self-refresh cycle.
摘要翻译：描述了用于DRAM的电路，当处于测试模式时，当动态随机存取存储器（DRAM）的自刷新操作达到各种完成阶段时，通知测试者。当达到自刷新周期的⅛，¼，½等时，通过信号通知测试仪，验证自刷新振荡器频率所需的时间相应减少了8倍，4倍， 2等等。通过添加对刷新地址计数器的高阶最高有效位进行解码的自刷新状态逻辑电路来实现部分测试时间的信令。第三最高有效位的激活信号完成自刷新周期的第‧秒，第二最高有效位信号的激活完成自刷新周期的第1/4，最高有效位信号的激活完成为1/2的自刷新周期，以及最高有效位信号的去激活完成自刷新周期。

2. 发明授权

US6061296A Multiple data clock activation with programmable delay for use in multiple CAS latency memory devices 有权
标题翻译：多个数据时钟激活与可编程延迟，用于多个CAS延迟存储器件
公开(公告)号：US6061296A
公开(公告)日：2000-05-09
申请号：US135252
申请日：1998-08-17
申请人： Luigi Ternullo, Jr. , Christopher Ematrudo , Michael C. Stephens, Jr.
发明人： Luigi Ternullo, Jr. , Christopher Ematrudo , Michael C. Stephens, Jr.
IPC分类号： G11C7/10 , G11C8/18
CPC分类号： G11C7/1039 , G11C7/1045 , G11C7/1051 , G11C7/1072
摘要： A timing scheme for multiple data clock activation with programmable delay for use in accessing a multiple CAS latency memory device. A multi-stage data propagation path is used to propagate a bit being accessed from a memory array of the device to an output line. Timing signals are generated so that in a CAS latency three mode, the timing signal that activates the next to last stage of the propagation path is triggered by an output clock signal that activates the last stage of the propagation path so that pulse from the output clock signal does not overlap with pulses of the timing signal that activates the previous stage. This timing scheme ensures the data lines feeding the last stage are not being restored while the last stage is sensing these data lines. A programmable delay circuit is used to adjust the timing of the output clock signal.
摘要翻译：具有可编程延迟的多数据时钟激活的定时方案，用于访问多个CAS延迟存储器设备。多级数据传播路径用于将正在访问的位从设备的存储器阵列传播到输出线。产生定时信号，使得在CAS等待三个模式中，激活传播路径的最后一级的定时信号由激活传播路径的最后一级的输出时钟信号触发，使得来自输出时钟的脉冲信号与激活前一级的定时信号的脉冲不重叠。该定时方案确保在最后一级感测这些数据线时，馈送最后一级的数据线不被恢复。可编程延迟电路用于调整输出时钟信号的时序。

3. 发明授权

US06764867B1 Reticle option layer detection method 有权
标题翻译：掩模选项层检测方法
公开(公告)号：US06764867B1
公开(公告)日：2004-07-20
申请号：US09764243
申请日：2001-01-19
申请人： Michael C. Stephens, Jr. , Christopher Ematrudo , Jeffrey S. Earl
发明人： Michael C. Stephens, Jr. , Christopher Ematrudo , Jeffrey S. Earl
IPC分类号： H01L2100
CPC分类号： H01L22/20 , H01L22/34 , H01L2924/3011
摘要： A new method of detecting a reticle option layer in an integrated circuit device has been achieved. The method may be applied to detect the presence of the threshold voltage implantation reticle option layer by direct die probing or by probing a pin of a package integrated circuit. The current through a first MOS transistor is measured by forcing a test voltage on the drain and the gate. The gate and the drain of the first MOS transistor are connected together while the source is connected to a reference voltage. The first MOS transistor has the standard threshold implantation but not the threshold voltage reticle option. The current through a second MOS transistor is measured by forcing the same test voltage on the drain and the gate. The gate and said drain of the second MOS transistor are connected together while the source is connected to a reference voltage. The second MOS transistor has the standard threshold voltage implantation and the threshold voltage implantation reticle option layer. The current through the first NMOS transistor and the current through the second MOS transistor are compared to detect the presence of the threshold voltage implantation reticle option layer in the integrated circuit device.
摘要翻译：已经实现了在集成电路装置中检测掩模版选择层的新方法。该方法可以用于通过直接芯片探测或通过探测封装集成电路的引脚来检测阈值电压注入掩模版选择层的存在。通过在漏极和栅极上施加测试电压来测量通过第一MOS晶体管的电流。第一MOS晶体管的栅极和漏极连接在一起，同时源极连接到参考电压。第一个MOS晶体管具有标准阈值植入，但不是阈值电压掩模版选项。通过第二MOS晶体管的电流通过在漏极和栅极上施加相同的测试电压来测量。第二MOS晶体管的栅极和漏极连接在一起，同时源极连接到参考电压。第二MOS晶体管具有标准阈值电压注入和阈值电压注入掩模版选择层。比较通过第一NMOS晶体管的电流和通过第二MOS晶体管的电流，以检测集成电路器件中阈值电压注入掩模版选项层的存在。

4. 发明授权

US06195309B1 Timing circuit for a burst-mode address counter 有权
标题翻译：脉冲串地址计数器的定时电路
公开(公告)号：US06195309B1
公开(公告)日：2001-02-27
申请号：US09320427
申请日：1999-05-26
申请人： Christopher Ematrudo
发明人： Christopher Ematrudo
IPC分类号： G11C800
CPC分类号： G11C7/1018 , G11C7/22
摘要： A burst-mode capable RAM chip includes a timing circuit for clocking a burst counter during a burst transfer. In response to an input indicating the beginning of the burst transfer, the timing circuit generates a first signal that loads the initial address of the burst transfer into the latches of a burst counter. Then, the timing circuit generates a second signal to increment the burst counter to the second address in the burst transfer after the load of the initial address has successfully completed but prior to the second clock cycle. Finally, the timing circuit generates subsequent signals to increment the burst counter through the remaining addresses of the burst transfer. Each of the subsequent signals is generated in response to an input from the system clock.
摘要翻译：具有突发模式的RAM芯片包括用于在突发传送期间对突发计数器进行计时的定时电路。响应于指示突发传输的开始的输入，定时电路产生将突发传输的初始地址加载到突发计数器的锁存器中的第一信号。然后，在初始地址的加载成功完成之后但在第二时钟周期之前，定时电路产生第二信号，以将突发计数器增加到突发传输中的第二地址。最后，定时电路产生后续信号，以通过突发传送的剩余地址来增加突发计数器。响应于来自系统时钟的输入而产生每个后续信号。

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