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1. 发明授权

US5740098A Using one memory to supply addresses to an associated memory during testing 失效
公开(公告)号：US5740098A
公开(公告)日：1998-04-14
申请号：US671279
申请日：1996-06-27
申请人： Robert Dean Adams , John Connor , James J. Covino , Roy Childs Flaker , Garrett Stephen Koch , Alan Lee Roberts , Jose Roriz Sousa , Luigi Ternullo, Jr.
发明人： Robert Dean Adams , John Connor , James J. Covino , Roy Childs Flaker , Garrett Stephen Koch , Alan Lee Roberts , Jose Roriz Sousa , Luigi Ternullo, Jr.
IPC分类号： G06F12/16 , G06F12/08 , G11C8/10 , G11C15/00 , G11C15/04 , G11C29/00 , G11C29/02 , G11C29/10 , G11C29/12 , G11C29/56
CPC分类号： G11C29/12 , G06F12/0893 , G11C15/00 , G11C8/10 , G11C29/10
摘要： An associated memory structure having a plurality of memories amenable for testing and a method of testing the memories is provided. First and second memories are formed, wherein data in the first memory provides a basis for at least a portion of the input to the second memory during functional operation of two memories. Preferably, an output latch for receiving the output test data from the first memory is provided. Means are provided for loading the first memory with data which is utilized as a basis for providing at least a portion of the input to the second memory. An access path from the output port of the first memory to the input port of the second memory allows use of the data in the first memory to generate at least a portion of the input to the second memory. The first memory is first tested independently of the second memory. Thereafter, the first memory is loaded with preconditioned data that is used as a basis for inputs to the second memory during testing of the second memory. The second memory is then tested by generating inputs to the first memory during testing of the second memory. Thus, outputs of the first memory constitute at least a portion of test data inputted to the second memory. A latch is provided to capture the output of the test data from the second memory.

2. 发明授权

US5715188A Method and apparatus for parallel addressing of CAMs and RAMs 失效
标题翻译：用于并行寻址CAM和RAM的方法和装置
公开(公告)号：US5715188A
公开(公告)日：1998-02-03
申请号：US597773
申请日：1996-02-07
申请人： James J. Covino , Roy Childs Flaker , Alan Lee Roberts , Jose Roriz Sousa
发明人： James J. Covino , Roy Childs Flaker , Alan Lee Roberts , Jose Roriz Sousa
IPC分类号： G06F12/16 , G06F12/08 , G11C8/10 , G11C15/00 , G11C15/04 , G11C29/00 , G11C29/02 , G11C29/10 , G11C29/12 , G11C29/56 , G11C13/00
CPC分类号： G11C29/12 , G06F12/0893 , G11C15/00 , G11C8/10 , G11C29/10
摘要： A method and apparatus are provided for parallel addressing a CAM and a RAM, and also for using a single wordline to address the CAM and/or RAM. The CAM and RAM are addressed using a common wordline, and the common wordline is also used for writing to the CAM during a write cycle and strobing the CAM during a read cycle.
摘要翻译：提供了一种用于并行寻址CAM和RAM的方法和装置，并且还用于使用单个字线来寻址CAM和/或RAM。使用公共字线寻址CAM和RAM，并且在读周期期间通用字线也用于写入CAM，并在读周期期间选通CAM。

3. 发明授权

US5721863A Method and structure for accessing semi-associative cache memory using multiple memories to store different components of the address 失效
标题翻译：使用多个存储器访问半关联高速缓冲存储器以存储地址的不同组件的方法和结构
公开(公告)号：US5721863A
公开(公告)日：1998-02-24
申请号：US593639
申请日：1996-01-29
申请人： James J. Covino , Roy Childs Flaker , Alan Lee Roberts , Jose Roriz Sousa
发明人： James J. Covino , Roy Childs Flaker , Alan Lee Roberts , Jose Roriz Sousa
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/1054 , G06F12/0864
摘要： A structure and method of operation of a cache memory are provided. The cache memory is organized such that the data on a given line of any page of the main memory is stored on the same line of a page of the cache memory. Two address memories are provided, one containing the first eight bits of the virtual address of the page of the data in main memory and the second the entire real page address in main memory. When an address is asserted on the bus, the line component of the address causes each of those lines from the cache memory to read out to a multiplexor. At the same time, the eight bit component of the virtual address is compared in the first memory to the eight bits of each line stored in the first memory, and if a compare is made, the data on that line from that page of cache memory is read to the CPU. Also, the entire real address is compared in the second memory, and if a match does not occur, the data from the cache to the CPU is flagged as invalid data. A structure and method are also provided to determine if duplicate addresses exist in the second address memory.
摘要翻译：提供了高速缓冲存储器的操作结构和操作方法。高速缓冲存储器被组织使得主存储器的任何页面的给定行上的数据被存储在高速缓冲存储器的页面的同一行上。提供两个地址存储器，一个包含主存储器中的数据页的虚拟地址的前八位，第二个是主存储器中的整个实际页地址。当总线上的地址被断言时，地址的线路分量使来自高速缓冲存储器的那些线路中的每条线路读出到多路复用器。同时，将虚拟地址的八位分量在第一存储器中比较到存储在第一存储器中的每一行的八位，如果进行比较，则从高速缓冲存储器页面那一行的数据被读取到CPU。而且，在第二存储器中比较整个实际地址，并且如果不发生匹配，则从缓存到CPU的数据被标记为无效数据。还提供了一种结构和方法来确定在第二地址存储器中是否存在重复的地址。

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