专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06903411B1 Architecture for circuit connection of a vertical transistor 有权
标题翻译：垂直晶体管的电路连接架构
公开(公告)号：US06903411B1
公开(公告)日：2005-06-07
申请号：US09648164
申请日：2000-08-25
申请人： Yih-Feng Chyan , John Michael Hergenrother , Donald Paul Monroe
发明人： Yih-Feng Chyan , John Michael Hergenrother , Donald Paul Monroe
IPC分类号： H01L27/10 , H01L21/336 , H01L21/768 , H01L21/8234 , H01L21/8238 , H01L21/8244 , H01L27/092 , H01L27/11 , H01L29/78 , H01L29/778
CPC分类号： H01L29/66666 , H01L21/76895 , H01L21/823885 , H01L27/11 , H01L27/1104 , H01L29/7827
摘要： An architecture for connection between regions in or adjacent a semiconductor layer. According to one embodiment a semiconductor device includes a first layer of semiconductor material and a first field effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The device includes a second field effect transistor also having a first source/drain region formed in the first layer. A channel region of the second transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. A conductive layer comprising a metal is positioned between the first source/drain region of each transistor to conduct current from one first source/drain region to the other first source/drain region.In another embodiment a first device region, is formed on a semiconductor layer. A second device region, is also formed on the semiconductor layer. A conductor layer comprising metal is positioned adjacent the first and second device regions to effect electrical connection between the first and second device regions. A first field effect transistor gate region is formed over the first device region and the conductor layer and a second field effect transistor gate region is formed over the second device region and the conductor layer.
摘要翻译：用于在半导体层中或邻近半导体层之间的区域之间连接的架构。根据一个实施例，半导体器件包括第一层半导体材料和第一场效应晶体管，其具有形成在第一层中的第一源/漏区。在第一层上形成晶体管的沟道区，并且在沟道区上形成相关联的第二源极/漏极区。该器件包括第二场效应晶体管，其还具有形成在第一层中的第一源/漏区。在第一层上形成第二晶体管的沟道区，并且在沟道区上形成相关联的第二源极/漏极区。包括金属的导电层位于每个晶体管的第一源极/漏极区之间，以将电流从一个第一源极/漏极区传导到另一个第一源极/漏极区。在另一个实施例中，第一器件区域形成在半导体层上。第二器件区域也形成在半导体层上。包括金属的导体层定位成邻近第一和第二器件区域以实现第一和第二器件区域之间的电连接。第一场效应晶体管栅极区域形成在第一器件区域上，并且导体层和第二场效应晶体管栅极区域形成在第二器件区域和导体层上。

2. 发明授权

US06653181B2 CMOS integrated circuit having vertical transistors and a process for fabricating same 有权
标题翻译：具有垂直晶体管的CMOS集成电路及其制造方法
公开(公告)号：US06653181B2
公开(公告)日：2003-11-25
申请号：US10211674
申请日：2002-08-02
申请人： John Michael Hergenrother , Donald Paul Monroe
发明人： John Michael Hergenrother , Donald Paul Monroe
IPC分类号： H01L218238
CPC分类号： H01L21/823885 , H01L27/0688 , H01L27/092
摘要： A process for fabricating a CMOS integrated circuit with vertical MOSFET devices is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET devices. After the at least three layers of material are formed on the substrate, the resulting structure is selectively doped to form an n-type region and a p-type region in the structure. Windows or trenches are formed in the layers in both the n-type region and the p-type region. The windows terminate at the surface of the silicon substrate in which one of either a source or drain region is formed. The windows or trenches are then filled with a semiconductor material. This semiconductor plug becomes the vertical channel of the transistor. Therefore the crystalline semiconductor plug is doped to form a source extension, a drain extension, and a channel region in the plug. Subsequent processing forms the other of a source or drain on top of the vertical channel and removes the sacrificial second material layer. The removal of the sacrificial second layer exposes a portion of the doped semiconductor plug. The device gate dielectric is then formed on the exposed portion of the doped semiconductor plug. The gate electrode is then deposited. The physical gate length of the resulting device corresponds to the deposited thickness of the second material layer.
摘要翻译：公开了一种用于制造具有垂直MOSFET器件的CMOS集成电路的工艺。在该过程中，在半导体衬底上依次形成至少三层材料。三层被布置成使得第二层介于第一层和第三层之间。第二层是牺牲性的，即在随后的处理期间该层被完全去除。第二层的厚度限定了垂直MOSFET器件的物理栅极长度。在衬底上形成至少三层材料之后，所得结构被选择性地掺杂以在该结构中形成n型区域和p型区域。 Windows或沟槽形成在n型区域和p型区域中的层中。窗口终止于其中形成源极或漏极区域之一的硅衬底的表面。然后用半导体材料填充窗口或沟槽。该半导体插头成为晶体管的垂直沟道。因此，晶体半导体插头被掺杂以在插头中形成源延伸部，漏极延伸部和沟道区域。随后的处理形成垂直通道顶部的源极或漏极中的另一个，并去除牺牲的第二材料层。牺牲第二层的去除暴露了掺杂半导体插件的一部分。然后在掺杂半导体插头的暴露部分上形成器件栅极电介质。然后沉积栅电极。所得装置的物理栅极长度对应于第二材料层的沉积厚度。

3. 发明授权

US06197641B1 Process for fabricating vertical transistors 有权
标题翻译：制造垂直晶体管的工艺
公开(公告)号：US06197641B1
公开(公告)日：2001-03-06
申请号：US09335707
申请日：1999-06-18
申请人： John Michael Hergenrother , Donald Paul Monroe , Gary Robert Weber
发明人： John Michael Hergenrother , Donald Paul Monroe , Gary Robert Weber
IPC分类号： H01L21336
CPC分类号： H01L29/66666 , H01L29/161 , H01L29/7827 , H01L29/78642
摘要： A process for fabricating a vertical MOSFET device for use in integrated circuits is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET. In the process the first and third layers have etch rates that are significantly lower than the etch rate of the second layer in an etchant selected to remove the second layer. The top layer, which is either the third or subsequent layer, is a stop layer for a subsequently performed mechanical polishing step that is used to remove materials formed over the at least three layers. After the at least three layers of material are formed on the substrate, a window or trench is formed in the layers. The window terminates at the surface of the silicon substrate in which one of either a source or drain region is formed in the silicon substrate. The window or trench is then filled with a semiconductor material. This semiconductor plug becomes the vertical channel of the transistor. Therefore the crystalline semiconductor plug is doped to form a source extension, a drain extension, and a channel region in the plug. Subsequent processing forms the other of a source or drain on top of the vertical channel and removes the sacrificial second material layer. The removal of the sacrificial second layer exposes a portion of the doped semiconductor plug. The device gate dielectric is then formed on the exposed portion of the doped semiconductor plug. The gate electrode is then deposited. The physical gate length of the resulting device corresponds to the deposited thickness of the second material layer.
摘要翻译：公开了用于制造用于集成电路的垂直MOSFET器件的工艺。在该过程中，在半导体衬底上依次形成至少三层材料。三层被布置成使得第二层介于第一层和第三层之间。第二层是牺牲性的，即在随后的处理期间该层被完全去除。第二层的厚度限定了垂直MOSFET的物理栅极长度。在该过程中，第一层和第三层的蚀刻速率明显低于蚀刻剂中被选择去除第二层的第二层的蚀刻速率。顶层，其是第三层或后续层，是用于随后执行的机械抛光步骤的停止层，其用于去除在至少三层上形成的材料。在衬底上形成至少三层材料之后，在这些层中形成窗口或沟槽。窗口终止于在硅衬底中形成源区或漏区之一的硅衬底的表面。然后用半导体材料填充窗口或沟槽。该半导体插头成为晶体管的垂直沟道。因此，晶体半导体插头被掺杂以在插头中形成源延伸部，漏极延伸部和沟道区域。随后的处理形成垂直通道顶部的源极或漏极中的另一个，并去除牺牲的第二材料层。牺牲第二层的去除暴露了掺杂半导体插件的一部分。然后在掺杂半导体插头的暴露部分上形成器件栅极电介质。然后沉积栅电极。所得装置的物理栅极长度对应于第二材料层的沉积厚度。

4. 发明申请

US20080157404A1 TRENCH STRUCTURE AND METHOD FOR CO-ALIGNMENT OF MIXED OPTICAL AND ELECTRON BEAM LITHOGRAPHIC FABRICATION LEVELS 失效
标题翻译：混合光学和电子束光刻制造水平对准的TRENCH结构和方法
公开(公告)号：US20080157404A1
公开(公告)日：2008-07-03
申请号：US11618957
申请日：2007-01-02
申请人： David Michael Fried , John Michael Hergenrother , Sharee Jane McNab , Michael J. Rooks , Anna Topol
发明人： David Michael Fried , John Michael Hergenrother , Sharee Jane McNab , Michael J. Rooks , Anna Topol
IPC分类号： H01L23/544 , G03F7/20 , H01L21/76
CPC分类号： H01L21/76283 , B82Y10/00 , B82Y40/00 , G03F7/7045 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01J37/3174 , H01L21/3081 , H01L21/823481 , H01L21/84 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.
摘要翻译：一种用于将集成电路芯片的制造级别的第一组特征对准到形成在衬底中的电子束对准目标并使用电子束光刻形成第一组特征并用于对准第二组特征的方法将集成电路芯片的制造水平设置到形成在基板中的光学对准目标，并且使用光刻法形成第二组特征，所述光学对准目标本身与电子束对准目标对准。还有一种形成电子束对准靶的方法和结构。

5. 发明授权

US06821851B2 Method of making ultra thin body vertical replacement gate MOSFET 有权
标题翻译：制造超薄体垂直替代栅极MOSFET的方法
公开(公告)号：US06821851B2
公开(公告)日：2004-11-23
申请号：US10649140
申请日：2003-08-27
申请人： John Michael Hergenrother , Pranav Kalavade
发明人： John Michael Hergenrother , Pranav Kalavade
IPC分类号： H01L218236
CPC分类号： H01L21/823487
摘要： A method of fabricating a VRG MOSFET includes the steps of: (a) forming a VRG multilayer stack; (b) forming a trench in the stack; (c) depositing an ultra thin, amorphous semiconductor (&agr;-semic) layer on the sidewalls of the trench (portions of the ultra thin layer on the sidewalls of the trench will ultimately form the channel or ultra thin body (UTB) of the MOSFET); (d) forming a thicker, &agr;-semic sacrificial layer on the ultra thin layer; (e) annealing the &agr;-semic layers to recrystallize them into single crystal layers; (f) selectively removing the recrystallized sacrificial layer; and (g) performing additional steps to complete the VRG MOSFET. In general, the sacrificial layer should facilitate the recrystallization of the ultra thin layer into single crystal material. In addition, the etch rate of the sacrificial layer should be sufficiently higher than that the ultra thin layer so that the sacrificial layer can be selectively removed in the presence of the ultra thin layer after recrystallization. The latter condition is illustratively satisfied by doping the sacrificial layer and by not (intentionally) doping the ultra thin layer. In accordance with one embodiment of our invention, step (g) includes filling the trench with oxide to form a thick back oxide region. In accordance with another embodiment of our invention, step (g) includes depositing a thin oxide layer (the back oxide) in the trench and then filling the remainder of the trench with a polycrystalline region (the back gate). VRG MOSFETs fabricated in accordance with our invention are expected to be electrostatically scalable with precise dimensional control. In addition, they can be fully depleted. Novel UTB device designs are also described.
摘要翻译：制造VRG MOSFET的方法包括以下步骤：（a）形成VRG多层堆叠; （b）在堆叠中形成沟槽; （c）在沟槽的侧壁上沉积超薄的非晶半导体（α-半）层（沟槽的侧壁上的超薄层的部分将最终形成MOSFET的沟道或超薄体（UTB）））; （d）在超薄层上形成较厚的α半牺牲层; （e）使α-半层退火以将它们重结晶成单晶层; （f）选择性地除去再结晶的牺牲层; 和（g）执行附加步骤来完成VRG MOSFET。通常，牺牲层应促进超薄层再结晶成单晶材料。此外，牺牲层的蚀刻速率应该足够高于超薄层，使得可以在重结晶之后在超薄层的存在下选择性地去除牺牲层。通过掺杂牺牲层和不（有意地）掺杂超薄层来说明后一个条件。根据本发明的一个实施方案，步骤（g）包括用氧化物填充沟槽以形成厚的氧化物区域。根据本发明的另一个实施方案，步骤（g）包括在沟槽中沉积薄氧化物层（后氧化物），然后用多晶区域（后门）填充沟槽的其余部分。根据我们的发明制造的VRG MOSFET预计将具有精确的尺寸控制的静电可伸缩性。此外，它们可以完全耗尽。还描述了新的UTB设备设计。

6. 发明授权

US08120138B2 High-Z structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels 有权
标题翻译：混合光学和电子束平版印刷制作水平的高Z结构和方法
公开(公告)号：US08120138B2
公开(公告)日：2012-02-21
申请号：US12436189
申请日：2009-05-06
申请人： David Michael Fried , John Michael Hergenrother , Sharee Jane McNab , Michael J. Rooks , Anna Topol
发明人： David Michael Fried , John Michael Hergenrother , Sharee Jane McNab , Michael J. Rooks , Anna Topol
IPC分类号： H01L23/544
CPC分类号： G03F9/708 , B82Y10/00 , B82Y40/00 , G03F7/7045 , G03F9/7076 , G03F9/7088 , H01J37/3174 , H01L21/76283 , H01L21/823481 , H01L21/84 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A structure for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target. The structure including a first trench in a semiconductor substrate, the first trench extending from a top surface of the substrate into the substrate a first distance; an electron back-scattering layer in a bottom of the first trench; a dielectric capping layer in the trench over the back-scattering layer; and a second trench in the substrate, the second trench extending from the top surface of the substrate into the substrate a second distance, the second distance less than the first distance.
摘要翻译：用于将集成电路芯片的制造级别的第一组特征对准到电子束对准目标的结构。所述结构包括半导体衬底中的第一沟槽，所述第一沟槽从所述衬底的顶表面延伸到所述衬底中第一距离; 在第一沟槽的底部的电子背散射层; 背面散射层上的沟槽中的介电覆盖层; 以及所述衬底中的第二沟槽，所述第二沟槽从所述衬底的顶表面延伸到所述衬底中第二距离，所述第二距离小于所述第一距离。

7. 发明授权

US07550361B2 Trench structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels 失效
标题翻译：用于混合光学和电子束平版印刷制造水平的共同对准的沟槽结构和方法
公开(公告)号：US07550361B2
公开(公告)日：2009-06-23
申请号：US11618957
申请日：2007-01-02
申请人： David Michael Fried , John Michael Hergenrother , Sharee Jane McNab , Michael J. Rooks , Anna Topol
发明人： David Michael Fried , John Michael Hergenrother , Sharee Jane McNab , Michael J. Rooks , Anna Topol
IPC分类号： H01L21/76
CPC分类号： H01L21/76283 , B82Y10/00 , B82Y40/00 , G03F7/7045 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01J37/3174 , H01L21/3081 , H01L21/823481 , H01L21/84 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.
摘要翻译：一种用于将集成电路芯片的制造级别的第一组特征对准到形成在衬底中的电子束对准目标并使用电子束光刻形成第一组特征并用于对准第二组特征的方法将集成电路芯片的制造水平设置到形成在基板中的光学对准目标，并且使用光刻法形成第二组特征，所述光学对准目标本身与电子束对准目标对准。还有一种形成电子束对准靶的方法和结构。

8. 发明授权

US06635924B1 Ultra thin body vertical replacement gate MOSFET 有权
标题翻译：超薄体垂直替代栅极MOSFET
公开(公告)号：US06635924B1
公开(公告)日：2003-10-21
申请号：US10164202
申请日：2002-06-06
申请人： John Michael Hergenrother , Pranav Kalavade
发明人： John Michael Hergenrother , Pranav Kalavade
IPC分类号： H01L2184
CPC分类号： H01L21/823487
摘要： A method of fabricating a VRG MOSFET includes the steps of: (a) forming a VRG multilayer stack; (b) forming a trench in the stack; (c) depositing an ultra thin, amorphous semiconductor (&agr;-semic) layer on the sidewalls of the trench (portions of the ultra thin layer on the sidewalls of the trench will ultimately form the channel or ultra thin body (UTB) of the MOSFET); (d) forming a thicker, &agr;-semic sacrificial layer on the ultra thin layer; (e) annealing the &agr;-semic layers to recrystallize them into single crystal layers; (f) selectively removing the recrystallized sacrificial layer; and (g) performing additional steps to complete the VRG MOSFET. In general, the sacrificial layer should facilitate the recrystallization of the ultra thin layer into single crystal material. In addition, the etch rate of the sacrificial layer should be sufficiently higher than that the ultra thin layer so that the sacrificial layer can be selectively removed in the presence of the ultra thin layer after recrystallization. The latter condition is illustratively satisfied by doping the sacrificial layer and by not (intentionally) doping the ultra thin layer. In accordance with one embodiment of our invention, step (g) includes filling the trench with oxide to form a thick back oxide region. In accordance with another embodiment of our invention, step (g) includes depositing a thin oxide layer (the back oxide) in the trench and then filling the remainder of the trench with a polycrystalline region (the back gate). VRG MOSFETs fabricated in accordance with our invention are expected to be electrostatically scalable with precise dimensional control. In addition, they can be fully depleted. Novel UTB device designs are also described.
摘要翻译：制造VRG MOSFET的方法包括以下步骤：（a）形成VRG多层堆叠; （b）在堆叠中形成沟槽; （c）在沟槽的侧壁上沉积超薄的非晶半导体（α-半）层（沟槽的侧壁上的超薄层的部分将最终形成MOSFET的沟道或超薄体（UTB）））; （d）在超薄层上形成较厚的α半牺牲层; （e）使α-半层退火以将它们重结晶成单晶层; （f）选择性地除去再结晶的牺牲层; 和（g）执行附加步骤来完成VRG MOSFET。通常，牺牲层应促进超薄层再结晶成单晶材料。此外，牺牲层的蚀刻速率应该足够高于超薄层，使得可以在重结晶之后在超薄层的存在下选择性地去除牺牲层。通过掺杂牺牲层和不（有意地）掺杂超薄层来说明后一个条件。根据本发明的一个实施方案，步骤（g）包括用氧化物填充沟槽以形成厚的氧化物区域。根据本发明的另一个实施方案，步骤（g）包括在沟槽中沉积薄氧化物层（后氧化物），然后用多晶区域（后门）填充沟槽的其余部分。根据我们的发明制造的VRG MOSFET预计将具有精确的尺寸控制的静电可伸缩性。此外，它们可以完全耗尽。还描述了新的UTB设备设计。

9. 发明授权

US07696057B2 Method for co-alignment of mixed optical and electron beam lithographic fabrication levels 有权
标题翻译：混合光学和电子束光刻制造水平的共同对准方法
公开(公告)号：US07696057B2
公开(公告)日：2010-04-13
申请号：US11618974
申请日：2007-01-02
申请人： David Michael Fried , John Michael Hergenrother , Sharee Jane McNab , Michael J. Rooks , Anna Topol
发明人： David Michael Fried , John Michael Hergenrother , Sharee Jane McNab , Michael J. Rooks , Anna Topol
IPC分类号： H01L21/76
CPC分类号： G03F9/708 , B82Y10/00 , B82Y40/00 , G03F7/7045 , G03F9/7076 , G03F9/7088 , H01J37/3174 , H01L21/76283 , H01L21/823481 , H01L21/84 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target including a high atomic weight layer formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.
摘要翻译：一种用于将集成电路芯片的制造级别的第一组特征对准到包括形成在衬底中的高原子重量层并且使用电子束光刻形成第一组特征的电子束对准靶的方法，将集成电路芯片的相同制造级别的特征集合到形成在基板中的光学对准目标并且使用光刻形成第二组特征，所述光学对准目标本身与电子束对准目标对准。还有一种形成电子束对准靶的方法和结构。

10. 发明授权

US07687863B2 Selective incorporation of charge for transistor channels 失效
标题翻译：选择性地并入晶体管通道的电荷
公开(公告)号：US07687863B2
公开(公告)日：2010-03-30
申请号：US12121858
申请日：2008-05-16
申请人： John Michael Hergenrother , Zhibin Ren , Dinkar Virendra Singh , Jeffrey William Sleight
发明人： John Michael Hergenrother , Zhibin Ren , Dinkar Virendra Singh , Jeffrey William Sleight
IPC分类号： H01L23/62
CPC分类号： H01L21/28097 , H01L21/26506 , H01L21/28185 , H01L21/7624 , H01L29/4975 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： A device and method for selective placement of charge into a gate stack includes forming gate stacks including a gate dielectric adjacent to a transistor channel and a gate conductor and forming doped regions for transistor operation. A layer rich in a passivating element is deposited over the doped regions and the gate stack, and the layer rich the passivating element is removed from selected transistors. The layer rich in the passivating element is than annealed to drive-in the passivating element to increase a concentration of charge at or near transistor channels on transistors where the layer rich in the passivating element is present. The layer rich in the passivating element is removed.
摘要翻译：用于选择性地将电荷放置到栅极堆叠中的器件和方法包括形成包括邻近晶体管沟道和栅极导体的栅极电介质的栅极堆叠，并形成用于晶体管操作的掺杂区域。在掺杂区域和栅极叠层上沉积富含钝化元素的层，并且从所选择的晶体管去除富含钝化元件的层。富含钝化元件的层比退火以驱动钝化元件，以增加在存在钝化元件的层的晶体管上的晶体管沟槽处或附近的电荷浓度。去除富含钝化元素的层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式