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1. 发明授权

US06493077B1 Optical test probe for silicon optical bench 失效
标题翻译：硅光学台的光学测试探头
公开(公告)号：US06493077B1
公开(公告)日：2002-12-10
申请号：US09906358
申请日：2001-07-16
申请人： John D. Crow , Petar Pepeljugoski , Jeremy D. Schaub
发明人： John D. Crow , Petar Pepeljugoski , Jeremy D. Schaub
IPC分类号： G01N2100
CPC分类号： G01M11/04
摘要： An optical testing device includes an optical fiber having a first numerical aperture at a first end of the optical fiber. A positioning structure is attached to the optical fiber for moving the first end of the optical fiber to any portion of a substrate for testing an optical device. The optical device may be disposed at any location on the substrate and provides a light beam with an emission angle less than the first numerical aperture. A test head collects the light beam through the optical fiber to test the optical device. A method for positioning the optical fiber and testing the optical device is also disclosed.
摘要翻译：光学测试装置包括在光纤的第一端具有第一数值孔径的光纤。定位结构附接到光纤，用于将光纤的第一端移动到用于测试光学装置的基板的任何部分。光学器件可以设置在衬底上的任何位置处，并提供具有小于第一数值孔径的发射角的光束。测试头通过光纤收集光束以测试光学装置。还公开了一种用于定位光纤并测试光学装置的方法。

2. 发明授权

US08543768B2 Memory system including a spiral cache 有权
公开(公告)号：US08543768B2
公开(公告)日：2013-09-24
申请号：US12640360
申请日：2009-12-17
申请人： Fadi H. Gebara , Jeremy D. Schaub , Volker Strumpen
发明人： Fadi H. Gebara , Jeremy D. Schaub , Volker Strumpen
IPC分类号： G06F12/08
CPC分类号： G06F12/122 , G06F12/0855 , G06F12/0897 , G06F2212/271
摘要： An integrated memory system with a spiral cache responds to requests for values at a first external interface coupled to a particular storage location in the cache in a time period determined by the proximity of the requested values to the particular storage location. The cache supports multiple outstanding in-flight requests directed to the same address using an issue table that tracks multiple outstanding requests and control logic that applies the multiple requests to the same address in the order received by the cache memory. The cache also includes a backing store request table that tracks push-back write operations issued from the cache memory when the cache memory is full and a new value is provided from the external interface, and the control logic to prevent multiple copies of the same value from being loaded into the cache or a copy being loaded before a pending push-back has been completed.

3. 发明授权

US08111090B2 Voltage comparator having improved kickback and jitter characteristics 失效
标题翻译：电压比较器具有改进的反冲和抖动特性
公开(公告)号：US08111090B2
公开(公告)日：2012-02-07
申请号：US12358547
申请日：2009-01-23
申请人： Fadi H. Gebara , Jeremy D. Schaub
发明人： Fadi H. Gebara , Jeremy D. Schaub
IPC分类号： H03K5/22
CPC分类号： H03K3/35613
摘要： A comparator apparatus for comparing a first and a second voltage input includes a pair of cross-coupled inverter devices, including a pull up device and a pull down device, with output nodes defined between the pull up and pull down devices. A first switching device is coupled to the first input and a second switching device is coupled to the second input, with control circuitry configured for selective switching between a reset mode and a compare mode. In the reset mode, the first and second voltage inputs are coupled to respective output nodes so as to develop a differential signal thereacross, and the pull down devices in each inverter are isolated from the pull up devices. In the compare mode, the voltage inputs are isolated from the output nodes, and the pull down devices in each inverter are coupled to the pull up devices to latch the output nodes.
摘要翻译：用于比较第一和第二电压输入的比较器装置包括一对交叉耦合的逆变器装置，包括上拉装置和下拉装置，其中输出节点限定在上拉和下拉装置之间。第一开关器件耦合到第一输入端，第二开关器件耦合到第二输入端，控制电路被配置为在复位模式和比较模式之间进行选择性切换。在复位模式下，第一和第二电压输入耦合到相应的输出节点，以便在其上产生差分信号，并且每个逆变器中的下拉器件与上拉器件隔离。在比较模式下，电压输入与输出节点隔离，并且每个逆变器中的下拉器件耦合到上拉器件以锁存输出节点。

4. 发明授权

US07949482B2 Delay-based bias temperature instability recovery measurements for characterizing stress degradation and recovery 失效
标题翻译：基于延迟的偏置温度不稳定性恢复测量，用于表征应力退化和恢复
公开(公告)号：US07949482B2
公开(公告)日：2011-05-24
申请号：US12142294
申请日：2008-06-19
申请人： Fadi H. Gebara , Jerry D. Hayes , John P. Keane , Sani R. Nassif , Jeremy D. Schaub
发明人： Fadi H. Gebara , Jerry D. Hayes , John P. Keane , Sani R. Nassif , Jeremy D. Schaub
IPC分类号： G01L1/00
CPC分类号： G01R31/31725 , G01R31/2856
摘要： A method, test circuit and test system provide measurements to accurately characterize threshold voltage changes due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI). Both the bias temperature instability recovery profile and/or the bias temperature shifts due to rapid repetitions of stress application can be studied. In order to provide accurate measurements when stresses are applied at intervals on the order of tens of nanoseconds while avoiding unwanted recovery, and/or to achieve recovery profile sampling resolutions in the nanosecond range, multiple delay or ring oscillator frequency measurements are made using a delay line that is formed from delay elements that have delay variation substantially caused only by NBTI or PBTI effects. Devices in the delay elements are stressed, and then the delay line/ring oscillator is operated to measure a threshold voltage change for one or more measurement periods on the order of nanoseconds.
摘要翻译：一种方法，测试电路和测试系统提供测量以精确表征由于负偏压温度不稳定性（NBTI）和正偏压温度不稳定性（PBTI）引起的阈值电压变化。可以研究由于应力应用的快速重复引起的偏置温度不稳定性恢复曲线和/或偏置温度偏移。为了提供精确的测量，当应力以几十纳秒的间隔施加，同时避免不必要的恢复时，和/或实现纳秒范围内的恢复曲线采样分辨率，使用延迟进行多个延迟或环形振荡器频率测量由具有实质上仅由NBTI或PBTI效应引起的延迟变化的延迟元件形成的线。延迟元件中的器件受到应力，然后延迟线/环形振荡器被操作以测量一个或多个量级的纳秒的一个或多个测量周期的阈值电压变化。

5. 发明授权

US07915653B2 Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector 有权
标题翻译：制造高速CMOS兼容的绝缘体上的光电探测器的结构和方法
公开(公告)号：US07915653B2
公开(公告)日：2011-03-29
申请号：US11556755
申请日：2006-11-06
申请人： Jack O. Chu , Gabriel K. Dehlinger , Alfred Grill , Steven J. Koester , Qiqing Ouyang , Jeremy D. Schaub
发明人： Jack O. Chu , Gabriel K. Dehlinger , Alfred Grill , Steven J. Koester , Qiqing Ouyang , Jeremy D. Schaub
IPC分类号： H01L27/146
CPC分类号： H01L31/101
摘要： The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.
摘要翻译：本发明解决了与Si CMOS技术兼容的高速高效光电探测器的问题。该结构由薄的SOI衬底上的Ge吸收层组成，并且使用隔离区，交替的n型和p型接触以及低电阻表面电极。该器件通过利用掩埋绝缘层，通过利用Ge吸收层，利用薄吸收层和窄电极间隔的低电压操作以及兼容性来兼容通过利用掩埋绝缘层来隔离在下面的衬底中产生的载流子，在广谱上的高量子效率，通过其平面结构和使用IV族吸收材料的CMOS器件。用于制造光电检测器的方法使用在薄SOI或外延氧化物上的Ge的直接生长，以及随后的热退火以实现高质量的吸收层。该方法限制可用于相互扩散的Si的量，从而允许Ge层退火，而不会导致Ge层被下面的Si大量稀释。

6. 发明申请

US20100122033A1 MEMORY SYSTEM INCLUDING A SPIRAL CACHE 有权
标题翻译：包含螺旋式缓存的存储系统
公开(公告)号：US20100122033A1
公开(公告)日：2010-05-13
申请号：US12640360
申请日：2009-12-17
申请人： Fadi H. Gebara , Jeremy D. Schaub , Volker Strumpen
发明人： Fadi H. Gebara , Jeremy D. Schaub , Volker Strumpen
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/122 , G06F12/0855 , G06F12/0897 , G06F2212/271
摘要： An integrated memory system with a spiral cache responds to requests for values at a first external interface coupled to a particular storage location in the cache in a time period determined by the proximity of the requested values to the particular storage location. The cache supports multiple outstanding in-flight requests directed to the same address using an issue table that tracks multiple outstanding requests and control logic that applies the multiple requests to the same address in the order received by the cache memory. The cache also includes a backing store request table that tracks push-back write operations issued from the cache memory when the cache memory is full and a new value is provided from the external interface, and the control logic to prevent multiple copies of the same value from being loaded into the cache or a copy being loaded before a pending push-back has been completed.
摘要翻译：具有螺旋高速缓存的集成存储器系统在由所请求的值与特定存储位置的接近度确定的时间段内响应耦合到高速缓存中的特定存储位置的第一外部接口处的值的请求。高速缓存支持使用跟踪多个未完成请求的问题表和针对由高速缓冲存储器接收的顺序将多个请求应用于相同地址的控制逻辑的针对同一地址的多个未完成的飞行中请求。高速缓存还包括后备存储请求表，其在高速缓冲存储器已满并且从外部接口提供新值时跟踪从缓存存储器发出的推回写入操作，以及用于防止相同值的多个副本的控制逻辑在加载到缓存或正在加载的副本之前，等待推送已经完成。

7. 发明授权

US07286947B1 Method and apparatus for determining jitter and pulse width from clock signal comparisons 失效
标题翻译：用于从时钟信号比较确定抖动和脉冲宽度的方法和装置
公开(公告)号：US07286947B1
公开(公告)日：2007-10-23
申请号：US11279651
申请日：2006-04-13
申请人： Hayden C. Cranford, Jr. , Fadi H. Gebara , Jeremy D. Schaub
发明人： Hayden C. Cranford, Jr. , Fadi H. Gebara , Jeremy D. Schaub
IPC分类号： G06F19/00
CPC分类号： G01R31/31709 , G01R31/31725
摘要： A method and apparatus for determining jitter and pulse width from clock signal comparisons provides a low cost and production-integrable mechanism for measuring a clock signal with a reference clock, both of unknown frequency. The measured clock signal is sampled at transitions of a reference clock and the sampled values are collected in a histogram according to a folding of the samples around a timebase which is either swept to detect a minimum jitter for the folded data or is obtained from direct frequency analysis for the sample set. The histogram for the correct estimated period is statistically analyzed to yield the pulse width, which is the difference between the peaks of the probability density function and jitter, which corresponds to width of the density function peaks. Frequency drift is corrected by adjusting the timebase used to fold the data across the sample set.
摘要翻译：用于从时钟信号比较确定抖动和脉冲宽度的方法和装置提供了一种低成本和可生产可集成的机制，用于测量具有未知频率的参考时钟的时钟信号。测量的时钟信号在参考时钟的转变时被采样，并且采样值被收集在直方图中，根据时基的周围样本的折叠，该时基被扫描以检测折叠数据的最小抖动，或者从直接频率获得分析样本集。统计分析正确估计周期的直方图以产生脉冲宽度，其是概率密度函数和抖动的峰值之间的差异，其对应于密度函数峰值的宽度。通过调整用于将样本集合中的数据折叠的时基来校正频率漂移。

8. 发明申请

US20090319202A1 Delay-Based Bias Temperature Instability Recovery Measurements for Characterizing Stress Degradation and Recovery 失效
标题翻译：基于延迟的偏压温度不稳定性恢复测量，用于表征应力退化和恢复
公开(公告)号：US20090319202A1
公开(公告)日：2009-12-24
申请号：US12142294
申请日：2008-06-19
申请人： Fadi H. Gebara , Jerry D. Hayes , John P. Keane , Sani R. Nassif , Jeremy D. Schaub
发明人： Fadi H. Gebara , Jerry D. Hayes , John P. Keane , Sani R. Nassif , Jeremy D. Schaub
IPC分类号： G01L1/00
CPC分类号： G01R31/31725 , G01R31/2856
摘要： A method, test circuit and test system provide measurements to accurately characterize threshold voltage changes due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI). Both the bias temperature instability recovery profile and/or the bias temperature shifts due to rapid repetitions of stress application can be studied. In order to provide accurate measurements when stresses are applied at intervals on the order of tens of nanoseconds while avoiding unwanted recovery, and/or to achieve recovery profile sampling resolutions in the nanosecond range, multiple delay or ring oscillator frequency measurements are made using a delay line that is formed from delay elements that have delay variation substantially caused only by NBTI or PBTI effects. Devices in the delay elements are stressed, and then the delay line/ring oscillator is operated to measure a threshold voltage change for one or more measurement periods on the order of nanoseconds.
摘要翻译：一种方法，测试电路和测试系统提供测量以精确表征由于负偏压温度不稳定性（NBTI）和正偏压温度不稳定性（PBTI）引起的阈值电压变化。可以研究由于应力应用的快速重复引起的偏置温度不稳定性恢复曲线和/或偏置温度偏移。为了提供精确的测量，当应力以几十纳秒的间隔施加，同时避免不必要的恢复时，和/或实现纳秒范围内的恢复曲线采样分辨率，使用延迟进行多个延迟或环形振荡器频率测量由具有实质上仅由NBTI或PBTI效应引起的延迟变化的延迟元件形成的线。延迟元件中的器件受到应力，然后延迟线/环形振荡器被操作以测量一个或多个量级的纳秒的一个或多个测量周期的阈值电压变化。

9. 发明申请

US20080288197A1 Calibration of Multi-Metric Sensitive Delay Measurement Circuits 有权
标题翻译：多尺度敏感延迟测量电路的校准
公开(公告)号：US20080288197A1
公开(公告)日：2008-11-20
申请号：US11750475
申请日：2007-05-18
申请人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
发明人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
IPC分类号： G01R29/02
CPC分类号： G01R31/2874 , G01R31/3016
摘要： A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits.
摘要翻译：用于校准多度量敏感延迟测量电路的方法和系统提供减少延迟中的过程相关变化及其对电路度量的敏感性。用于延迟电路的处理角由至少一个延迟测量确定，对于该延迟测量，由于过程变化引起的延迟的变化被预先表征。延迟测量是在已知的温度，电源电压和延迟电路设计测量的任何其他环境度量的已知值进行的。然后从建立的过程角确定延迟与电路度量的系数，从而延迟测量的电路度量值的计算由于电路到电路和/或管芯到管芯的工艺变化而提高了精度和减小的变化的延迟电路。

10. 发明申请

US20080288196A1 Correction of Delay-Based Metric Measurements Using Delay Circuits Having Differing Metric Sensitivities 失效
标题翻译：使用具有不同公制灵敏度的延迟电路校正基于延迟的公制测量
公开(公告)号：US20080288196A1
公开(公告)日：2008-11-20
申请号：US11750385
申请日：2007-05-18
申请人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
发明人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
IPC分类号： G01R29/00 , G01R29/02
CPC分类号： G01R31/3016
摘要： Correction of delay-based metric measurements using delay circuits having differing metric sensitivities provides improved accuracy for environmental and other circuit metric measurements that used delay lines. A delay line measurement, which may be a one-shot measurement or a ring oscillator frequency measurement is performed either simultaneously or sequentially using at least two delay lines that have differing sensitivities to a particular metric under measurement. A correction circuit or algorithm uses the measured delays or ring oscillator frequencies and corrects at least one of the metric measurements determined from one of the delays or ring oscillator frequencies in conformity with the other delay or ring oscillator frequency. The delays may be inverter chains, with one chain having a higher sensitivity to supply voltage than the other delay chain, with the other delay chain having a higher sensitivity to temperature. Temperature results can then be corrected for supply voltage variation and vice-versa.
摘要翻译：使用具有不同的度量灵敏度的延迟电路对基于延迟的度量测量进行校正为使用延迟线的环境和其他电路量度测量提供了改进的精度。可以使用对测量的特定度量具有不同灵敏度的至少两个延迟线来同时或顺序地执行可以是单次测量或环形振荡器频率测量的延迟线测量。校正电路或算法使用测量的延迟或环形振荡器频率，并根据其他延迟或环形振荡器频率来校正从延迟或环形振荡器频率之一确定的度量测量中的至少一个。延迟可以是逆变器链，一个链对电源电压的敏感性高于另一个延迟链，另一个延迟链对温度具有较高的灵敏度。然后可以对电源电压变化校正温度结果，反之亦然。

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