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1. 发明授权

US08972703B2 Multithreaded processor architecture with operational latency hiding 有权
标题翻译：具有可操作延迟隐藏的多线程处理器架构
公开(公告)号：US08972703B2
公开(公告)日：2015-03-03
申请号：US13180724
申请日：2011-07-12
申请人： Matteo Frigo , Ahmed Gheith , Volker Strumpen
发明人： Matteo Frigo , Ahmed Gheith , Volker Strumpen
IPC分类号： G06F9/38 , G06F11/20
CPC分类号： G06F9/38 , G06F9/30043 , G06F9/3009 , G06F9/30112 , G06F9/3017 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/461 , G06F9/4843 , G06F11/2094
摘要： A method and processor architecture for achieving a high level of concurrency and latency hiding in an “infinite-thread processor architecture” with a limited number of hardware threads is disclosed. A preferred embodiment defines “fork” and “join” instructions for spawning new context-switched threads. Context switching is used to hide the latency of both memory-access operations (i.e., loads and stores) and arithmetic/logical operations. When an operation executing in a thread incurs a latency having the potential to delay the instruction pipeline, the latency is hidden by performing a context switch to a different thread. When the result of the operation becomes available, a context switch back to that thread is performed to allow the thread to continue.
摘要翻译：公开了一种用于在具有有限数量的硬件线程的“无限线程处理器架构”中实现高水平并发和延迟隐藏的方法和处理器架构。优选实施例定义了用于产生新的上下文切换线程的“fork”和“join”指令。上下文切换用于隐藏两个存储器访问操作（即，加载和存储）和算术/逻辑操作的延迟。当在线程中执行的操作引起具有延迟指令流水线的可能性的等待时间时，通过执行到不同线程的上下文切换来隐藏等待时间。当操作的结果变得可用时，执行回到该线程的上下文切换以允许线程继续。

2. 发明授权

US08364895B2 Global instructions for spiral cache management 有权
标题翻译：螺旋缓存管理的全局说明
公开(公告)号：US08364895B2
公开(公告)日：2013-01-29
申请号：US13419143
申请日：2012-03-13
申请人： Volker Strumpen
发明人： Volker Strumpen
IPC分类号： G06F12/00
CPC分类号： G06F12/0846 , G06F12/0811 , G06F2212/271
摘要： A method of operation of a pipelined cache memory supports global operations within the cache. The cache may be a spiral cache, with a move-to-front M2F network for moving values from a backing store to a front-most tile coupled to a processor or lower-order level of a memory hierarchy and a spiral push-back network for pushing out modified values to the backing-store. The cache controller manages application of global commands by propagating individual commands to the tiles. The global commands may provide zeroing, flushing and reconciling of the given tiles. Commands for interrupting and resuming interrupted global commands may be implemented, to reduce halting or slowing of processing while other global operations are in process. A line detector within each tile supports reconcile and flush operations, and a line patcher in the controller provides for initializing address ranges with no processor intervention.
摘要翻译：流水线缓存存储器的操作方法支持高速缓存内的全局操作。高速缓存可以是螺旋高速缓存，具有移动到前面的M2F网络，用于将值从后备存储移动到耦合到存储器层级的处理器或低级别级别的最前面的片和螺旋式推回网络将修改后的值推送到后台存储。高速缓存控制器通过将各个命令传播到瓦片来管理全局命令的应用。全局命令可以提供给定瓦片的归零，刷新和调和。可以实现用于中断和恢复中断的全局命令的命令，以在其他全局操作正在进行时减少处理的停止或减慢。每个瓦片内的线检测器支持协调和刷新操作，控制器中的线路修补器提供初始化地址范围，无需处理器干预。

3. 发明申请

US20120179872A1 GLOBAL INSTRUCTIONS FOR SPIRAL CACHE MANAGEMENT 有权
标题翻译：全球快递管理指南
公开(公告)号：US20120179872A1
公开(公告)日：2012-07-12
申请号：US13419143
申请日：2012-03-13
申请人： Volker Strumpen
发明人： Volker Strumpen
IPC分类号： G06F12/08
CPC分类号： G06F12/0846 , G06F12/0811 , G06F2212/271
摘要： A method of operation of a pipelined cache memory supports global operations within the cache. The cache may be a spiral cache, with a move-to-front M2F network for moving values from a backing store to a front-most tile coupled to a processor or lower-order level of a memory hierarchy and a spiral push-back network for pushing out modified values to the backing-store. The cache controller manages application of global commands by propagating individual commands to the tiles. The global commands may provide zeroing, flushing and reconciling of the given tiles. Commands for interrupting and resuming interrupted global commands may be implemented, to reduce halting or slowing of processing while other global operations are in process. A line detector within each tile supports reconcile and flush operations, and a line patcher in the controller provides for initializing address ranges with no processor intervention.
摘要翻译：流水线缓存存储器的操作方法支持高速缓存内的全局操作。高速缓存可以是螺旋高速缓存，具有移动到前面的M2F网络，用于将值从后备存储移动到耦合到存储器层级的处理器或低级别级别的最前面的片和螺旋式推回网络将修改后的值推送到后台存储。高速缓存控制器通过将各个命令传播到瓦片来管理全局命令的应用。全局命令可以提供给定瓦片的归零，刷新和调和。可以实现用于中断和恢复中断的全局命令的命令，以在其他全局操作正在进行时减少处理的停止或减慢。每个瓦片内的线检测器支持协调和刷新操作，控制器中的线路修补器提供初始化地址范围，无需处理器干预。

4. 发明授权

US08060699B2 Spiral cache memory and method of operating a spiral cache 失效
标题翻译：螺旋高速缓存和操作螺旋高速缓存的方法
公开(公告)号：US08060699B2
公开(公告)日：2011-11-15
申请号：US12270095
申请日：2008-11-13
申请人： Volker Strumpen , Matteo Frigo
发明人： Volker Strumpen , Matteo Frigo
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/123 , G06F12/0897 , G06F2212/271 , Y02D10/13
摘要： A memory provides reduction in access latency for frequently-accessed values by self-organizing to always move a requested value to a front-most central storage element of a spiral. The occupant of the central location is swapped backward, which continues backward through the spiral until an empty location is swapped-to, or the last displaced value is cast out of the last location in the spiral. The elements in the spiral may be cache memories or single elements. The resulting cache memory is self-organizing and for the one-dimensional implementation has a worst-case access time proportional to N, where N is the number of tiles in the spiral. A k-dimensional spiral cache has a worst-case access time proportional to N1/k. Further, a spiral cache system provides a basis for a non-inclusive system of cache memory, which reduces the amount of space and power consumed by a cache memory of a given size.
摘要翻译：存储器通过自组织来提供经常访问的值的访问等待时间，以将请求的值始终移动到螺旋的最前面的中央存储元件。中央位置的乘员被倒置，后退通过螺旋，直到空的位置被交换，或者最后的位移值被抛弃在螺旋中的最后位置。螺旋中的元件可以是高速缓冲存储器或单个元件。所得到的高速缓冲存储器是自组织的，并且由于一维实现具有与N成比例的最差情况访问时间，其中N是螺旋中的瓦片的数量。 k维螺旋高速缓存具有与N1 / k成比例的最差情况访问时间。此外，螺旋高速缓存系统为非包容性高速缓存存储器系统提供了基础，其减少了给定大小的高速缓冲存储器消耗的空间和功率量。

5. 发明授权

US08495431B2 Temperature-profiled device fingerprint generation and authentication from power-up states of static cells 失效
标题翻译：温度分析设备指纹生成和静态电池上电状态的认证
公开(公告)号：US08495431B2
公开(公告)日：2013-07-23
申请号：US13483252
申请日：2012-05-30
申请人： Fadi H. Gebara , Joonsoo Kim , Jeremy D. Schaub , Volker Strumpen
发明人： Fadi H. Gebara , Joonsoo Kim , Jeremy D. Schaub , Volker Strumpen
IPC分类号： G06F11/00
CPC分类号： G06F21/73 , G06F21/44 , G11C11/41 , G11C16/20 , G11C29/50 , G11C2029/4402 , G11C2029/5002
摘要： A method, system and computer program product for generating device fingerprints and authenticating devices uses initial states of internal storage cells after each of a number multiple power cycles for each of a number of device temperatures to generate a device fingerprint. The device fingerprint may include pairs of expected values for each of the internal storage cells and a corresponding probability that the storage cell will assume the expected value. Storage cells that have expected values varying over the multiple temperatures may be excluded from the fingerprint. A device is authenticated by a similarity algorithm that uses a match of the expected values from a known fingerprint with power-up values from an unknown device, weighting the comparisons by the probability for each cell to compute a similarity measure.
摘要翻译：用于产生设备指纹和认证设备的方法，系统和计算机程序产品在多个设备温度中的每一个的多个多个功率周期中的每一个之后使用内部存储单元的初始状态来生成设备指纹。设备指纹可以包括每个内部存储单元的预期值对以及存储单元将采用期望值的对应概率。可以从指纹中排除具有期望值在多个温度上变化的存储单元。相似性算法通过使用来自已知指纹的预期值与来自未知设备的上电值的匹配的相似性算法进行认证，对每个小区计算相似性度量的概率加权比较。

6. 发明申请

US20100122035A1 SPIRAL CACHE MEMORY AND METHOD OF OPERATING A SPIRAL CACHE 失效
标题翻译：螺旋式高速缓存存储器和操作螺旋缓存的方法
公开(公告)号：US20100122035A1
公开(公告)日：2010-05-13
申请号：US12270095
申请日：2008-11-13
申请人： Volker Strumpen , Matteo Frigo
发明人： Volker Strumpen , Matteo Frigo
IPC分类号： G06F12/08 , G06F12/00 , G06F1/04
CPC分类号： G06F12/123 , G06F12/0897 , G06F2212/271 , Y02D10/13
摘要： A spiral cache memory provides reduction in access latency for frequently-accessed values by self-organizing to always move a requested value to a front-most central storage element of the spiral. The occupant of the central location is swapped backward, which continues backward through the spiral until an empty location is swapped-to, or the last displaced value is cast out of the last location in the spiral. The elements in the spiral may be cache memories or single elements. The resulting cache memory is self-organizing and for the one-dimensional implementation has a worst-case access time proportional to N, where N is the number of tiles in the spiral. A k-dimensional spiral cache has a worst-case access time proportional to N1/k. Further, a spiral cache system provides a basis for a non-inclusive system of cache memory, which reduces the amount of space and power consumed by a cache memory of a given size.
摘要翻译：螺旋高速缓冲存储器通过自组织来提供经常访问的值的访问延迟的降低，以便始终将请求的值移动到螺旋的最前面的中央存储元件。中央位置的乘员被倒置，后退通过螺旋，直到空的位置被交换，或者最后的位移值被抛弃在螺旋中的最后位置。螺旋中的元件可以是高速缓冲存储器或单个元件。所得到的高速缓冲存储器是自组织的，并且由于一维实现具有与N成比例的最差情况访问时间，其中N是螺旋中的瓦片的数量。 k维螺旋高速缓存具有与N1 / k成比例的最差情况访问时间。此外，螺旋高速缓存系统为非包容性高速缓冲存储器系统提供了基础，其减少了给定大小的高速缓冲存储器消耗的空间和功率的量。

7. 发明申请

US20100122012A1 SYSTOLIC NETWORKS FOR A SPIRAL CACHE 有权
标题翻译： SYSTOLIC网络用于螺旋式缓存
公开(公告)号：US20100122012A1
公开(公告)日：2010-05-13
申请号：US12640348
申请日：2009-12-17
申请人： Fadi H. Gebara , Jeremy D. Schaub , Volker Strumpen
发明人： Fadi H. Gebara , Jeremy D. Schaub , Volker Strumpen
IPC分类号： G06F12/00 , G06F1/04 , G06F12/08
CPC分类号： G06F12/0893 , G06F1/04
摘要： Systolic networks within a tiled storage array provide for movement of requested values to a front-most tile, while making space for the requested values at the front-most tile by moving other values away. A first and second information pathway provide different linear pathways through the tiles. The movement of other values, requests for values and responses to requests is controlled according to a clocking logic that governs the movement on the first and second information pathways according to a systolic duty cycle. The first information pathway may be a move-to-front network of a spiral cache, crossing the spiral push-back network which forms the push-back network. The systolic duty cycle may be a three-phase duty cycle, or a two-phase duty cycle may be provided if the storage tiles support a push-back swap operation.
摘要翻译：平铺存储阵列内的收缩网络提供请求值移动到最前面的瓦片，同时通过将其他值移开，为最前面的瓦片上的请求值提供空间。第一和第二信息路径提供通过瓦片的不同线性路径。其他值的移动，对请求的值和响应的请求根据控制在第一和第二信息路径上的移动的时钟逻辑根据收缩期周期来控制。第一信息路径可以是螺旋形高速缓存的移动到前端网络，跨越形成推回网络的螺旋式推回网络。收缩期占空比可以是三相占空比，或者如果存储瓦片支持推回式交换操作，则可以提供两相占空比。

8. 发明申请

US20070260663A1 Cyclic segmented prefix circuits for mesh networks 有权
标题翻译：网状网络的循环分段前缀电路
公开(公告)号：US20070260663A1
公开(公告)日：2007-11-08
申请号：US11408099
申请日：2006-04-20
申请人： Matteo Frigo , Volker Strumpen
发明人： Matteo Frigo , Volker Strumpen
IPC分类号： G06F7/38
CPC分类号： G06F7/506 , G06F2207/5063
摘要： Parallel prefix circuits for computing a cyclic segmented prefix operation with a mesh topology are disclosed. In one embodiment of the present invention, the elements (prefix nodes) of the mesh are arranged in row-major order. Values are accumulated toward the center of the mesh and partial results are propagated outward from the center of the mesh to complete the cyclic segmented prefix operation. This embodiment has been shown to be time-optimal. In another embodiment of the present invention, the prefix nodes are arranged such that the prefix node corresponding to the last element in the array is located at the center of the array. This alternative embodiment is not only time-optimal when accounting for wire-lengths (and therefore propagation delays), but it is also asympotically optimal in terms of minimizing the number of segmented prefix operators.
摘要翻译：公开了用于计算具有网格拓扑的循环分段前缀操作的并行前缀电路。在本发明的一个实施例中，网格的元素（前缀节点）按行主顺序排列。值向网格的中心累积，部分结果从网格的中心向外传播，以完成循环分段前缀操作。该实施例已被证明是时间最佳的。在本发明的另一个实施例中，前缀节点被布置成使得与阵列中的最后一个元素相对应的前缀节点位于阵列的中心。这种替代实施例不仅在考虑线长度（因此传播延迟）时是时间最优的，而且在最小化分段前缀运算符的数量方面也是最优的。

9. 发明授权

US6161219A System and method for providing checkpointing with precompile directives and supporting software to produce checkpoints, independent of environment constraints 失效
标题翻译：提供检查点与预编译指令的系统和方法，并支持软件生成检查点，而不受环境限制
公开(公告)号：US6161219A
公开(公告)日：2000-12-12
申请号：US888013
申请日：1997-07-03
申请人： Balkrishna Ramkumar , Volker Strumpen
发明人： Balkrishna Ramkumar , Volker Strumpen
IPC分类号： G06F11/36 , G06F9/44
CPC分类号： G06F11/1438
摘要： A method for portable checkpointing comprising the steps of: pre-compiling an input source code; and outputting an associated output source code which includes support for portable checkpointing. The portability of the checkpoints allows migration between systems with different hardware, software, and operating systems.The portable checkpoints are stored in a Universal Code Format (UCF) and are selectively activated at the next potential checkpoint marker after a MinTBC (Minimum Time Between Checkpoints) timer expires.
摘要翻译：一种用于便携式检查点的方法，包括以下步骤：预编译输入源代码; 并输出包括支持便携式检查点的关联的输出源代码。检查点的可移植性允许在具有不同硬件，软件和操作系统的系统之间进行迁移。便携式检查点以通用代码格式（UCF）存储，并且在MinTBC（检查点之间的最小时间）定时器到期之后，在下一个潜在检查点标记处有选择地激活。

10. 发明申请

US20140075159A1 Multithreaded processor architecture with operational latency hiding 有权
标题翻译：具有可操作延迟隐藏的多线程处理器架构
公开(公告)号：US20140075159A1
公开(公告)日：2014-03-13
申请号：US13180724
申请日：2011-07-12
申请人： Matteo Frigo , Ahmed Gheith , Volker Strumpen
发明人： Matteo Frigo , Ahmed Gheith , Volker Strumpen
IPC分类号： G06F9/38
CPC分类号： G06F9/38 , G06F9/30043 , G06F9/3009 , G06F9/30112 , G06F9/3017 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/461 , G06F9/4843 , G06F11/2094
摘要： A method and processor architecture for achieving a high level of concurrency and latency hiding in an “infinite-thread processor architecture” with a limited number of hardware threads is disclosed. A preferred embodiment defines “fork” and “join” instructions for spawning new context-switched threads. Context switching is used to hide the latency of both memory-access operations (i.e., loads and stores) and arithmetic/logical operations. When an operation executing in a thread incurs a latency having the potential to delay the instruction pipeline, the latency is hidden by performing a context switch to a different thread. When the result of the operation becomes available, a context switch back to that thread is performed to allow the thread to continue.
摘要翻译：公开了一种用于在具有有限数量的硬件线程的“无限线程处理器架构”中实现高水平并发和延迟隐藏的方法和处理器架构。优选实施例定义了用于产生新的上下文切换线程的“fork”和“join”指令。上下文切换用于隐藏两个存储器访问操作（即，加载和存储）和算术/逻辑操作的延迟。当在线程中执行的操作引起具有延迟指令流水线的可能性的等待时间时，通过执行到不同线程的上下文切换来隐藏等待时间。当操作的结果变得可用时，执行回到该线程的上下文切换以允许线程继续。

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