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1. 发明授权

US08551555B2 Biocompatible coatings for medical devices 有权
标题翻译：用于医疗器械的生物相容性涂层
公开(公告)号：US08551555B2
公开(公告)日：2013-10-08
申请号：US11964428
申请日：2007-12-26
申请人： John Burghard , Carmen Campbell , Todd R. Younkin , Markus Kuhn , David Shykind , Jose Maiz
发明人： John Burghard , Carmen Campbell , Todd R. Younkin , Markus Kuhn , David Shykind , Jose Maiz
IPC分类号： A61L33/00
CPC分类号： B82Y30/00 , A61L27/34 , A61L31/10 , A61L2420/02 , B05D1/185 , B05D1/22 , B05D3/044 , B05D3/142 , B05D7/52 , B82Y40/00 , C08L89/04
摘要： Biocompatible coatings for implantable medical devices are disclosed. Embodiments of the invention provide methods for coating an object with a biocompatible coating wherein the device is suspended using a flowing gas during the coating process. Embodiments of the invention provide tropoelastin coatings and methods of creating tropoelastin coatings for implantable medical devices. Optionally, the biocompatible coating can be a drug eluting coating.
摘要翻译：公开了用于可植入医疗装置的生物相容性涂层。本发明的实施例提供了用生物相容性涂层涂覆物体的方法，其中在涂覆过程中使用流动的气体悬挂该装置。本发明的实施方案提供托普拉斯他汀涂层和用于可植入医疗装置的创伤弹力蛋白涂层的方法。任选地，生物相容性涂层可以是药物洗脱涂层。

2. 发明申请

US20090169714A1 BIOCOMPATIBLE COATINGS FOR MEDICAL DEVICES 有权
标题翻译：用于医疗器械的生物涂料
公开(公告)号：US20090169714A1
公开(公告)日：2009-07-02
申请号：US11964428
申请日：2007-12-26
申请人： John Burghard , Carmen Campbell , Todd R. Younkin , Markus Kuhn , David Shykind , Jose Maiz
发明人： John Burghard , Carmen Campbell , Todd R. Younkin , Markus Kuhn , David Shykind , Jose Maiz
IPC分类号： A61L33/12
CPC分类号： B82Y30/00 , A61L27/34 , A61L31/10 , A61L2420/02 , B05D1/185 , B05D1/22 , B05D3/044 , B05D3/142 , B05D7/52 , B82Y40/00 , C08L89/04
摘要： Biocompatible coatings for implantable medical devices are disclosed. Embodiments of the invention provide methods for coating an object with a biocompatible coating wherein the device is suspended using a flowing gas during the coating process. Embodiments of the invention provide tropoelastin coatings and methods of creating tropoelastin coatings for implantable medical devices. Optionally, the biocompatible coating can be a drug eluting coating.
摘要翻译：公开了用于可植入医疗装置的生物相容性涂层。本发明的实施例提供了用生物相容性涂层涂覆物体的方法，其中在涂覆过程中使用流动的气体悬挂该装置。本发明的实施方案提供托普拉斯他汀涂层和用于可植入医疗装置的创伤弹力蛋白涂层的方法。任选地，生物相容性涂层可以是药物洗脱涂层。

3. 发明申请

US20090130293A1 BIOCOMPATIBLE COATINGS FOR MEDICAL DEVICES 审中-公开
标题翻译：用于医疗器械的生物涂料
公开(公告)号：US20090130293A1
公开(公告)日：2009-05-21
申请号：US11941834
申请日：2007-11-16
申请人： David Shykind , Todd Younkin , John Burghard , Markus Kuhn , Carmen Campbell , Jose Maiz
发明人： David Shykind , Todd Younkin , John Burghard , Markus Kuhn , Carmen Campbell , Jose Maiz
IPC分类号： A61L33/12
CPC分类号： A61L31/10 , C08L89/06
摘要： Biocompatible coatings for implantable medical devices are disclosed. Embodiments of the invention provide plasma etch processes, surface silanization processes, and protein coating processes. Embodiments of the invention provide tropoelastin coatings and methods of creating tropoelastin coatings for implantable medical devices. Optionally, the biocompatible coating can be a drug eluting coating.
摘要翻译：公开了用于可植入医疗装置的生物相容性涂层。本发明的实施方案提供等离子体蚀刻工艺，表面硅烷化方法和蛋白质涂覆方法。本发明的实施方案提供托普拉斯他汀涂层和用于可植入医疗装置的创伤弹力蛋白涂层的方法。任选地，生物相容性涂层可以是药物洗脱涂层。

4. 发明申请

US20080242012A1 High quality silicon oxynitride transition layer for high-k/metal gate transistors 审中-公开
标题翻译：高k /金属栅晶体管的高品质氮氧化硅过渡层
公开(公告)号：US20080242012A1
公开(公告)日：2008-10-02
申请号：US11729188
申请日：2007-03-28
申请人： Sangwoo Pae , Jose Maiz , Gilbert Dewey , Matthew V. Metz , Markus Kuhn , Mark Doczy , Jack Kavalieros
发明人： Sangwoo Pae , Jose Maiz , Gilbert Dewey , Matthew V. Metz , Markus Kuhn , Mark Doczy , Jack Kavalieros
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/517 , H01L21/28079 , H01L21/28194 , H01L29/495 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A method for fabricating a high quality silicon oxynitride layer for a high-k/metal gate transistor comprises depositing a high-k dielectric layer on a substrate, depositing a barrier layer on the high-k dielectric layer, wherein the barrier layer includes at least one of nitrogen or oxygen, depositing a capping layer on the barrier layer, and annealing the substrate at a temperature that causes at least a portion of the nitrogen and/or oxygen in the barrier layer to diffuse to an interface between the high-k dielectric layer and the substrate. The diffused nitrogen or oxygen forms a high-quality silicon oxynitride layer at the interface. The high-k dielectric layer, the barrier layer, and the capping layer may then be etched to form a gate stack for use in a high-k/metal gate transistor. The capping layer may be replaced with a metal gate electrode using a replacement metal gate process.
摘要翻译：制造用于高k /金属栅极晶体管的高质量氮氧化硅层的方法包括在衬底上沉积高k电介质层，在高k电介质层上沉积阻挡层，其中阻挡层至少包括氮气或氧气中的一种，在阻挡层上沉积覆盖层，并且在使阻挡层中的氮和/或氧的至少一部分扩散到高k电介质层和基底。扩散的氮或氧在界面处形成高质量的氮氧化硅层。然后可以蚀刻高k电介质层，阻挡层和覆盖层以形成用于高k /金属栅极晶体管的栅极堆叠。使用替代金属浇口工艺可以用金属栅电极代替覆盖层。

5. 发明申请

US20070168836A1 Repair bits for a low voltage cache 有权
标题翻译：修复低电压缓存的位
公开(公告)号：US20070168836A1
公开(公告)日：2007-07-19
申请号：US11322988
申请日：2005-12-30
申请人： Morgan Dempsey , Jose Maiz
发明人： Morgan Dempsey , Jose Maiz
IPC分类号： G11C29/00
CPC分类号： G11C29/808 , G11C15/00
摘要： A method and apparatus for repairing cache memories/arrays is described herein. A cache includes a plurality of lines and logically viewable in columns. A repair cache coupled to the cache includes a repair bit mapped to each logically viewable column. A repair module determines a bad bit to be repaired within a column based on any individual or combination of factors, such as the number of errors per line of the cache, the number of errors correctable per line of the cache due to error correction code (ECC), the failure rate of bits, or other considerations. The bad bit is transparently repaired by the repair bit mapped to the column including the bad bit, upon an access to a cache line including the bad bit.
摘要翻译：本文描述了用于修复高速缓冲存储器/阵列的方法和装置。缓存包括多个行，并且可以在列中逻辑地查看。耦合到高速缓存的修复缓存包括映射到每个逻辑可见列的修复位。修复模块基于任何个体或因素组合来确定在列内修复的坏位，例如每个高速缓存行的错误数量，由于错误校正码每行高速缓存可纠错的数量（ ECC），位的故障率或其他考虑。在访问包括坏位的高速缓存行时，坏位被映射到包括坏位的列的修复位透明地修复。

6. 发明申请

US20060043579A1 Transistor performance enhancement using engineered strains 失效
标题翻译：使用工程菌株的晶体管性能提升
公开(公告)号：US20060043579A1
公开(公告)日：2006-03-02
申请号：US10930247
申请日：2004-08-31
申请人： Jun He , Zhiyong Ma , Jose Maiz , Mark Bohr , Martin Giles , Guanghai Xu
发明人： Jun He , Zhiyong Ma , Jose Maiz , Mark Bohr , Martin Giles , Guanghai Xu
IPC分类号： H01L23/34
CPC分类号： H01L29/7842 , H01L21/823807 , H01L23/42 , H01L2224/16 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/01087 , H01L2924/01322 , H01L2924/10253 , H01L2924/15311 , H01L2924/16152 , H01L2924/00 , H01L2224/0401
摘要： A semiconductor substrate having metal oxide semiconductor (MOS) devices, such as an integrated circuit die, is mechanically coupled to a stress structure to apply a stress that improves the performance of at least a portion of the MOS devices on the die.
摘要翻译：具有诸如集成电路管芯的金属氧化物半导体（MOS）器件的半导体衬底被机械耦合到应力结构，以施加提高模具上的至少一部分MOS器件的性能的应力。

7. 发明授权

US06919637B2 Interconnect structure for an integrated circuit and method of fabrication 失效
标题翻译：集成电路的互连结构和制造方法
公开(公告)号：US06919637B2
公开(公告)日：2005-07-19
申请号：US10261543
申请日：2002-09-30
申请人： Jun He , Jose Maiz , Hyun-Mog Park
发明人： Jun He , Jose Maiz , Hyun-Mog Park
IPC分类号： H01L23/522 , H01L23/532 , H01L29/40
CPC分类号： H01L23/5222 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure for an integrated circuit having several levels of conductors is disclosed. Dielectric pillars for mechanical support are formed between conductors in adjacent layers at locations that do not have vias. The pillars are particularly useful with low-k ILD or air dielectric.
摘要翻译：公开了一种具有多级导体的集成电路的互连结构。在不具有通孔的位置处，在相邻层中的导体之间形成用于机械支撑的介电柱。支柱对于低k ILD或空气电介质特别有用。

8. 发明申请

US20080105925A1 Process charging and electrostatic damage protection in silicon-on-insulator technology 失效
标题翻译：硅绝缘体技术中的工艺充电和静电损伤保护
公开(公告)号：US20080105925A1
公开(公告)日：2008-05-08
申请号：US11593706
申请日：2006-11-03
申请人： Sangwoo Pae , Jose Maiz
发明人： Sangwoo Pae , Jose Maiz
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/1207
摘要： A SOI device features a conductive pathway between active SOI devices and a bulk SOI substrate. The conductive pathway provides the ability to sink plasma-induced process charges into a bulk substrate in the event of process charging, such as interlayer dielectric deposition in a plasma environment, plasma etch deposition, or other fabrication provides. A method is also disclosed which includes dissipating electrostatic and process charges from a top of a SOI device to the bottom of the device. The top and bottom of the SOI device may characterize a region of active devices and a semiconductor method respectively. The method further includes a single masking step to create seed regions for an epitaxial-silicon pathway.
摘要翻译： SOI器件在有源SOI器件和体SOI衬底之间具有导电通路。导电通路提供了在处理充电的情况下（例如等离子体环境中的层间电介质沉积，等离子体蚀刻沉积或其它制造提供）将等离子体诱导的工艺电荷吸收到体衬底中的能力。还公开了一种方法，其包括将静电和处理电荷从SOI器件的顶部消散到器件的底部。 SOI器件的顶部和底部可分别表征有源器件的区域和半导体方法。该方法还包括单个掩模步骤以产生外延硅通路的种子区域。

9. 发明申请

US20080076216A1 Method to fabricate high-k/metal gate transistors using a double capping layer process 审中-公开
标题翻译：使用双层覆盖层工艺制造高k /金属栅极晶体管的方法
公开(公告)号：US20080076216A1
公开(公告)日：2008-03-27
申请号：US11527263
申请日：2006-09-25
申请人： Sangwoo Pae , Jose Maiz , Chetan Prasad
发明人： Sangwoo Pae , Jose Maiz , Chetan Prasad
IPC分类号： H01L21/336
CPC分类号： H01L29/517 , H01L21/28088 , H01L29/4966 , H01L29/66545
摘要： Semiconductor devices and methods to fabricate thereof are described. For an embodiment, a semiconductor device features a double capping layer. The double capping layer may include a first-capping layer and a second-capping layer. The first-capping layer protects a high-k gate dielectric film during a replacement gate process and the second-capping layer protects the first-capping layer during metal deposition. For other embodiments, the first-capping layer prevents the interaction between a polysilicon layer and a high-k gate dielectric film to prevent Vt-pinning of fabricated transistors.
摘要翻译：对半导体装置及其制造方法进行说明。对于一个实施例，半导体器件具有双重覆盖层。双层覆盖层可以包括第一覆盖层和第二覆盖层。第一盖层在替代栅极工艺期间保护高k栅极电介质膜，并且第二覆盖层在金属沉积期间保护第一覆盖层。对于其他实施例，第一覆盖层防止多晶硅层和高k栅极电介质膜之间的相互作用以防止制造的晶体管的栅极。

10. 发明申请

US20060261437A1 Methods of forming electromigration and thermal gradient based fuse structures 有权
公开(公告)号：US20060261437A1
公开(公告)日：2006-11-23
申请号：US11133835
申请日：2005-05-20
申请人： Jose Maiz , Jun He , Mark Bohr
发明人： Jose Maiz , Jun He , Mark Bohr
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a metallic fuse structure by forming at least one via on a first interconnect structure, lining the at least one via with a barrier layer, and then forming a second interconnect structure on the at least one via.

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