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1. 发明授权

US07562264B2 Fault tolerant soft error detection for storage subsystems 有权
标题翻译：存储子系统的容错软错误检测
公开(公告)号：US07562264B2
公开(公告)日：2009-07-14
申请号：US11516909
申请日：2006-09-06
申请人： Matthew B. Tangvald , Morgan Dempsey , Scott T. Peiffer
发明人： Matthew B. Tangvald , Morgan Dempsey , Scott T. Peiffer
IPC分类号： G06F11/00
CPC分类号： G06F11/1612 , G06F11/1076 , G06F11/1616 , G06F11/2017 , G06F11/2089 , G06F2211/1009 , G06F2211/1059
摘要： A method and apparatus for detecting soft errors in a storage subsystem is provided. Write data generated for a write operation in a first controller is concurrently generated in a second controller and written to a storage device by the first controller. Soft errors are detected by comparing the two sets of write data by comparing respective checksums or the write data read back from the storage device by the second controller.
摘要翻译：提供一种用于检测存储子系统中的软错误的方法和装置。在第一控制器中为写入操作生成的写入数据在第二控制器中同时生成并由第一控制器写入存储设备。通过比较两组写入数据，通过比较由第二控制器从存储设备读回的各个校验和或写入数据来检测软错误。

2. 发明申请

US20070165477A1 Method and apparatus to adjust voltage for storage location reliability 有权
标题翻译：调整电压的方法和装置，用于存储位置的可靠性
公开(公告)号：US20070165477A1
公开(公告)日：2007-07-19
申请号：US11322518
申请日：2005-12-30
申请人： Morgan Dempsey
发明人： Morgan Dempsey
IPC分类号： G11C8/00
CPC分类号： G11C29/44 , G11C29/021 , G11C29/028 , G11C2029/0401 , G11C2029/5002
摘要： According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storage locations for the cache, a detector to measure a thermal environment of the processor, and circuitry to raise an operating voltage of the processor if the actual number of unreliable storage locations exceeds the acceptable number of unreliable storage locations, and if the thermal environment is acceptable.
摘要翻译：根据本发明的实施例，诸如处理器的集成电路包括计数器，用于对处理器高速缓存中的不可靠存储位置的实际数量进行计数，至少一个寄存器，用于存储用于高速缓存的可接受数量的不可靠存储位置，检测器，以测量处理器的热环境，以及如果实际数量不可靠的存储位置超过可接受数量的不可靠存储位置，以及如果热环境是可接受的，则提高处理器的工作电压的电路。

3. 发明申请

US20090096664A1 Method, Apparatus and Computer Program Product for Providing Stabilization During a Tracking Operation 审中-公开
标题翻译：方法，装置和计算机程序产品，用于在跟踪操作期间提供稳定
公开(公告)号：US20090096664A1
公开(公告)日：2009-04-16
申请号：US11870003
申请日：2007-10-10
申请人： Carlton William Carroll , Daniel Morgan Dempsey
发明人： Carlton William Carroll , Daniel Morgan Dempsey
IPC分类号： G01S13/00
CPC分类号： G01S7/4026 , G01S13/66 , G01S2007/403 , G01S2007/4034 , G01S2007/4091
摘要： An apparatus for providing stabilization during a tracking operation may include a processing element configured to define an inertial pointing vector relative to a point of interest, receive tracking information related to the point of interest, and determine compensation of the inertial pointing vector based on the received tracking information and motion of a platform conducting the tracking operation.
摘要翻译：用于在跟踪操作期间提供稳定的装置可以包括处理元件，其被配置为相对于兴趣点定义惯性指向矢量，接收与兴趣点相关的跟踪信息，以及基于接收到的惯性指向矢量来确定补偿跟踪跟踪操作的平台的跟踪信息和运动。

4. 发明申请

US20080126885A1 Fault tolerant soft error detection for storage subsystems 有权
标题翻译：存储子系统的容错软错误检测
公开(公告)号：US20080126885A1
公开(公告)日：2008-05-29
申请号：US11516909
申请日：2006-09-06
申请人： Matthew B. Tangvald , Morgan Dempsey , Scott T. Peiffer
发明人： Matthew B. Tangvald , Morgan Dempsey , Scott T. Peiffer
IPC分类号： G06F11/00
CPC分类号： G06F11/1612 , G06F11/1076 , G06F11/1616 , G06F11/2017 , G06F11/2089 , G06F2211/1009 , G06F2211/1059
摘要： A method and apparatus for detecting soft errors in a storage subsystem is provided. Write data generated for a write operation in a first controller is concurrently generated in a second controller and written to a storage device by the first controller. Soft errors are detected by comparing the two sets of write data by comparing respective checksums or the write data read back from the storage device by the second controller.
摘要翻译：提供一种用于检测存储子系统中的软错误的方法和装置。在第一控制器中为写入操作生成的写入数据在第二控制器中同时生成并由第一控制器写入存储设备。通过比较两组写入数据，通过比较由第二控制器从存储设备读回的各个校验和或写入数据来检测软错误。

5. 发明申请

US20070168836A1 Repair bits for a low voltage cache 有权
标题翻译：修复低电压缓存的位
公开(公告)号：US20070168836A1
公开(公告)日：2007-07-19
申请号：US11322988
申请日：2005-12-30
申请人： Morgan Dempsey , Jose Maiz
发明人： Morgan Dempsey , Jose Maiz
IPC分类号： G11C29/00
CPC分类号： G11C29/808 , G11C15/00
摘要： A method and apparatus for repairing cache memories/arrays is described herein. A cache includes a plurality of lines and logically viewable in columns. A repair cache coupled to the cache includes a repair bit mapped to each logically viewable column. A repair module determines a bad bit to be repaired within a column based on any individual or combination of factors, such as the number of errors per line of the cache, the number of errors correctable per line of the cache due to error correction code (ECC), the failure rate of bits, or other considerations. The bad bit is transparently repaired by the repair bit mapped to the column including the bad bit, upon an access to a cache line including the bad bit.
摘要翻译：本文描述了用于修复高速缓冲存储器/阵列的方法和装置。缓存包括多个行，并且可以在列中逻辑地查看。耦合到高速缓存的修复缓存包括映射到每个逻辑可见列的修复位。修复模块基于任何个体或因素组合来确定在列内修复的坏位，例如每个高速缓存行的错误数量，由于错误校正码每行高速缓存可纠错的数量（ ECC），位的故障率或其他考虑。在访问包括坏位的高速缓存行时，坏位被映射到包括坏位的列的修复位透明地修复。

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