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1. 发明授权

US07135398B2 Reliable low-k interconnect structure with hybrid dielectric 有权
标题翻译：具有混合电介质的可靠的低k互连结构
公开(公告)号：US07135398B2
公开(公告)日：2006-11-14
申请号：US10901868
申请日：2004-07-29
申请人： John A. Fitzsimmons , Stephen E. Greco , Jia Lee , Stephen M. Gates , Terry Spooner , Matthew S. Angyal , Habib Hichri , Theordorus E. Standaert , Glenn A. Biery
发明人： John A. Fitzsimmons , Stephen E. Greco , Jia Lee , Stephen M. Gates , Terry Spooner , Matthew S. Angyal , Habib Hichri , Theordorus E. Standaert , Glenn A. Biery
IPC分类号： H01L21/4763
CPC分类号： H01L21/76832 , H01L21/76801 , H01L21/76807 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.
摘要翻译：公开了一种具有混合电介质的高级后端（BEOL）互连结构。用于通孔电平的层间电介质（ILD）优选地不同于线路电平的ILD。在优选实施例中，通孔级ILD由低k SiCOH材料形成，并且线级ILD由低k聚合物热固性材料形成。

2. 发明授权

US06917108B2 Reliable low-k interconnect structure with hybrid dielectric 有权
公开(公告)号：US06917108B2
公开(公告)日：2005-07-12
申请号：US10294139
申请日：2002-11-14
申请人： John A. Fitzsimmons , Stephen E. Greco , Jia Lee , Stephen M. Gates , Terry Spooner , Matthew S. Angyal , Habib Hichri , Theordorus E. Standaert , Glenn A. Biery
发明人： John A. Fitzsimmons , Stephen E. Greco , Jia Lee , Stephen M. Gates , Terry Spooner , Matthew S. Angyal , Habib Hichri , Theordorus E. Standaert , Glenn A. Biery
IPC分类号： H01L21/768 , H01L23/532 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76832 , H01L21/76801 , H01L21/76807 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.

3. 发明授权

US06939797B2 Advanced BEOL interconnect structures with low-k PE CVD cap layer and method thereof 失效
标题翻译：具有低k PE CVD覆盖层的高级BEOL互连结构及其方法
公开(公告)号：US06939797B2
公开(公告)日：2005-09-06
申请号：US10706773
申请日：2003-11-12
申请人： Edward Barth , John A. Fitzsimmons , Stephen M. Gates , Thomas H. Ivers , Sarah L. Lane , Jia Lee , Ann McDonald , Vincent McGahay , Darryl D. Restaino
发明人： Edward Barth , John A. Fitzsimmons , Stephen M. Gates , Thomas H. Ivers , Sarah L. Lane , Jia Lee , Ann McDonald , Vincent McGahay , Darryl D. Restaino
IPC分类号： H01L21/311 , H01L21/314 , H01L21/316 , H01L21/318 , H01L21/768 , H01L23/532 , H01L21/4763 , H01L21/44 , H01L21/461
CPC分类号： H01L21/76834 , H01L21/31144 , H01L21/3148 , H01L21/31612 , H01L21/31633 , H01L21/3185 , H01L21/76801 , H01L21/76807 , H01L21/76832 , H01L21/76838 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.
摘要翻译：公开了一种先进的后端（BEOL）金属化结构。该结构包括具有低介电常数（低-k）的扩散阻挡层或覆盖层，其中通过等离子体增强化学气相沉积（PE CVD）工艺，覆盖层由氮化硅形成。金属化结构还包括由具有小于约4的介电常数的含碳电介质材料形成的层间电介质（ILD），以及优选由氮化硅或碳化硅形成的ILD上的连续硬掩模层。还公开了一种用于形成BEOL金属化结构的方法。该方法包括预清洁或预激活步骤，以改善盖层与下面的铜导体的粘合性。预清洁或预活化步骤包括将铜表面暴露于包括氢，氨，氮和/或惰性气体的还原等离子体。

4. 发明授权

US06737747B2 Advanced BEOL interconnect structures with low-k PE CVD cap layer and method thereof 有权
公开(公告)号：US06737747B2
公开(公告)日：2004-05-18
申请号：US10047965
申请日：2002-01-15
申请人： Edward Barth , John A. Fitzsimmons , Stephen M. Gates , Thomas H. Ivers , Sarah L. Lane , Jia Lee , Ann McDonald , Vincent McGahay , Darryl D. Restaino
发明人： Edward Barth , John A. Fitzsimmons , Stephen M. Gates , Thomas H. Ivers , Sarah L. Lane , Jia Lee , Ann McDonald , Vincent McGahay , Darryl D. Restaino
IPC分类号： H01L2348
CPC分类号： H01L21/76834 , H01L21/31144 , H01L21/3148 , H01L21/31612 , H01L21/31633 , H01L21/3185 , H01L21/76801 , H01L21/76807 , H01L21/76832 , H01L21/76838 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.

5. 发明授权

US07517790B2 Method and structure to enhance temperature/humidity/bias performance of semiconductor devices by surface modification 失效
标题翻译：通过表面改性来提高半导体器件的温度/湿度/偏置性能的方法和结构
公开(公告)号：US07517790B2
公开(公告)日：2009-04-14
申请号：US10906189
申请日：2005-02-08
申请人： John A. Fitzsimmons , Stephen M. Gates , Michael W. Lane , Eric G. Liniger
发明人： John A. Fitzsimmons , Stephen M. Gates , Michael W. Lane , Eric G. Liniger
IPC分类号： H01L21/44
CPC分类号： H01L23/564 , H01L24/05 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05009 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/48463 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method is disclosed of repairing wire bond damage on semiconductor chips such as high speed semiconductor microprocessors, application specific integrated circuits (ASICs), and other high speed integrated circuit devices, particularly devices using low-K dielectric materials. The method involves surface modification using reactive liquids. In a preferred embodiment, the method comprises applying a silicon-containing liquid reagent precursor such as TEOS to the surface of the chip and allowing the liquid reagent to react with moisture to form a solid dielectric plug or film (50) to produce a barrier against moisture ingress, thereby enhancing the temperature/humidity/bias (THB) performance of such semiconductor devices.
摘要翻译：公开了一种修复诸如高速半导体微处理器，专用集成电路（ASIC）和其它高速集成电路器件的半导体芯片上的引线键合损伤的方法，特别是使用低K电介质材料的器件。该方法涉及使用反应性液体的表面改性。在优选的实施方案中，该方法包括将诸如TEOS的含硅液体试剂前体施加到芯片的表面，并允许液体试剂与水分反应形成固体电介质塞或膜（50）以产生抵抗湿度进入，从而提高这种半导体器件的温度/湿度/偏差（THB）性能。

6. 发明授权

US06617690B1 Interconnect structures containing stress adjustment cap layer 有权
标题翻译：互连结构包含应力调整盖层
公开(公告)号：US06617690B1
公开(公告)日：2003-09-09
申请号：US10218292
申请日：2002-08-14
申请人： Stephen M. Gates , Timothy J. Dalton , John A. Fitzsimmons
发明人： Stephen M. Gates , Timothy J. Dalton , John A. Fitzsimmons
IPC分类号： H01L2940
CPC分类号： H01L23/53295 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Novel interconnect structures possessing a relatively low internal stress and dielectric constant for use in semiconductor devices are provided herein. The novel interconnect structures comprise a first layer having a coefficient of thermal expansion greater than about 20 ppm and a first internal stress associated therewith, the first layer having a first set of metallic lines formed therein; a second layer having a coefficient of thermal expansion less than about 20 ppm and a second internal stress associated therewith, the second layer having a second set of metallic lines formed therein; and one or more stress adjustment cap layers formed between the first layer and the second layer, the cap layer(s) having a third internal stress to offset the first stress of the first layer and the second stress of the second layer and inducing a favorable relief of stress on the interconnect structure. Methods for making a semiconductor device having a substantially reduced internal stress are also provided.
摘要翻译：本文提供了具有用于半导体器件的相对低的内应力和介电常数的新型互连结构。新颖的互连结构包括具有大于约20ppm的热膨胀系数的第一层和与其相关联的第一内部应力，第一层具有形成在其中的第一组金属线; 具有小于约20ppm的热膨胀系数的第二层和与其相关联的第二内应力，所述第二层在其中形成有第二组金属线; 以及形成在所述第一层和所述第二层之间的一个或多个应力调整盖层，所述盖层具有第三内应力以抵消所述第一层的第一应力和所述第二层的所述第二应力，并诱导有利的减轻互连结构上的应力。还提供了制造具有显着降低的内部应力的半导体器件的方法。

7. 发明授权

US08796150B2 Bilayer trench first hardmask structure and process for reduced defectivity 有权
标题翻译：双层沟槽第一硬掩模结构和减少缺陷的过程
公开(公告)号：US08796150B2
公开(公告)日：2014-08-05
申请号：US13012166
申请日：2011-01-24
申请人： Hakeem B. S. Akinmade-Yusuff , Samuel Sung Shik Choi , Edward R. Engbrecht , John A. Fitzsimmons
发明人： Hakeem B. S. Akinmade-Yusuff , Samuel Sung Shik Choi , Edward R. Engbrecht , John A. Fitzsimmons
IPC分类号： H01L21/311 , H01L21/32 , H01L29/06
CPC分类号： H01L21/31144 , H01L21/76804 , H01L21/76807
摘要： A method and structure for transferring a lithographic pattern into a substrate includes forming a dielectric hardmask layer over a dielectric substrate. A metal hardmask layer is formed over the dielectric hardmask layer. A protective capping hardmask layer or capping film is formed over the metal hardmask layer, and a lithographic structure for pattern transfer is formed over the capping layer. A pattern is transferred into the dielectric substrate using the defined lithographic structure. The capping hardmask layer can be removed during subsequent processing.
摘要翻译：用于将光刻图案转印到基板中的方法和结构包括在电介质基底上形成电介质硬掩模层。在介电硬掩模层上形成金属硬掩模层。在金属硬掩模层上形成保护性覆盖硬掩模层或覆盖膜，并且在覆盖层上形成用于图案转印的光刻结构。使用限定的光刻结构将图案转移到电介质基板中。在后续处理过程中，可以移除加盖硬掩模层。

8. 发明申请

US20130334691A1 SIDEWALLS OF ELECTROPLATED COPPER INTERCONNECTS 有权
标题翻译：电镀铜互连的边界
公开(公告)号：US20130334691A1
公开(公告)日：2013-12-19
申请号：US13525823
申请日：2012-06-18
申请人： Mukta G. Farooq , John A. Fitzsimmons , Troy L. Graves-Abe
发明人： Mukta G. Farooq , John A. Fitzsimmons , Troy L. Graves-Abe
IPC分类号： H01L23/52 , H01L21/283
CPC分类号： H05K3/423 , H01L21/76844 , H01L21/76846 , H01L21/76858 , H01L21/76898 , H01L23/481 , H01L23/53209 , H01L23/53214 , H01L23/53238 , H01L23/53242 , H01L23/53257 , H01L2924/0002 , Y10T428/12764 , H01L2924/00
摘要： A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material. The structure including a first intermetallic compound separating the diffusion barrier from the conductive material, the first intermetallic compound comprises an alloying material and the conductive material, and is mechanically bound to the conductive material, the alloying material is at least one of the materials selected from the group of chromium, tin, nickel, magnesium, cobalt, aluminum, manganese, titanium, zirconium, indium, palladium, and silver; and a first high friction interface located between the diffusion barrier and the first intermetallic compound and parallel to the sidewall of the opening, wherein the first high friction interface results in a mechanical bond between the diffusion barrier and the first intermetallic compound.
摘要翻译：一种形成在开口中的结构，其具有由非金属材料限定的基本上垂直的侧壁，并且具有由导电垫限定的基本上水平的底部，该结构包括覆盖侧壁的扩散阻挡层和由导电材料构成的填充物。所述结构包括将所述扩散阻挡物与所述导电材料分离的第一金属间化合物，所述第一金属间化合物包括合金材料和所述导电材料，并且机械地结合到所述导电材料上，所述合金材料是选自以下的至少一种材料：铬，锡，镍，镁，钴，铝，锰，钛，锆，铟，钯和银的组合; 以及位于所述扩散阻挡层和所述第一金属间化合物之间且平行于所述开口的侧壁的第一高摩擦界面，其中所述第一高摩擦界面导致所述扩散阻挡层和所述第一金属间化合物之间的机械结合。

9. 发明授权

US08288271B2 Method for reworking antireflective coating over semiconductor substrate 有权
标题翻译：在半导体衬底上重新制造抗反射涂层的方法
公开(公告)号：US08288271B2
公开(公告)日：2012-10-16
申请号：US12610679
申请日：2009-11-02
申请人： Hakeem Akinmade Yusuff , John A. Fitzsimmons , Ranee Wai-Ling Kwong
发明人： Hakeem Akinmade Yusuff , John A. Fitzsimmons , Ranee Wai-Ling Kwong
IPC分类号： H01L33/44 , H01L51/00
CPC分类号： H01L21/31138 , G03F7/091 , G03F7/422 , H01L21/0276 , H01L21/31144
摘要： A method and a structure for reworking an antireflective coating (ARC) layer over a semiconductor substrate. The method includes providing a substrate having a material layer, forming a planarization layer on the material layer, forming an organic solvent soluble layer on the planarization layer, forming an ARC layer on the organic solvent soluble layer, forming a pattern in the ARC layer, and removing the organic solvent soluble layer and the ARC layer with an organic solvent while leaving the planarization layer unremoved. The structure includes a substrate having a material layer, a planarization layer on the material layer, an organic solvent soluble layer on the planarization layer, and an ARC layer on the organic solvent soluble layer.
摘要翻译：一种用于在半导体衬底上再加工抗反射涂层（ARC）层的方法和结构。该方法包括提供具有材料层的基板，在材料层上形成平坦化层，在平坦化层上形成有机溶剂可溶层，在有机溶剂可溶层上形成ARC层，在ARC层中形成图案，并且用有机溶剂除去有机溶剂可溶层和ARC层，同时留下平坦化层不被除去。该结构包括具有材料层的基板，材料层上的平坦化层，平坦化层上的有机溶剂可溶层和有机溶剂可溶层上的ARC层。

10. 发明申请

US20110193199A1 ELECTROMIGRATION IMMUNE THROUGH-SUBSTRATE VIAS 有权
标题翻译：电磁辐射穿过基底VIAS
公开(公告)号：US20110193199A1
公开(公告)日：2011-08-11
申请号：US12702463
申请日：2010-02-09
申请人： Ronald G. Filippi , John A. Fitzsimmons , Kevin Kolvenbach , Ping-Chuan Wang
发明人： Ronald G. Filippi , John A. Fitzsimmons , Kevin Kolvenbach , Ping-Chuan Wang
IPC分类号： H01L23/48 , H01L21/50
CPC分类号： H01L25/0657 , H01L21/76898 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/10253 , H01L2924/1301 , H01L2924/1305 , H01L2924/00 , H01L2224/05552
摘要： A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.
摘要翻译：贯穿衬底通孔（TSV）结构包括至少两个嵌入衬底中的导电通路段，并且通过它们之间的导电阻挡层彼此分离。每个单独的导电通路段的长度通常等于或小于导电材料的漂浮长度，使得由每个导电阻挡层产生的应力引起的后向流动力抵消每个导电通路段中的电迁移力。因此，TSV结构免于电迁移，并且在三维堆叠的芯片之间提供可靠的电连接。

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