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1. 发明授权

US07989865B2 Deep trench capacitor for SOI CMOS devices for soft error immunity 有权
标题翻译：用于SOI CMOS器件的深沟槽电容器，用于软误差抗扰度
公开(公告)号：US07989865B2
公开(公告)日：2011-08-02
申请号：US12200538
申请日：2008-08-28
申请人： John Edward Barth, Jr. , Kerry Bernstein , Ethan Harrison Cannon , Francis Roger White
发明人： John Edward Barth, Jr. , Kerry Bernstein , Ethan Harrison Cannon , Francis Roger White
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0629 , H01L27/10861 , H01L29/66181
摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.
摘要翻译：公开了半导体结构。半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二所述第一侧与所述有源半导体层相邻，与所述绝缘体层的所述第二侧相邻配置的衬底，设置在所述半导体器件的所述主体/沟道区域下方的深沟槽电容器。深沟槽电容器与半导体器件的主体/沟道区电连接并接触半导体器件的主体/沟道区，并且位于半导体器件的栅极附近。半导体结构增加了临界电荷Qcrit，从而降低了半导体器件的软错误率（SER）。

2. 发明授权

US07954028B2 Structure for redundancy programming of a memory device 有权
标题翻译：存储器件冗余编程的结构
公开(公告)号：US07954028B2
公开(公告)日：2011-05-31
申请号：US12046508
申请日：2008-03-12
申请人： John Edward Barth, Jr. , Kevin William Gorman
发明人： John Edward Barth, Jr. , Kevin William Gorman
IPC分类号： G01R31/28
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/72
摘要： A design structure for implementing redundancy programming in a memory macro of an integrated circuit chip. It is assumed that all fails are row fails until determined to be bitline fails, circuits for implementing a method wherein it is assumed that all fails are row fails until determined to be bitline fails and test patterns are passed back to the failure detecting circuit when a wordline destination of the test patterns has previously been determined to be failing, and the test patterns and resultant patterns are passed between the memory macro and a test engine via logic paths connecting the memory macro to other circuits in said integrated circuit chip.
摘要翻译：一种用于在集成电路芯片的存储器宏中实现冗余编程的设计结构。假设所有故障都是行故障，直到确定为位线故障，用于实现其中假定全部故障的方法的电路是行失败，直到确定为位线失败，并且当a = 1时将测试模式传回故障检测电路测试图案的字线目的地已经被确定为失败，并且测试图案和结果图案通过将存储器宏连接到所述集成电路芯片中的其它电路的逻辑路径在存储器宏和测试引擎之间传递。

3. 发明授权

US06939797B2 Advanced BEOL interconnect structures with low-k PE CVD cap layer and method thereof 失效
标题翻译：具有低k PE CVD覆盖层的高级BEOL互连结构及其方法
公开(公告)号：US06939797B2
公开(公告)日：2005-09-06
申请号：US10706773
申请日：2003-11-12
申请人： Edward Barth , John A. Fitzsimmons , Stephen M. Gates , Thomas H. Ivers , Sarah L. Lane , Jia Lee , Ann McDonald , Vincent McGahay , Darryl D. Restaino
发明人： Edward Barth , John A. Fitzsimmons , Stephen M. Gates , Thomas H. Ivers , Sarah L. Lane , Jia Lee , Ann McDonald , Vincent McGahay , Darryl D. Restaino
IPC分类号： H01L21/311 , H01L21/314 , H01L21/316 , H01L21/318 , H01L21/768 , H01L23/532 , H01L21/4763 , H01L21/44 , H01L21/461
CPC分类号： H01L21/76834 , H01L21/31144 , H01L21/3148 , H01L21/31612 , H01L21/31633 , H01L21/3185 , H01L21/76801 , H01L21/76807 , H01L21/76832 , H01L21/76838 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.
摘要翻译：公开了一种先进的后端（BEOL）金属化结构。该结构包括具有低介电常数（低-k）的扩散阻挡层或覆盖层，其中通过等离子体增强化学气相沉积（PE CVD）工艺，覆盖层由氮化硅形成。金属化结构还包括由具有小于约4的介电常数的含碳电介质材料形成的层间电介质（ILD），以及优选由氮化硅或碳化硅形成的ILD上的连续硬掩模层。还公开了一种用于形成BEOL金属化结构的方法。该方法包括预清洁或预激活步骤，以改善盖层与下面的铜导体的粘合性。预清洁或预活化步骤包括将铜表面暴露于包括氢，氨，氮和/或惰性气体的还原等离子体。

4. 发明授权

US06737747B2 Advanced BEOL interconnect structures with low-k PE CVD cap layer and method thereof 有权
公开(公告)号：US06737747B2
公开(公告)日：2004-05-18
申请号：US10047965
申请日：2002-01-15
申请人： Edward Barth , John A. Fitzsimmons , Stephen M. Gates , Thomas H. Ivers , Sarah L. Lane , Jia Lee , Ann McDonald , Vincent McGahay , Darryl D. Restaino
发明人： Edward Barth , John A. Fitzsimmons , Stephen M. Gates , Thomas H. Ivers , Sarah L. Lane , Jia Lee , Ann McDonald , Vincent McGahay , Darryl D. Restaino
IPC分类号： H01L2348
CPC分类号： H01L21/76834 , H01L21/31144 , H01L21/3148 , H01L21/31612 , H01L21/31633 , H01L21/3185 , H01L21/76801 , H01L21/76807 , H01L21/76832 , H01L21/76838 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.

5. 发明授权

US5740068A Fidelity enhancement of lithographic and reactive-ion-etched images by optical proximity correction 失效
标题翻译：通过光学邻近校正对光刻和反应离子蚀刻图像的保真度增强
公开(公告)号：US5740068A
公开(公告)日：1998-04-14
申请号：US655790
申请日：1996-05-30
申请人： Lars Wolfgang Liebmann , Robert Thomas Sayah , John Edward Barth, Jr.
发明人： Lars Wolfgang Liebmann , Robert Thomas Sayah , John Edward Barth, Jr.
IPC分类号： G03F1/00 , G03F1/36 , G03F7/20 , H01L21/027 , G03F7/00 , H01J37/304
CPC分类号： G03F7/70441 , G03F1/36
摘要： A method for performing optical proximity correction is disclosed that not only limits the optical proximity correction to electrically relevant structures, but also improves the accuracy of the corrections by processing individual feature edges, and minimizes the mask manufacturing impacts by avoiding the introduction of jogs into the design. Critical edge regions of the relevant electrical structures are analyzed, sorted and manipulated to receive optical proximity corrections.
摘要翻译：公开了一种用于执行光学邻近校正的方法，其不仅将光学邻近校正限制到电气相关结构，而且还通过处理单个特征边缘来提高校正的精度，并且通过避免将点动灯引入到接近校正中来最小化掩模制造影响设计。对相关电气结构的临界边缘区域进行分析，分类和操作以接收光学邻近校正。

6. 发明授权

US08120968B2 High voltage word line driver 失效
标题翻译：高电压字线驱动器
公开(公告)号：US08120968B2
公开(公告)日：2012-02-21
申请号：US12704703
申请日：2010-02-12
申请人： William Robert Reohr , John Edward Barth, Jr. , Toshiaki Kirihata , Derek H. Leu , Donald W. Plass
发明人： William Robert Reohr , John Edward Barth, Jr. , Toshiaki Kirihata , Derek H. Leu , Donald W. Plass
IPC分类号： G11C16/06
CPC分类号： G11C8/08 , G11C11/4085
摘要： A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control signal. For the pull-up clamp transistor, the source is coupled to the drain of the pull-up transistor, the drain to the word line, and the gate to a pull-up clamp gate signal. For the pull-down transistor, the source is coupled to a second power supply, and the gate to a pull-down control signal. For the pull-down clamp transistor, the source is coupled to the drain of the pull-down transistor, the drain to the word line, and the gate to a pull-down clamp gate signal. The word line is coupled to one or more DRAM cells. Source to drain voltage magnitudes of the pull-up and pull-down transistors are less than a voltage between the first and second power supplies.
摘要翻译：耦合到存储器电路字线的字线驱动电路包括上拉，上拉钳位，下拉和下拉钳位晶体管，每个具有源极，漏极和栅极。对于上拉晶体管，源极耦合到第一电源，并将栅极耦合到上拉控制信号。对于上拉钳位晶体管，源极耦合到上拉晶体管的漏极，到字线的漏极，并将栅极耦合到上拉钳位信号。对于下拉晶体管，源极耦合到第二电源，并将栅极耦合到下拉控制信号。对于下拉钳位晶体管，源极耦合到下拉晶体管的漏极，漏极到字线，而栅极耦合到下拉钳位栅极信号。字线耦合到一个或多个DRAM单元。源极到漏极上拉和下拉晶体管的电压幅度小于第一和第二电源之间的电压。

7. 发明申请

US20110199837A1 High Voltage Word Line Driver 失效
标题翻译：高电压字线驱动器
公开(公告)号：US20110199837A1
公开(公告)日：2011-08-18
申请号：US12704703
申请日：2010-02-12
申请人： William Robert Reohr , John Edward Barth, JR. , Toshiaki Kirihata , Derek H. Leu , Donald W. Plass
发明人： William Robert Reohr , John Edward Barth, JR. , Toshiaki Kirihata , Derek H. Leu , Donald W. Plass
IPC分类号： G11C8/08 , G11C7/00
CPC分类号： G11C8/08 , G11C11/4085
摘要： A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control signal. For the pull-up clamp transistor, the source is coupled to the drain of the pull-up transistor, the drain to the word line, and the gate to a pull-up clamp gate signal. For the pull-down transistor, the source is coupled to a second power supply, and the gate to a pull-down control signal. For the pull-down clamp transistor, the source is coupled to the drain of the pull-down transistor, the drain to the word line, and the gate to a pull-down clamp gate signal. The word line is coupled to one or more DRAM cells. Source to drain voltage magnitudes of the pull-up and pull-down transistors are less than a voltage between the first and second power supplies.
摘要翻译：耦合到存储器电路字线的字线驱动电路包括上拉，上拉钳位，下拉和下拉钳位晶体管，每个具有源极，漏极和栅极。对于上拉晶体管，源极耦合到第一电源，并将栅极耦合到上拉控制信号。对于上拉钳位晶体管，源极耦合到上拉晶体管的漏极，到字线的漏极，并将栅极耦合到上拉钳位信号。对于下拉晶体管，源极耦合到第二电源，并将栅极耦合到下拉控制信号。对于下拉钳位晶体管，源极耦合到下拉晶体管的漏极，漏极到字线，而栅极耦合到下拉钳位栅极信号。字线耦合到一个或多个DRAM单元。源极到漏极上拉和下拉晶体管的电压幅度小于第一和第二电源之间的电压。

8. 发明授权

US07920434B2 Memory sensing method and apparatus 有权
标题翻译：存储器感测方法和装置
公开(公告)号：US07920434B2
公开(公告)日：2011-04-05
申请号：US12199438
申请日：2008-08-27
申请人： Mesut Meterelliyoz , John Edward Barth, Jr. , William Robert Reohr
发明人： Mesut Meterelliyoz , John Edward Barth, Jr. , William Robert Reohr
IPC分类号： G11C5/00
CPC分类号： G11C11/4091 , G11C11/4097
摘要： Techniques for sensing data states of respective memory cells in a memory array are provided, the memory array including at least a first bit line coupled to at least a subset of the memory cells. In one aspect, a circuit for sensing data states of respective memory cells in the memory array includes at least one sense amplifier coupled to the first bit line. The sense amplifier includes a first transistor operative to selectively inhibit charging of the first bit line in a manner which is independent of a voltage level on a second bit line coupled to the sense amplifier.
摘要翻译：提供了用于感测存储器阵列中的相应存储器单元的数据状态的技术，所述存储器阵列至少包括耦合到所述存储器单元的至少一个子集的第一位线。在一个方面，用于感测存储器阵列中各个存储单元的数据状态的电路包括耦合到第一位线的至少一个读出放大器。感测放大器包括第一晶体管，其操作以选择性地禁止第一位线的充电，其方式与在与读出放大器耦合的第二位线上的电压电平无关。

9. 发明授权

US07564729B2 Differential and hierarchical sensing for memory circuits 有权
标题翻译：存储电路的差分和分层感测
公开(公告)号：US07564729B2
公开(公告)日：2009-07-21
申请号：US12057011
申请日：2008-03-27
申请人： John Edward Barth, Jr. , Paul C. Parries , William Robert Reohr , Matthew R. Wordeman
发明人： John Edward Barth, Jr. , Paul C. Parries , William Robert Reohr , Matthew R. Wordeman
IPC分类号： G11C7/02
CPC分类号： G11C7/12 , G11C7/02 , G11C7/062 , G11C11/4091 , G11C11/4094
摘要： A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit. At least two block circuits are connected to a given pair of bank bit lines, the block circuits being configured such that a load on each bank bit line in the given pair of bank bit lines is substantially matched to one another.
摘要翻译：存储器电路包括多个字线，多对互补组位线，多个块选择线和多个块电路。每个块电路包括局部位线; 第一晶体管，其具有连接到本地位线的控制端子，连接到给定的一对组位线的第一组位线的第一偏置端子和连接到第一电压源的第二偏置端子; 第二晶体管，其具有连接到对应的一个块选择线的控制端子，连接到给定的一对组位线的第二组位线的第一偏置端子和连接到局部位线的第二偏置端子; 以及连接到本地位线和存储电路中的相应字线的多个存储单元。至少两个块电路连接到给定的一组组位线，块电路被配置为使得给定的一组组位线中的每个组位线上的负载基本上彼此匹配。

10. 发明申请

US20080170448A1 STRUCTURE FOR REDUNDANCY PROGRAMMING OF A MEMORY DEVICE 有权
标题翻译：用于存储器件冗余编程的结构
公开(公告)号：US20080170448A1
公开(公告)日：2008-07-17
申请号：US12046508
申请日：2008-03-12
申请人： John Edward Barth , Kevin William Gorman
发明人： John Edward Barth , Kevin William Gorman
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/72
摘要： A design structure for implementing redundancy programming in a memory macro of an integrated circuit chip. It is assumed that all fails are row fails until determined to be bitline fails, circuit means for implementing a method wherein it is assumed that all fails are row fails until determined to be bitline fails and test patterns are passed back to the failure detecting circuit when a wordline destination of the test patterns has previously been determined to be failing, and the test patterns and resultant patterns are passed between the memory macro and a test engine via logic paths connecting the memory macro to other circuits in said integrated circuit chip.
摘要翻译：一种用于在集成电路芯片的存储器宏中实现冗余编程的设计结构。假设所有故障都是行故障，直到确定为位线故障，用于实现其中假设所有故障都是行故障直到确定为位线故障并且测试模式被传回到故障检测电路的方法的电路装置测试图案的字线目的地已经被确定为失败，并且测试图案和结果图案通过将存储器宏连接到所述集成电路芯片中的其他电路的逻辑路径在存储器宏和测试引擎之间传递。

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