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1. 发明申请

US20070222081A1 SURFACE TREATMENT OF INTER-LAYER DIELECTRIC 有权
标题翻译：层间电介质的表面处理
公开(公告)号：US20070222081A1
公开(公告)日：2007-09-27
申请号：US11308422
申请日：2006-03-23
申请人： Shyng-Tsong Chen , Qinghung Lin , Kelly Malone , Sanjay Mehta , Terry Spooner , Chih-Chao Yang
发明人： Shyng-Tsong Chen , Qinghung Lin , Kelly Malone , Sanjay Mehta , Terry Spooner , Chih-Chao Yang
IPC分类号： H01L23/52
CPC分类号： H01L21/76825 , H01L21/3105 , H01L21/31058 , H01L21/76808 , H01L21/76814 , H01L21/76831
摘要： When an interconnect structure is built on porous ultra low k (ULK) material, the bottom of the trench and/or via is usually damaged by a following metallization process which may be suitable for dense higher dielectric materials. Embodiment of the present invention may provide a method of forming an interconnect structure on an inter-layer dielectric (ILD) material. The method includes steps of treating an exposed area of said ILD material to create a densified area, and metallizing said densified area.
摘要翻译：当在多孔超低k（ULK）材料上构建互连结构时，沟槽和/或通孔的底部通常被以下金属化工艺损坏，这可能适合于较高的介电材料。本发明的实施例可以提供在层间电介质（ILD）材料上形成互连结构的方法。该方法包括处理所述ILD材料的暴露区域以产生致密化区域以及金属化所述致密化区域的步骤。

2. 发明申请

US20070166996A1 METHOD OF MAKING A SEMICONDUCTOR STRUCTURE WITH A PLATING ENHANCEMENT LAYER 有权
标题翻译：用镀层增强层制作半导体结构的方法
公开(公告)号：US20070166996A1
公开(公告)日：2007-07-19
申请号：US11306930
申请日：2006-01-17
申请人： Shom Ponoth , Steven Chen , John Fitzsimmons , Terry Spooner
发明人： Shom Ponoth , Steven Chen , John Fitzsimmons , Terry Spooner
IPC分类号： H01L21/4763
CPC分类号： H01L21/76873 , H01L21/7688 , H01L2221/1089
摘要： Disclosed is a method of making a semiconductor structure, wherein the method includes forming an interlayer dielectric (ILD) layer on a semiconductor layer, forming a conductive plating enhancement layer (PEL) on the ILD, patterning the ILD and PEL, depositing a seed layer into the pattern formed by the ILD and PEL, and then plating copper on the seed layer. The PEL serves to decrease the resistance across the wafer so to facilitate the plating of the copper. The PEL preferably is an optically transparent and conductive layer.
摘要翻译：公开了一种半导体结构的制造方法，其特征在于，在半导体层上形成层间电介质层（ILD）层，在ILD上形成导电性电镀增强层（PEL），图案化ILD和PEL，进入由ILD和PEL形成的图案，然后在种子层上镀铜。 PEL用于降低晶片上的电阻，以便于镀铜。 PEL优选是光学透明且导电的层。

3. 发明申请

US20070117342A1 GCIB LINER AND HARDMASK REMOVAL PROCESS 有权
标题翻译： GCIB LINER和HARDMASK拆卸过程
公开(公告)号：US20070117342A1
公开(公告)日：2007-05-24
申请号：US11164423
申请日：2005-11-22
申请人： Shyng-Tsong Chen , John Fitzsimmons , Shom Ponoth , Terry Spooner
发明人： Shyng-Tsong Chen , John Fitzsimmons , Shom Ponoth , Terry Spooner
IPC分类号： H01L21/76
CPC分类号： H01L21/32136 , H01L21/31116 , H01L21/76802 , H01L21/7684
摘要： A method comprises depositing a dielectric film layer, a hard mask layer, and a patterned photo resist layer on a substrate. The method further includes selectively etching the dielectric film layer to form sub-lithographic features by reactive ion etch processing and depositing a barrier metal layer and a copper layer. The method further includes etching the barrier metal layer and hard mask layer by gas cluster ion beam (GCIB) processing.
摘要翻译：一种方法包括在衬底上沉积电介质膜层，硬掩模层和图案化光刻胶层。该方法还包括通过反应离子蚀刻处理选择性地蚀刻电介质膜层以形成亚光刻特征，并沉积阻挡金属层和铜层。该方法还包括通过气体簇离子束（GCIB）处理蚀刻阻挡金属层和硬掩模层。

4. 发明授权

US07135398B2 Reliable low-k interconnect structure with hybrid dielectric 有权
标题翻译：具有混合电介质的可靠的低k互连结构
公开(公告)号：US07135398B2
公开(公告)日：2006-11-14
申请号：US10901868
申请日：2004-07-29
申请人： John A. Fitzsimmons , Stephen E. Greco , Jia Lee , Stephen M. Gates , Terry Spooner , Matthew S. Angyal , Habib Hichri , Theordorus E. Standaert , Glenn A. Biery
发明人： John A. Fitzsimmons , Stephen E. Greco , Jia Lee , Stephen M. Gates , Terry Spooner , Matthew S. Angyal , Habib Hichri , Theordorus E. Standaert , Glenn A. Biery
IPC分类号： H01L21/4763
CPC分类号： H01L21/76832 , H01L21/76801 , H01L21/76807 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.
摘要翻译：公开了一种具有混合电介质的高级后端（BEOL）互连结构。用于通孔电平的层间电介质（ILD）优选地不同于线路电平的ILD。在优选实施例中，通孔级ILD由低k SiCOH材料形成，并且线级ILD由低k聚合物热固性材料形成。

5. 发明申请

US20060157857A1 Metal capped copper interconnect 有权
公开(公告)号：US20060157857A1
公开(公告)日：2006-07-20
申请号：US11376199
申请日：2006-03-16
申请人： Michael Lane , Stefanie Chiras , Terry Spooner , Robert Rosenberg
发明人： Michael Lane , Stefanie Chiras , Terry Spooner , Robert Rosenberg
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： C25D5/10 , C25D5/50 , C25D7/123 , H01L21/2885 , H01L21/76807 , H01L21/76843 , H01L21/76849 , H01L21/76867 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76886 , H01L23/53233 , H01L2924/0002 , H01L2924/00
摘要： A conducting material comprising: a conducting core region comprising copper and from 0.001 atomic percent to 0.6 atomic percent of one or more metals selected from iridium, osmium and rhenium; and an interfacial region. The interfacial region comprises at least 80 atomic percent or greater of the one or more metals. The invention is also directed to a method of making a conducting material comprising: providing an underlayer; contacting the underlayer with a seed layer, the seed layer comprising copper and one or more metals selected from iridium, osmium and rhenium; depositing a conducting layer comprising copper on the seed layer, and annealing the conducting layer at a temperature sufficient to cause grain growth in the conducting layer, yet minimize the migration of the one or more alloy metals from the seed layer to the conducting layer. The method further comprises polishing the conducting layer to provide a polished copper surface material, and annealing the polished copper surface material at a temperature to cause migration of the one or more metals from the seed layer to the polished surface to provide an interfacial region in contact with a copper conductor core region. The interfacial region and the copper conductor core region comprise the one or more metals.

6. 发明申请

US20060006070A1 Copper conductor 有权
标题翻译：铜导体
公开(公告)号：US20060006070A1
公开(公告)日：2006-01-12
申请号：US10887087
申请日：2004-07-09
申请人： Michael Lane , Stefanie Chiras , Terry Spooner , Robert Rosenberg , Daniel Edelstein
发明人： Michael Lane , Stefanie Chiras , Terry Spooner , Robert Rosenberg , Daniel Edelstein
IPC分类号： C25D1/00 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： C25D5/10 , C25D5/50 , C25D7/123 , H01L21/2885 , H01L21/76807 , H01L21/76843 , H01L21/76849 , H01L21/76867 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76886 , H01L23/53233 , H01L2924/0002 , H01L2924/00
摘要： A conducting material comprising: a conducting core region comprising copper and from 0.001 atomic percent to 0.6 atomic percent of one or more metals selected from iridium, osmium and rhenium; and an interfacial region. The interfacial region comprises at least 80 atomic percent or greater of the one or more metals. The invention is also directed to a method of making a conducting material comprising: providing an underlayer; contacting the underlayer with a seed layer, the seed layer comprising copper and one or more metals selected from iridium, osmium and rhenium; depositing a conducting layer comprising copper on the seed layer, and annealing the conducting layer at a temperature sufficient to cause grain growth in the conducting layer, yet minimize the migration of the one or more alloy metals from the seed layer to the conducting layer. The method further comprises polishing the conducting layer to provide a polished copper surface material, and annealing the polished copper surface material at a temperature to cause migration of the one or more metals from the seed layer to the polished surface to provide an interfacial region in contact with a copper conductor core region. The interfacial region and the copper conductor core region comprise the one or more metals.
摘要翻译：一种导电材料，包括：导电核心区域，其包含铜和0.001原子％至0.6原子％的选自铱，锇和铼的一种或多种金属; 和界面区域。所述界面区域包含所述一种或多种金属的至少80原子％以上。本发明还涉及一种制造导电材料的方法，包括：提供底层; 使底层与种子层接触，晶种层包含铜和一种或多种选自铱，锇和铼的金属; 在种子层上沉积包含铜的导电层，并且在足以在导电层中引起晶粒生长的温度下对导电层退火，同时最小化一种或多种合金金属从晶种层向导电层的迁移。该方法还包括抛光导电层以提供抛光的铜表面材料，并且在一定温度下退火抛光的铜表面材料，以使一种或多种金属从晶种层迁移到抛光表面以提供接触的界面区域具有铜导体核心区域。界面区域和铜导体芯区域包括一种或多种金属。

7. 发明申请

US20050118796A1 Process for forming an electrically conductive interconnect 审中-公开
标题翻译：用于形成导电互连的工艺
公开(公告)号：US20050118796A1
公开(公告)日：2005-06-02
申请号：US10722558
申请日：2003-11-28
申请人： Stefanie Chiras , Michael Lane , Robert Rosenberg , Terry Spooner
发明人： Stefanie Chiras , Michael Lane , Robert Rosenberg , Terry Spooner
IPC分类号： H01L21/768 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76846
摘要： An electrically conductive metallic interconnect in a trench or via in a dielectric is provided by depositing a first liner layer on the walls and bottom of the trench or via; removing residual contamination from the bottom of the trench or via; depositing a second liner layer in the trench; depositing a seed layer and filling the trench with electrically conductive metallic material.
摘要翻译：通过在沟槽或通孔的壁和底部上沉积第一衬里层来提供电介质中沟槽或通路中的导电金属互连件; 去除沟槽底部或通孔的残留污染物; 在沟槽中沉积第二衬里层; 沉积种子层并用导电金属材料填充沟槽。

8. 发明授权

US06784105B1 Simultaneous native oxide removal and metal neutral deposition method 有权
标题翻译：同时自然氧化物去除和金属中性沉积法
公开(公告)号：US06784105B1
公开(公告)日：2004-08-31
申请号：US10410496
申请日：2003-04-09
申请人： Chih-Chao Yang , Yun Wang , Larry Clevenger , Andrew Simon , Stephen Greco , Kaushik Chanda , Terry Spooner , Andy Cowley , Sunfei Fang
发明人： Chih-Chao Yang , Yun Wang , Larry Clevenger , Andrew Simon , Stephen Greco , Kaushik Chanda , Terry Spooner , Andy Cowley , Sunfei Fang
IPC分类号： H01L2144
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76838 , H01L21/76862 , H01L21/76865
摘要： A method of fabricating a semiconductor device having a dielectric structure on which an interconnect structure is optionally patterned using lithographic and etching techniques, within a single deposition chamber, is provided. The dielectric structure may optionally be covered by diffusion barrier materials prior to a sputter etching process. This sputter etching process is used to remove the native oxide on an underneath metal conductor surface and includes a directional gaseous bombardment with simultaneous deposition of metal neutral. Diffusion barrier materials may also be deposited into the pattern.
摘要翻译：提供一种制造具有电介质结构的半导体器件的方法，其中使用光刻和蚀刻技术在单个淀积室内使互连结构任意地图案化。在溅射蚀刻工艺之前，电介质结构可任选地被扩散阻挡材料覆盖。该溅射蚀刻工艺用于去除下面的金属导体表面上的自然氧化物，并且包括具有同时沉积金属中性的定向气体轰击。扩散阻挡材料也可以沉积到图案中。

9. 发明申请

US20070246792A1 METHOD FOR FABRICATING BACK END OF THE LINE STRUCTURES WITH LINER AND SEED MATERIALS 有权
标题翻译：用衬里和种子材料制作线结构的后端的方法
公开(公告)号：US20070246792A1
公开(公告)日：2007-10-25
申请号：US11380074
申请日：2006-04-25
申请人： Chih-Chao Yang , Shyng-Tsong Chen , Shom Ponoth , Terry Spooner
发明人： Chih-Chao Yang , Shyng-Tsong Chen , Shom Ponoth , Terry Spooner
IPC分类号： H01L29/00 , H01L21/4763
CPC分类号： H01L21/76846 , H01L21/76865
摘要： A sputter-etching method employed to achieve a thinned down noble metal liner layer deposited on the surface or field of an intermediate back end of the line (BEOL) interconnect structure. The noble metal liner layer is substantially thinned down to a point where the effect of the noble metal has no significant effect in the chemical-mechanical polishing (CMP) process. The noble metal liner layer may be completely removed by sputter etching to facilitate effective planarization by chemical-mechanical polishing to take place.
摘要翻译：用于实现沉积在线（BEOL）互连结构的中间后端的表面或场上的减薄的贵金属衬里层的溅射蚀刻方法。贵金属衬里层基本上变薄到贵金属的作用在化学机械抛光（CMP）工艺中没有显着影响的程度。可以通过溅射蚀刻完全去除贵金属衬里层，以便通过化学机械抛光发生有效的平坦化。

10. 发明申请

US20060043590A1 MAINTAINING UNIFORM CMP HARD MASK THICKNESS 有权
标题翻译：维持均匀的CMP硬掩模厚度
公开(公告)号：US20060043590A1
公开(公告)日：2006-03-02
申请号：US10711145
申请日：2004-08-27
申请人： Steven Shyng-Tsong Chen , Kaushik Kumar , Stephen Greco , Shom Ponoth , Terry Spooner , David Rath , Wei-Tsu Tseng
发明人： Steven Shyng-Tsong Chen , Kaushik Kumar , Stephen Greco , Shom Ponoth , Terry Spooner , David Rath , Wei-Tsu Tseng
IPC分类号： H01L21/4763 , H01L23/48 , H01L23/52 , H01L29/40 , H01L21/31 , H01L21/469
CPC分类号： H01L21/7684 , H01L21/3212 , H01L21/76832 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A chemical mechanical polishing (CMP) step is used to remove excess conductive material (e.g., Cu) overlying a low-k or ultralow-k interlevel dielectric layer (ILD) layer having trenches filled with conductive material, for a damascene interconnect structure. A reactive ion etch (RIE) or a Gas Cluster Ion Beam (GCIB) process is used to remove a portion of a liner which is atop a hard mask. A wet etch step is used to remove an oxide portion of the hard mask overlying the ILD, followed by a final touch-up Cu CMP (CMP) step which chops the protruding Cu patterns off and lands on the SiCOH hard mask. In this manner, processes used to remove excess conductive material substantially do not affect the portion of the hard mask overlying the interlevel dielectric layer.
摘要翻译：化学机械抛光（CMP）步骤用于去除覆盖在具有填充有导电材料的沟槽的低k或超低k层间介质层（ILD）层上的过剩导电材料（例如Cu），用于镶嵌互连结构。使用反应离子蚀刻（RIE）或气体簇离子束（GCIB）方法去除位于硬掩模顶部的衬垫的一部分。使用湿蚀刻步骤去除覆盖在ILD上的硬掩模的氧化物部分，随后是最后的上覆Cu CMP（CMP）步骤，其将突出的Cu图案切掉并落在SiCOH硬掩模上。以这种方式，用于去除过量的导电材料的工艺基本上不影响覆盖层间电介质层的硬掩模的部分。

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