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1. 发明申请

US20060014371A1 Method for forming an integrated semiconductor circuit arrangement 有权
公开(公告)号：US20060014371A1
公开(公告)日：2006-01-19
申请号：US11138984
申请日：2005-05-26
申请人： Johann Rieger , Stefan Lipp , Hans Zeindl , Thomas Detzel , Hubert Maier
发明人： Johann Rieger , Stefan Lipp , Hans Zeindl , Thomas Detzel , Hubert Maier
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76838 , H01L21/7684
摘要： Methods for forming an integrated semiconductor circuit arrangement are disclosed. In one embodiment, a semiconductor circuit with a first semiconductor circuit region and with a second semiconductor circuit region is formed in each case in a semiconductor material region. A first metallization layer is applied to the structure thus obtained. A protective material region is then formed. A second metallization layer is subsequently applied, which is then also patterned. Afterward, the first metallization layer together with the protective material region is then patterned.

2. 发明授权

US07531439B2 Method for forming an integrated semiconductor circuit arrangement 有权
标题翻译：用于形成集成半导体电路装置的方法
公开(公告)号：US07531439B2
公开(公告)日：2009-05-12
申请号：US11138984
申请日：2005-05-26
申请人： Johann Rieger , Stefan Lipp , Hans Peter Zeindl , Thomas Detzel , Hubert Maier
发明人： Johann Rieger , Stefan Lipp , Hans Peter Zeindl , Thomas Detzel , Hubert Maier
IPC分类号： H01L21/44
CPC分类号： H01L21/76838 , H01L21/7684
摘要： Methods for forming an integrated semiconductor circuit arrangement are disclosed. In one embodiment, a semiconductor circuit with a first semiconductor circuit region and with a second semiconductor circuit region is formed in each case in a semiconductor material region. A first metallization layer is applied to the structure thus obtained. A protective material region is then formed. A second metallization layer is subsequently applied, which is then also patterned. Afterward, the first metallization layer together with the protective material region is then patterned.
摘要翻译：公开了形成集成半导体电路装置的方法。在一个实施例中，在半导体材料区域中形成具有第一半导体电路区域和第二半导体电路区域的半导体电路。将第一金属化层施加到由此获得的结构上。然后形成保护材料区域。随后施加第二金属化层，然后将其图案化。之后，将第一金属化层与保护材料区域一起构图。

3. 发明授权

US5731718A Evaluation and amplifier circuit 失效
标题翻译：评估和放大电路
公开(公告)号：US5731718A
公开(公告)日：1998-03-24
申请号：US723847
申请日：1996-09-30
申请人： Johann Rieger
发明人： Johann Rieger
IPC分类号： G11C11/417 , G11C7/06 , G11C11/409 , G11C11/4091 , G01C7/00
CPC分类号： G11C11/4091 , G11C7/065
摘要： An evaluation and amplifier circuit of the type of a keyed flipflop including at least two first transistors of a given channel type connected in series to each other disposed between first and second signal lines, has a connection from the gates of the first transistors to a respective one of the second and first signal lines. The first two transistors respectively form a first node common to the first two transistors for receiving a first control signal. A series circuit has at least two second transistors of the same channel type as the first transistors being connected in parallel to the first transistors, The gates of the first transistors are further connected with a respective one of the second and first signal lines. Furthermore, the amplifier circuit includes the feature that the second transistors form a second node common to the second transistors for receiving a second control signal, and a differential signal appearing on the signal lines is evaluated and amplified by the second transistors after the first transistors have received the differential signal.
摘要翻译：具有连接在第一和第二信号线之间的彼此串联连接的给定沟道类型的至少两个第一晶体管的键控触发器类型的评估和放大器电路具有从第一晶体管的栅极到相应的第一晶体管的连接第二和第一信号线之一。前两个晶体管分别形成用于接收第一控制信号的前两个晶体管公共的第一节点。串联电路具有与第一晶体管并联连接的至少两个与第一晶体管并联的沟道类型的第二晶体管。第一晶体管的栅极与第二和第一信号线中的相应一个进一步连接。此外，放大器电路包括第二晶体管形成用于接收第二控制信号的第二晶体管公共的第二节点的特征，并且在第一晶体管具有第一晶体管之后，出现在信号线上的差分信号由第二晶体管评估和放大接收差分信号。

4. 发明授权

US4940183A Arrangement for fastening rails 失效
标题翻译：紧固导轨的布置
公开(公告)号：US4940183A
公开(公告)日：1990-07-10
申请号：US346746
申请日：1989-05-03
申请人： Johann Rieger , Hermann Orasche
发明人： Johann Rieger , Hermann Orasche
IPC分类号： E01B9/52 , E01B9/60 , E01B11/06
CPC分类号： E01B9/52 , E01B11/06 , E01B9/60
摘要： In an arrangement for fastening stock rails, wing rails or track rails (1) at the side being averted from the running edge, in which arrangement a strap (5) is pressed against the web of the rail with interposition of a leaf spring (9) or, respectively, of a spring pile, the strap (5) is given a convex shape at its outer side facing the leaf spring (9), whereby a defined pressure point (D) is provided for the attack of the leaf spring (9).
摘要翻译：在用于紧固弹簧轨道的翼片轨道或轨道轨道（1）的布置中，从行驶边缘避开该轨道（1），在该布置中，带（5）被压靠在轨道的腹板上，插入板簧）或分别为弹簧桩，所述带（5）在其面向所述板簧（9）的外侧具有凸形形状，由此提供限定的压力点（D）用于板簧的攻击（ 9）。

5. 发明授权

US06366511B2 Method for checking a semiconductor memory device 有权
标题翻译：用于检查半导体存储器件的方法
公开(公告)号：US06366511B2
公开(公告)日：2002-04-02
申请号：US09910745
申请日：2001-07-23
申请人： Johann Rieger , Thomas Von Der Ropp
发明人： Johann Rieger , Thomas Von Der Ropp
IPC分类号： G11C700
CPC分类号： G11C29/028 , G11C11/401 , G11C29/50 , G11C2029/5004
摘要： A method for checking a semiconductor memory device integrated on a semiconductor chip includes providing the semiconductor memory device with a plurality of memory cells each being disposed on a semiconductor substrate for one binary information value, data lines for reading out and writing in information values, gate transistors being associated with the memory cells for selectively clearing a data path between a given memory cell and a data line, selection lines for purposefully triggering the gate transistors, and at least one in-chip reference voltage being adjusted to a predetermined normal value when the semiconductor memory device is functioning as intended. The method for checking the semiconductor memory device integrated on a semiconductor chip is carried out by at least intermittently varying the at least one in-chip reference voltage, and detecting and weighting the information values read out at the at least intermittently varied reference voltage.
摘要翻译：一种用于检查集成在半导体芯片上的半导体存储器件的方法包括：为半导体存储器件提供多个存储单元，每个存储单元分别设置在半导体衬底上用于一个二进制信息值，用于读出和写入信息值的数据线，门晶体管与存储器单元相关联，用于选择性地清除给定存储单元和数据线之间的数据通路，用于有目的地触发栅极晶体管的选择线，以及至少一个片上参考电压被调整到预定正常值时半导体存储器件按预期工作。用于检查集成在半导体芯片上的半导体存储器件的方法至少间歇地改变至少一个片上参考电压，并且检测和加权在至少间歇变化的参考电压读出的信息值。

6. 发明授权

US5125603A Sliding chair, sliding plate and ribbed plate, respectively, for railway switches or railway crossings 失效
标题翻译：滑动椅，滑板和钢板，适用于铁路开关或铁路交叉
公开(公告)号：US5125603A
公开(公告)日：1992-06-30
申请号：US530593
申请日：1990-05-30
申请人： Hermann Orasche , Johann Rieger , Heinz Steiger
发明人： Hermann Orasche , Johann Rieger , Heinz Steiger
IPC分类号： E01B7/06 , E01B7/00 , E01B7/02 , E01B9/54
CPC分类号： E01B7/02 , E01B2202/042 , E01B2202/06
摘要： A railway structure for a sliding chair (2), a sliding plate and a ribbed plate (1), respectively, for railway switches or railway crossings. The structure includes friction-reducing sliding members (4, 5) of synthetic plastic material being releasably mounted within recesses (3) in the sliding chair (2) and the plates, respectively. There are accommodated within each recess (3) at least two sliding members (4, 5) having their side surfaces engaged over the major part of the periphery by inwardly protruding walls or profiles of the edge of the recess, so that there results a safe mounting in position of the sliding members (4, 5). The structure makes the interchange of the sliding members a simple procedure.
摘要翻译：分别用于铁路开关或铁路路口的滑椅（2），滑板和肋板（1）的铁路结构。该结构包括合成塑料材料的减摩滑动构件（4,5）可释放地分别安装在滑椅（2）和板中的凹槽（3）内。在每个凹部（3）内容纳有至少两个滑动构件（4,5），它们的侧表面通过向内突出的凹部的边缘或外形而在周边的主要部分上接合，从而使得安全安装在滑动构件（4,5）的位置。该结构使得滑动构件的交换变得简单。

7. 发明授权

US5783962A Bootstrap circuit and integrated memory circuit having the bootstrap circuit 失效
标题翻译：自举电路和具有自举电路的集成存储器电路
公开(公告)号：US5783962A
公开(公告)日：1998-07-21
申请号：US679372
申请日：1996-07-08
申请人： Johann Rieger
发明人： Johann Rieger
IPC分类号： G11C11/407 , G11C5/14 , G11C8/08 , H03K17/06 , H03K17/16
CPC分类号： H03K17/063 , G11C5/145 , G11C8/08
摘要： A bootstrap circuit includes a transfer transistor and a driver transistor of the same channel type each having two channel terminals and a gate. A first signal terminal receives a first signal and a second signal terminal receives a second signal. One of the channel terminals of the transfer transistor is connected to the gate of the driver transistor. The other of the channel terminals of the transfer transistor is connected to the first signal terminal. One of the channel terminals of the driver transistor is connected to the second signal terminal. The other of the channel terminals of the driver transistor forms an output of the bootstrap circuit. A configuration generates a third signal and has an output connected to the gate of the transfer transistor. The second signal has an edge extending from a first level to a second level and beginning at a bootstrap time. The first signal has a precharging level between the first level and the second level of the second signal occurring no later than another time being at the latest equal to the bootstrap time. After the other time, the third signal has a first level being equal to or located on the other side of the level of the first signal as seen from the second level of the second signal. Before the other time, the third signal has a second level being on the same side of the precharging level of the first signal as seen from the second level of the second signal.
摘要翻译：自举电路包括传输晶体管和具有两个通道端子和栅极的相同通道类型的驱动器晶体管。第一信号终端接收第一信号，第二信号终端接收第二信号。传输晶体管的通道端子之一连接到驱动晶体管的栅极。传输晶体管的另一个通道端子连接到第一信号端子。驱动晶体管的通道端子之一连接到第二信号端子。驱动器晶体管的另一个通道端子形成自举电路的输出。配置产生第三信号并且具有连接到传输晶体管的栅极的输出。第二信号具有从第一级延伸到第二级的边缘并且在引导时间开始。所述第一信号具有在所述第二信号的所述第一电平和所述第二电平之间的预充电电平不迟于等于所述自举时间的另一时间。在另一时间之后，第三信号具有与第二信号的第二电平相同的第一电平等于或位于第一信号的电平的另一侧。在另一时间之前，第三信号具有与第二信号的第二电平相似的第一信号的预充电电平的同一侧。

8. 发明授权

US5459690A Integrated semiconductor memory with redundancy arrangement 失效
标题翻译：具有冗余布置的集成半导体存储器
公开(公告)号：US5459690A
公开(公告)日：1995-10-17
申请号：US920315
申请日：1992-08-17
申请人： Johann Rieger , Johann Stecker
发明人： Johann Rieger , Johann Stecker
IPC分类号： G11C29/00 , G06F20060101 , G06F11/16 , G11C20060101 , G11C7/00 , G11C29/04
CPC分类号： G11C29/781 , G11C29/806 , G11C29/808 , G11C29/846
摘要： An integrated semiconductor memory has a block decoder BKDEC having block selection signals BKS and a plurality of main memory area block units BK which can be individually activated. The main memory area block units BK contain memory locations which can be selected via word and bit lines NWL, NBL, NBL and redundancy memory locations RMC, which can be selected via redundancy word lines RWL. The main memory area block units BK contain programmable redundancy block decoders RBK, which in conjunction with redundancy word line decoders RWDEC enable the selection of redundancy word lines RWL. If a redundancy word line RWL is to be selected, it is exclusively that main memory area block unit BK in which the redundancy word line RWL that is to be selected is contained that is activated. In this case, activation which is otherwise usual is suppressed via an appropriate block selection signal BKS. It is rendered possible in this way that the redundancy word line RWL that is to be selected together with its redundancy memory locations RMC can be arranged in a different main memory area block unit BK from the memory locations to be replaced together with their normal word lines NWL, but also in an (any) other main memory area block unit BK. It is possible in this way to increase the yield in the production of integrated semiconductor memories.
摘要翻译： PCT No.PCT / DE92 / 00316 Sec。 371日期：1992年8月17日 102（e）日期1992年8月17日PCT提交1992年4月16日PCT公布。出版物WO93 / 21578 日期为1993年10月28日。集成半导体存储器具有块解码器BKDEC，其具有块选择信号BKS和可单独激活的多个主存储区域块单元BK。主存储器区块单元BK包含可以经由字线和位线NWL，NBL，＆UPbar＆N和冗余存储器位置RMC选择的存储器位置，其可以通过冗余字线RWL选择。主存储区域块单元BK包含可编程冗余块解码器RBK，其与冗余字线解码器RWDEC一起使能冗余字线RWL的选择。如果要选择冗余字线RWL，则仅包含被激活的要被选择的冗余字线RWL的主存储器区块单元BK。在这种情况下，通过适当的块选择信号BKS来抑制否则通常的激活。以这种方式可以使得要与其冗余存储器位置RMC一起选择的冗余字线RWL可以被布置在与要被替换的存储器位置不同的主存储区域块单元BK中，与其正常字线 NWL，也可以在（任何）其他主存储区块BK中。以这种方式可以提高集成半导体存储器的生产中的产量。

9. 发明授权

US4981264A Device for fixing stock rails in railway switches as well as process for fixing stock rails by means of such device 失效
标题翻译：用于固定铁路开关中的导轨的装置以及借助于这种装置固定导轨的工艺
公开(公告)号：US4981264A
公开(公告)日：1991-01-01
申请号：US353025
申请日：1989-05-17
申请人： Hermann Orasche , Johann Rieger
发明人： Hermann Orasche , Johann Rieger
IPC分类号： E01B7/02 , E01B7/22
CPC分类号： E01B7/02 , E01B7/22
摘要： In a device for fixing stock rails (1) in railway switches, including a base plate (2) for the stock rail (1) and a sliding chair (3) for the switch tongue mounted on the base plate and comprising an elongated spring element (6) for pressing down the rail foot and preferably having the shape of a plate, the spring element (6) can be introduced, preferably without tension, into a tunnel-shaped recess (5) provided in the sliding chair (3) and extending in a direction approximately normal to the stock rail. The upper edge of the tongue-shaped recess (5) within the sliding chair (3) extends, with the formation of a kink (13), in direction towards the rail foot steeper in upward direction that in an area (11) extending more flatly in front of the kink (13). A separate wedge (10) can, for the purpose of guying the spring element (6) against the rail foot, be driven in within the area (11) of flatter extension of the upper edge at a distance from the kink (13) of the upper edge. On account of the wedges presence, a progressive spring characteristic of the spring element (6) can easily be adapted to the requirements.
摘要翻译：在用于在铁路开关中固定库存轨道（1）的装置中，包括用于库存轨道（1）的基板（2）和用于安装在基板上的开关舌的滑动椅（3），并且包括细长的弹簧元件（6）用于压下导轨脚并且优选地具有板的形状，弹簧元件（6）可以优选地没有张力地被引入设置在滑动椅子（3）中的隧道形凹部（5）中，并且沿大致垂直于钢轨的方向延伸。在滑椅（3）内的舌形凹部（5）的上边缘沿着朝向轨道脚的方向形成扭结（13），在向上方向上更陡，在更延伸的区域（11）中在扭结前面（13）。为了使弹簧元件（6）抵靠导轨脚，单独的楔形件（10）可以被驱动在与上边缘的平坦延伸区域（11）相距一定距离处上边缘。由于楔子存在，弹簧元件（6）的渐进弹簧特性可以容易地适应要求。

10. 发明授权

US5675543A Integrated semiconductor memory device 失效
标题翻译：集成半导体存储器件
公开(公告)号：US5675543A
公开(公告)日：1997-10-07
申请号：US694533
申请日：1996-08-09
申请人： Johann Rieger
发明人： Johann Rieger
IPC分类号： G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/80 , G11C29/846
摘要： Integrated semiconductor memory device having a semiconductor substrate with a redundant circuit arrangement formed thereon for replacing a defective memory cell of the integrated semiconductor memory device by selecting a redundant memory cell likewise disposed on the semiconductor substrate, the memory cells of the integrated semiconductor memory device being constructed and addressable in blocks; the redundant memory cells being combined into a redundant memory cell field addressable as a unit by the redundant circuit arrangement; and the redundant circuit arrangement having a redundant selection circuit for selecting a redundant memory cell from the redundant memory cell field to replace a defective memory cell from any of the memory cell blocks, includes a redundance control circuit forming part of the redundant circuit arrangement and enabling, as a function of a programmed redundant selection signal, one of the data content of a normal memory cell and the data content of a redundant memory cell suitably substituted in the event of a defect in the normal memory cell of the redundant memory cell field, the redundance control circuit being connected downstream from read amplifier circuits for reading out data from the normal memory cells and from read amplifier circuits for reading out redundant data from the redundant memory cells.
摘要翻译：一种集成半导体存储器件，具有形成有冗余电路装置的半导体衬底，用于通过选择同样设置在半导体衬底上的冗余存储单元来替换集成半导体存储器件的有缺陷的存储单元，所述集成半导体存储器件的存储单元为构造和可寻址的块; 所述冗余存储单元被组合成冗余存储单元区域，所述冗余存储器单元可由所述冗余电路装置作为单元寻址; 并且所述冗余电路装置具有冗余选择电路，用于从所述冗余存储单元字段中选择冗余存储器单元以从任何存储单元块替换有缺陷的存储器单元，所述冗余选择电路包括冗余控制电路，其形成所述冗余电路装置的一部分并使能作为编程冗余选择信号的函数，正常存储单元的数据内容之一和在冗余存储单元字段的正常存储单元中的缺陷的情况下适当替代的冗余存储单元的数据内容，冗余控制电路连接在读取放大器电路的下游，用于从正常存储单元读出数据，并从读取放大器电路连接用于从冗余存储单元读出冗余数据。

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