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1. 发明申请

US20050237821A1 Method and system of external data storage 失效
标题翻译：外部数据存储的方法和系统
公开(公告)号：US20050237821A1
公开(公告)日：2005-10-27
申请号：US11055881
申请日：2005-02-11
申请人： Gerard Dekker , Albert Bosscha , Antonius Johannes Van De Ven
发明人： Gerard Dekker , Albert Bosscha , Antonius Johannes Van De Ven
IPC分类号： G06F12/10 , G06F20060101 , G06F1/00 , G06F3/06 , G06F12/00 , G06F12/14 , G06F13/00 , G06F13/10 , G06F13/16 , G06F15/16 , G06F17/30 , G06F21/24 , G07F7/10 , G09C1/00 , G11C20060101 , G11C5/00 , H04L20060101
CPC分类号： G07F7/1008 , G06Q20/341 , G06Q20/346 , G06Q20/3552 , G06Q20/357 , G06Q20/40975
摘要： A method of external data storage in a system including a primary processing device, having a processor and a primary data storage unit, adapted to run application programs for processing active records in the processor and configured to store data belonging to active records in the primary data storage unit; and a secondary data storage system, accessible to the primary processing device, includes loading data belonging to an active record into the primary data storage unit and externalising the record by transferring at least a piece of data belonging to the record to the secondary data storage system for storage. The step of externalising a record includes the making of a call by an application program using data belonging to the record to an interface, arranged to transfer the piece of data to the secondary data storage system.
摘要翻译：一种包括主处理装置的系统中的外部数据存储方法，所述主处理装置具有处理器和主数据存储单元，所述处理器和主数据存储单元适于运行用于处理所述处理器中的活动记录的应用程序，并且被配置为将属于所述主数据的数据存储单元; 以及主处理设备可访问的辅助数据存储系统包括将属于活动记录的数据加载到主数据存储单元中，并且通过将属于该记录的至少一条数据传送到次级数据存储系统来对该记录进行外部化用于存储。外部化记录的步骤包括使用属于该记录的数据由应用程序进行的呼叫，被布置成将该数据块传送到次要数据存储系统。

2. 发明申请

US20050226031A1 Low leakage asymmetric sram cell devices 有权
标题翻译：低泄漏非对称sram细胞器件
公开(公告)号：US20050226031A1
公开(公告)日：2005-10-13
申请号：US10524319
申请日：2003-08-08
申请人： Farid Najm , Navid Azizi , Andreas Moshovos
发明人： Farid Najm , Navid Azizi , Andreas Moshovos
IPC分类号： G11C20060101 , G11C7/00 , G11C7/02 , G11C7/06 , G11C11/00 , G11C11/34 , G11C11/412
CPC分类号： G11C7/067 , G11C7/062 , G11C11/412
摘要： Asymmetric SRAM cell designs exploiting data storage patterns found in ordinary software programs wherein most of the bits stored are zeroes for data and instruction streams. The asymmetric SRAM cell designs offer lower leakage power with little impact on latency. In asymmetric SRAM cells, selected transistors are “weakened” to reduce leakage current when the cell is storing a zero. Transistor weakening may be achieved by using higher voltage threshold transistors, by varying transistor geometries, or other means. In addition, a novel sense amplifier design is provided that leverages the asymmetric nature of the asymmetric SRAM cells to offer cell read times that are comparable with conventional symmetric SRAM cells. Lastly, cache memory designs are provided that are based on asymmetric SRAM cells offering leakage power reduction while maintaining high performance, comparable noise margins, and stability with respect to conventional cache memories.
摘要翻译：非对称SRAM单元设计利用在普通软件程序中发现的数据存储模式，其中存储的大部分位为零，用于数据和指令流。非对称SRAM单元设计提供较低的漏电功率，对延迟影响不大。在非对称SRAM单元中，当单元存储零时，所选择的晶体管被“削弱”以减少泄漏电流。可以通过使用较高电压阈值晶体管，通过改变晶体管几何形状或其他方式来实现晶体管弱化。此外，提供了一种新颖的读出放大器设计，其利用非对称SRAM单元的非对称特性来提供与常规对称SRAM单元相当的单元读取时间。最后，提供基于非对称SRAM单元的缓存存储器设计，其提供泄漏功率降低，同时保持高性能，可比较的噪声容限和相对于常规高速缓冲存储器的稳定性。

3. 发明授权

US06909633B2 MRAM architecture with a flux closed data storage layer 失效
标题翻译：具有磁通闭合数据存储层的MRAM架构
公开(公告)号：US06909633B2
公开(公告)日：2005-06-21
申请号：US10688664
申请日：2003-10-16
申请人： David Tsang
发明人： David Tsang
IPC分类号： G11C20060101 , G11C11/02 , G11C11/15 , G11C11/16 , G11C11/22 , H01L23/48
CPC分类号： G11C11/16
摘要： A method and system for providing and using a magnetic memory are disclosed. The method and system include providing a plurality of magnetic memory cells and providing at least one magnetic write line coupled with the plurality of magnetic memory cells. Each of the magnetic memory cells includes a magnetic element having a data storage layer. The data storage layer stores data magnetically. The magnetic write line(s) are magnetostatically coupled with at least the data storage layer of the magnetic element of the corresponding magnetic memory cells. Consequently, flux closure is substantially achieved for the data storage layer of each of the plurality of magnetic memory cells.
摘要翻译：公开了一种用于提供和使用磁存储器的方法和系统。该方法和系统包括提供多个磁存储器单元并且提供与多个磁存储单元耦合的至少一个磁写入线。每个磁存储单元包括具有数据存储层的磁性元件。数据存储层磁性存储数据。磁写入线与至少相应磁存储器单元的磁性元件的数据存储层静磁耦合。因此，对于多个磁存储单元中的每一个的数据存储层，实质上实现了磁通闭合。

4. 发明授权

US06888192B2 Mirror image non-volatile memory cell transistor pairs with single poly layer 失效
标题翻译：镜像非易失性存储单元晶体管对与单层多层
公开(公告)号：US06888192B2
公开(公告)日：2005-05-03
申请号：US10465718
申请日：2003-06-18
申请人： Bohumil Lojek
发明人： Bohumil Lojek
IPC分类号： G11C20060101 , G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/76 , H01L29/788 , H01L29/792 , H01L39/792
CPC分类号： H01L21/28273 , G11C16/0416 , G11C2216/10 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/66825 , H01L29/7887
摘要： An arrangement of non-volatile memory transistors constructed in symmetric pairs within the space defined by intersecting pairs of word and bit lines of a memory array. The transistors have spaced apart sources and drains separated by a channel and having a floating gate over the channel characteristic of electrically erasable programmable read only memory transistors, except that there is no second poly gate. Only a single poly gate is used as a floating charge storage gate. This floating gate is placed sufficiently close to the source or drain of the device as to enable band-to-band tunneling. The floating gate is extended over the substrate to cross a word line where the floating gate is in a capacitive relation. The word line is used to program and erase the floating gate in combination with a source or drain electrode. A block erase mode is available so that the arrangement of transistors can operate as a flash memory. The single layer of poly has a T-shape, with the T-top used as the communication member with the word line and a T-base used as a floating gate. Both T-members are at the same potential. The intersecting pairs of word and bit lines resemble a tic-tac-toe pattern, with a central clear zone wherein pairs of symmetric non-volatile memory transistors are built.
摘要翻译：在由存储器阵列的字和位线的相交对限定的空间内以对称对构造的非易失性存储器晶体管的布置。晶体管具有由沟道隔开的间隔开的源极和漏极，并且在电可擦除可编程只读存储器晶体管的通道特性上具有浮置栅极，除了不存在第二多晶硅栅极。仅使用单个多晶硅栅极作为浮动电荷存储栅极。该浮置栅极被放置得足够靠近器件的源极或漏极，以实现带 - 带隧穿。浮置栅极延伸到衬底上，以跨越浮动栅极处于电容关系的字线。字线用于与源极或漏极组合编程和擦除浮动栅极。块擦除模式是可用的，使得晶体管的布置可以作为闪存存储器工作。单层Poly具有T形，T形顶部用作与字线的通信构件，并且T形底座用作浮动栅极。两个T成员都有同样的潜力。字和位线的交叉对类似于tic-tac-toe图案，具有中心清晰区域，其中构建了对对称非易失性存储器晶体管对。

5. 发明申请

US20050024928A1 Asynchronous static random access memory 有权
标题翻译：异步静态随机存取存储器
公开(公告)号：US20050024928A1
公开(公告)日：2005-02-03
申请号：US10890816
申请日：2004-07-13
申请人： Uri Cummings , Andrew Lines
发明人： Uri Cummings , Andrew Lines
IPC分类号： G11C20060101 , G11C11/00 , G11C11/413 , G11C15/00
CPC分类号： G11C11/413
摘要： A static random access memory (SRAM) is provided including a plurality of SRAM state elements and SRAM environment circuitry. The SRAM environment circuitry is operable to interface with external asynchronous circuitry and to enable reading of and writing to the SRAM state elements in a delay-insensitive manner provided that at least one timing assumption is met.
摘要翻译：提供了包括多个SRAM状态元件和SRAM环境电路的静态随机存取存储器（SRAM）。 SRAM环境电路可操作以与外部异步电路接口，并且能够以延迟不敏感的方式读取和写入SRAM状态元件，只要满足至少一个定时假设即可。

6. 发明授权

US4380804A Earom cell matrix and logic arrays with common memory gate 失效
标题翻译： Earom单元矩阵和具有公共存储器门的逻辑阵列
公开(公告)号：US4380804A
公开(公告)日：1983-04-19
申请号：US220644
申请日：1980-12-29
申请人： George C. Lockwood , Murray L. Trudel
发明人： George C. Lockwood , Murray L. Trudel
IPC分类号： G11C14/00 , G11C20060101 , G11C7/00 , G11C11/40 , G11C16/04 , G11C16/10 , G11C16/12 , G11C17/00 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792 , H03K19/177
CPC分类号： G11C16/10 , G11C16/04 , G11C16/12 , H01L29/792 , H03K19/17712
摘要： A three gate programmable memory cell comprised of a variable threshold memory element medial of two access gate elements, together forming a series path whose conductive state can be altered by any one of the series elements. Each cell has lines for individually accessing the three gate electrodes, in addition to line connections to opposite ends of the conductive path formed by the elements in series. In one form, an alterable threshold transistor is connected in series between two field effect transistors, one of the two controlling cell addressing and the other actuating the read mode. The cell is erased with a high voltage pulse on the memory line. Subsequent programming of the cell is defined by the voltage states on the word and bit lines of the addressing transistor in time coincidence with an opposite polarity, shorter duration pulse on the memory line. The logic state stored in the cell is defined by the presence or absence of a conductive path through the cell when all three gates are biased to their read mode levels. A unitary configuration of the cell includes a single substrate, with a channel defined between doped node regions. Electrically isolated gate electrodes of the three transistors are symmetrically disposed adjacent each other over the channel to control its conductivity in segments. The cells are amenable to being grouped in arrays, while retaining the independence of the high voltage memory line and the flexibility of individual row and column addresses.
摘要翻译：三门可编程存储器单元由两个存取门元件的中间的可变阈值存储元件组成，一起形成其导电状态可以由串联元件中的任何一个改变的串联路径。除了线路连接到由元件串联形成的导电路径的相对端之外，每个单元具有用于单独访问三个栅电极的线。在一种形式中，可变阈值晶体管串联连接在两个场效应晶体管之间，两个控制单元寻址之一，另一个驱动读模式。存储器线上的高电压脉冲擦除电池。单元的后续编程由寻址晶体管的字和位线上的电压状态以与相反极性的时间一致，存储线上的较短持续时间脉冲定义。当所有三个门偏置到它们的读取模式电平时，存储在单元中的逻辑状态由存在或不存在通过单元的导电路径来定义。单元的单元结构包括单个衬底，其中沟道限定在掺杂节点区域之间。三个晶体管的电隔离栅电极被对称地设置在通道上彼此相邻以控制其在段中的导电性。这些单元可以被分组成阵列，同时保持高压存储器线路的独立性以及单独的行和列地址的灵活性。

7. 发明授权

US3418644A Thin film memory 失效
标题翻译：薄膜记忆
公开(公告)号：US3418644A
公开(公告)日：1968-12-24
申请号：US37398064
申请日：1964-06-10
申请人： NCR CO
发明人： PAUL HIGASHI , GUNDERSON ROBERT O
IPC分类号： G11C11/14 , G11C20060101 , G11C7/00 , G11C11/04
CPC分类号： G11C7/00 , G11C11/04

8. 发明申请

US20050242343A1 Organic electronic circuit with functional interlayer, and method for making the same 审中-公开
标题翻译：具有功能性夹层的有机电子线路及其制造方法
公开(公告)号：US20050242343A1
公开(公告)日：2005-11-03
申请号：US11115242
申请日：2005-04-27
申请人： Niclas Edvardsson , Isak Engquist , Mats Johansson
发明人： Niclas Edvardsson , Isak Engquist , Mats Johansson
IPC分类号： G11C20060101 , G11C11/22 , H01L21/02 , H01L29/08 , H01L51/10
CPC分类号： H01L28/40 , G11C11/22
摘要： An organic electronic circuit (C) with improved performance, particularly at elevated temperatures, comprises an organic electret or ferroelectric material (2) provided between a first electrode (1a) and a second electrode (1b). A cell with a capacitor-like structure is defined in the organic electret or ferroelectric material (2) and can be accessed electrically directly or indirectly via the electrodes. At least one functional interlayer (3a; 3b) is provided between one of the electrodes (1a; 1b) and the organic electret or ferroelectric material (2). The interlayer material is inorganic, non-conducting and substantially inert relative to the organic electret or ferroelectric material (2) in general. Typically the interlayer (3) is inert relative to the organic electret or ferroelectric material (2) particularly when the latter is a fluorine-containing material. A plurality of circuits (C) is used for forming a matrix-addressable array.—The interlayer is deposited as molecular species from a source of functional interlayer material without dissociation of individual interlayer molecules.
摘要翻译：具有改进性能的有机电子电路（C），特别是在高温下，包括设置在第一电极（1a）和第二电极（1b）之间的有机驻极体或铁电材料（2）。具有电容器状结构的电池被限定在有机驻极体或铁电材料（2）中，并且可以通过电极直接或间接地访问。在一个电极（1a，1b）和有机驻极体或铁电材料（2）之间提供至少一个功能性中间层（3a; 3b）。中间层材料通常相对于有机驻极体或铁电材料（2）是无机的，不导电的和基本上是惰性的。通常，中间层（3）相对于有机驻极体或铁电材料（2）是惰性的，特别是当后者是含氟材料时。多个电路（C）用于形成矩阵寻址阵列。中间层作为分子物质从功能性中间层材料源沉积而不分离各层间分子。

9. 发明申请

US20050213391A1 Fowler-Nordheim block alterable EEPROM memory cell 有权
标题翻译： Fowler-Nordheim块可变EEPROM存储单元
公开(公告)号：US20050213391A1
公开(公告)日：2005-09-29
申请号：US11126418
申请日：2005-05-11
申请人： Bohumil Lojek
发明人： Bohumil Lojek
IPC分类号： G11C20060101 , G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L29/7883 , G11C16/0433 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/66825
摘要： A block alterable memory cell has a select control gate extending from a floating gate region to a drain region. The block alterable memory cell comprises a substrate layer that further includes a source implant region, a floating gate transistor region, and a drain implant region. A tunnel oxide layer overlies the substrate layer and is deposited to a thickness of approximately 70 angstroms. A first oxide layer overlies the tunnel oxide layer, with an inter poly layer overlying the first oxide layer, and a second poly layer extending over the floating gate transistor region to an edge of the drain implant region.
摘要翻译：块可变存储单元具有从浮置栅极区域延伸到漏极区域的选择控制栅极。块可改变存储单元包括进一步包括源注入区，浮栅晶体管区和漏注入区的衬底层。隧道氧化物层覆盖在衬底层上并沉积到大约70埃的厚度。第一氧化物层覆盖隧道氧化物层，其中覆盖第一氧化物层的多晶硅层，以及在浮置栅极晶体管区域上延伸到漏极注入区域的边缘的第二多晶硅层。

10. 发明申请

US20050174873A1 Semiconductor memory device and method of operating same 有权
公开(公告)号：US20050174873A1
公开(公告)日：2005-08-11
申请号：US11096970
申请日：2005-04-01
申请人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
发明人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
IPC分类号： G11C20060101 , G11C8/00 , G11C11/00 , G11C11/404 , G11C11/406 , G11C11/4097
CPC分类号： G11C11/404 , G11C7/18 , G11C8/08 , G11C11/406 , G11C11/40618 , G11C11/4097 , G11C2211/4016 , G11C2211/4065 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

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