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1. 发明授权

US08151085B2 Method for address translation in virtual machines 失效
标题翻译：虚拟机地址转换方法
公开(公告)号：US08151085B2
公开(公告)日：2012-04-03
申请号：US12353478
申请日：2009-01-14
申请人： Joerg Deutschle , Ute Gaertner , Erwin Pfeffer , Chung-Lung Kevin Shum , Bruce Wagar
发明人： Joerg Deutschle , Ute Gaertner , Erwin Pfeffer , Chung-Lung Kevin Shum , Bruce Wagar
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/1036 , G06F9/45558 , G06F12/0888 , G06F2009/45583
摘要： The invention relates to a method for address translation in a system running multiple levels of virtual machines containing a hierarchically organized translation lookaside buffer comprising at least two linked hierarchical sub-units, a first sub-unit comprising a lookaside buffer for some higher level address translation levels, and the second sub-unit comprising a lookaside buffer for some lower level address translation levels, and said second sub-unit being arranged to store TLB index address information of the upper level sub-unit as tag information in its lower level TLB structure, comprising the steps of collecting intermediate address translation results on different virtual machine levels; and buffering the intermediate translation results in the translation lookaside buffer.
摘要翻译：本发明涉及一种用于运行多级虚拟机的系统中的地址转换方法，该虚拟机包含分层组织的翻译后备缓冲器，其包括至少两个链接的分层子单元，第一子单元包括用于某些更高级地址转换的后备缓冲器并且第二子单元包括用于一些较低级别地址转换级别的后备缓冲器，并且所述第二子单元被布置为将上级子单元的TLB索引地址信息作为标签信息存储在其较低级别的TLB结构中包括以下步骤：在不同的虚拟机级上收集中间的地址转换结果; 并且将中间翻译结果缓冲到翻译后备缓冲器中。

2. 发明申请

US20090187731A1 Method for Address Translation in Virtual Machines 失效
标题翻译：虚拟机地址转换方法
公开(公告)号：US20090187731A1
公开(公告)日：2009-07-23
申请号：US12353478
申请日：2009-01-14
申请人： Joerg Deutschle , Ute Gaertner , Erwin Pfeffer , Chung-Lung Kevin Shum , Bruce Wagar
发明人： Joerg Deutschle , Ute Gaertner , Erwin Pfeffer , Chung-Lung Kevin Shum , Bruce Wagar
IPC分类号： G06F12/10 , G06F9/455
CPC分类号： G06F12/1036 , G06F9/45558 , G06F12/0888 , G06F2009/45583
摘要： The invention relates to a method for address translation in a system running multiple levels of virtual machines containing a hierarchically organized translation lookaside buffer comprising at least two linked hierarchical sub-units, a first sub-unit comprising a lookaside buffer for some higher level address translation levels, and the second sub-unit comprising a lookaside buffer for some lower level address translation levels, and said second sub-unit being arranged to store TLB index address information of the upper level sub-unit as tag information in its lower level TLB structure, comprising the steps of collecting intermediate address translation results on different virtual machine levels; and buffering the intermediate translation results in the translation lookaside buffer.
摘要翻译：本发明涉及一种用于运行多级虚拟机的系统中的地址转换方法，该虚拟机包含分层组织的翻译后备缓冲器，其包括至少两个链接的分层子单元，第一子单元包括用于某些更高级地址转换的后备缓冲器并且第二子单元包括用于一些较低级别地址转换级别的后备缓冲器，并且所述第二子单元被布置为将上级子单元的TLB索引地址信息作为标签信息存储在其较低级别的TLB结构中包括以下步骤：在不同的虚拟机级上收集中间的地址转换结果; 并且将中间翻译结果缓冲到翻译后备缓冲器中。

3. 发明申请

US20090216516A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR GENERATING TRACE DATA 失效
标题翻译：方法，用于生成跟踪数据的系统和计算机程序产品
公开(公告)号：US20090216516A1
公开(公告)日：2009-08-27
申请号：US12036430
申请日：2008-02-25
申请人： Debbie A. St. Onge , Jane H. Bartik , Barry W. Krumm , Erwin Pfeffer , Chung-Lung Kevin Shum
发明人： Debbie A. St. Onge , Jane H. Bartik , Barry W. Krumm , Erwin Pfeffer , Chung-Lung Kevin Shum
IPC分类号： G06F9/44
CPC分类号： G06F11/3466 , G06F11/3461 , G06F2201/885
摘要： There is provided a method, system and computer program product for generating trace data related to a data processing system event. The method includes: receiving an instruction relating to the system event from a location in the system; determining a minimum number of trace segment records required to record instruction information; and creating a trace segment table including the number of trace segment records, the number of trace segment records including at least one instruction record.
摘要翻译：提供了一种用于生成与数据处理系统事件相关的跟踪数据的方法，系统和计算机程序产品。该方法包括：从系统中的位置接收与系统事件有关的指令; 确定记录指令信息所需的跟踪段记录的最小数量; 并创建包括跟踪段记录的数量的跟踪段表，包括至少一个指令记录的跟踪段记录的数目。

4. 发明授权

US07975182B2 Method, system and computer program product for generating trace data 失效
标题翻译：用于生成跟踪数据的方法，系统和计算机程序产品
公开(公告)号：US07975182B2
公开(公告)日：2011-07-05
申请号：US12036430
申请日：2008-02-25
申请人： Debbie A. St. Onge , Jane H. Bartik , Barry W. Krumm , Erwin Pfeffer , Chung-Lung Kevin Shum
发明人： Debbie A. St. Onge , Jane H. Bartik , Barry W. Krumm , Erwin Pfeffer , Chung-Lung Kevin Shum
IPC分类号： G06F11/00
CPC分类号： G06F11/3466 , G06F11/3461 , G06F2201/885
摘要： There is provided a method, system and computer program product for generating trace data related to a data processing system event. The method includes: receiving an instruction relating to the system event from a location in the system; determining a minimum number of trace segment records required to record instruction information; and creating a trace segment table including the number of trace segment records, the number of trace segment records including at least one instruction record.
摘要翻译：提供了一种用于生成与数据处理系统事件相关的跟踪数据的方法，系统和计算机程序产品。该方法包括：从系统中的位置接收与系统事件有关的指令; 确定记录指令信息所需的跟踪段记录的最小数量; 并创建包括跟踪段记录的数量的跟踪段表，包括至少一个指令记录的跟踪段记录的数目。

5. 发明授权

US08015362B2 Method and system for handling cache coherency for self-modifying code 有权
标题翻译：用于处理缓存一致性的自修改代码的方法和系统
公开(公告)号：US08015362B2
公开(公告)日：2011-09-06
申请号：US12031923
申请日：2008-02-15
申请人： Gregory W. Alexander , Christian Jacobi , Barry W. Krumm , Chung-Lung Kevin Shum , Aaron Tsai
发明人： Gregory W. Alexander , Christian Jacobi , Barry W. Krumm , Chung-Lung Kevin Shum , Aaron Tsai
IPC分类号： G06F12/00
CPC分类号： G06F12/0848 , G06F9/3812
摘要： A method for handling cache coherency includes allocating a tag when a cache line is not exclusive in a data cache for a store operation, and sending the tag and an exclusive fetch for the line to coherency logic. An invalidation request is sent within a minimum amount of time to an I-cache, preferably only if it has fetched to the line and has not been invalidated since, which request includes an address to be invalidated, the tag, and an indicator specifying the line is for a PSC operation. The method further includes comparing the request address against stored addresses of prefetched instructions, and in response to a match, sending a match indicator and the tag to an LSU, within a maximum amount of time. The match indicator is timed, relative to exclusive data return, such that the LSU can discard prefetched instructions following execution of the store operation that stores to a line subject to an exclusive data return, and for which the match is indicated.
摘要翻译：一种用于处理高速缓存一致性的方法包括当高速缓存行在存储操作的数据高速缓存中不排斥时分配标签，以及将该标签和该行的独占提取发送到一致性逻辑。无效请求在最小时间内被发送到I缓存，优选地只有当它已经被取出到该行并且没有被无效时，因为哪个请求包括要被无效的地址，该标签和一个指示线路用于PSC操作。该方法还包括将请求地址与预取指令的存储地址进行比较，并且响应于匹配，在最大时间量内向LSU发送匹配指示符和标签。匹配指示符相对于独占数据返回是定时的，使得LSU可以执行存储操作之后丢弃预取指令，存储到受独占数据返回的行，并且指示匹配。

6. 发明授权

US07890700B2 Method, system, and computer program product for cross-invalidation handling in a multi-level private cache 失效
标题翻译：用于多级私有缓存中的交叉无效处理的方法，系统和计算机程序产品
公开(公告)号：US07890700B2
公开(公告)日：2011-02-15
申请号：US12051736
申请日：2008-03-19
申请人： Ka Shan Choy , Jennifer A. Navarro , Chung-Lung Kevin Shum , Aaron Tsai
发明人： Ka Shan Choy , Jennifer A. Navarro , Chung-Lung Kevin Shum , Aaron Tsai
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0815
摘要： A method, system, and computer program product for cross-invalidation handling in a multi-level private cache are provided. The system includes a processor. The processor includes a fetch address register logic in communication with a level 1 data cache, a level 1 instruction cache, a level 2 cache, and a higher level cache. The processor also includes a set of cross-invalidate snapshot counter implemented in the fetch address register. Each cross-invalidate snapshot counter tracks an amount of pending higher level cross-invalidations received before new data for the corresponding cache miss is returned from the higher-level cache. The processor also includes logic executing on the fetch address register for handling level 1 data cache misses and interfacing with the level 2 cache. In response to the new data, and upon determining that older cross-invalidations are pending, the new data is prevented from being used by the processor.
摘要翻译：提供了一种用于在多级私有缓存中进行交叉无效处理的方法，系统和计算机程序产品。该系统包括一个处理器。处理器包括与1级数据高速缓存，1级指令高速缓存，2级高速缓存和更高级高速缓存通信的取指地址寄存器逻辑。该处理器还包括一组在获取地址寄存器中实现的交叉无效快照计数器。每个交叉无效快照计数器跟踪在从较高级别的缓存返回相应的高速缓存未命中的新数据之前接收到的未决更高级别的交叉无效的量。该处理器还包括在取出地址寄存器上执行的逻辑，用于处理1级数据高速缓存未命中并与2级缓存进行接口。响应于新数据，并且在确定旧的交叉无效正在等待时，防止新数据被处理器使用。

7. 发明申请

US20100241899A1 Debugging for multiple errors in a microprocessor environment 有权
标题翻译：在微处理器环境中调试多个错误
公开(公告)号：US20100241899A1
公开(公告)日：2010-09-23
申请号：US12405418
申请日：2009-03-17
申请人： Ulrich Mayer , Timothy John Slegel , Chung-Lung Kevin Shum , Frank Lehnert , Guenter Gerwig
发明人： Ulrich Mayer , Timothy John Slegel , Chung-Lung Kevin Shum , Frank Lehnert , Guenter Gerwig
IPC分类号： G06F11/20 , G06F9/30
CPC分类号： G06F11/1407 , G06F9/3863 , G06F9/3865 , G06F11/0721 , G06F11/076 , G06F11/0772
摘要： A new method and apparatus have been taught for storing error information used for debugging as generated by the initial and subsequent error occurrences. In this invention, a register with several bit ranges is used to store error information. The first bit-range is allocated to the initial error information. If the total number of the errors exceeds the capacity of the register, the last error is kept in a last bit-range. This way, precious initial error information (as well as the last error information) will be available for debugging.
摘要翻译：已经教导了一种新的方法和装置，用于存储由初始和随后的错误发生产生的用于调试的错误信息。在本发明中，使用具有多个位范围的寄存器来存储错误信息。第一个比特范围被分配给初始的错误信息。如果错误总数超过寄存器的容量，则最后一个错误将保留在最后一个位范围内。这样，宝贵的初始错误信息（以及最后一个错误信息）将可用于调试。

8. 发明申请

US20090240922A1 METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND HARDWARE PRODUCT FOR IMPLEMENTING RESULT FORWARDING BETWEEN DIFFERENTLY SIZED OPERANDS IN A SUPERSCALAR PROCESSOR 失效
标题翻译：方法，系统，计算机程序产品和用于在超级处理器中执行不同尺寸操作之前的结果的硬件产品
公开(公告)号：US20090240922A1
公开(公告)日：2009-09-24
申请号：US12051792
申请日：2008-03-19
申请人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, JR. , Chung-Lung Kevin Shum , Timothy J. Slegel
发明人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, JR. , Chung-Lung Kevin Shum , Timothy J. Slegel
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30036 , G06F9/3828
摘要： Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction.
摘要翻译：通过对用于操作数转发的第一组指令进行分组，以及对用于结果转发的第二组指令进行分组，在超标量处理器中的不同大小的操作数之间提供结果和操作数转发，所述第一组指令包括具有第一操作数的第一源指令以及具有第二操作数的第一依赖指令，所述第一依赖指令取决于所述第一源指令; 所述第二组指令包括具有第三操作数和第二从属指令的第二源指令，所述第三操作数和第二从属指令具有第四操作数，所述第二依赖指令取决于所述第二源指令，通过转发所述第一操作数全部或部分地执行操作数转发，因为它在执行之前被读取到第一个依赖指令; 执行结果转发，将第二源指令的结果全部或部分转发到第二依赖指令; 其中通过与第一依赖指令一起执行第一源指令来执行操作数转发; 并且其中通过与第二从属指令一起执行第二源指令来执行结果转发。

9. 发明申请

US20090217002A1 SYSTEM AND METHOD FOR PROVIDING ASYNCHRONOUS DYNAMIC MILLICODE ENTRY PREDICTION 失效
标题翻译：用于提供异步动态MILLICODE入侵预测的系统和方法
公开(公告)号：US20090217002A1
公开(公告)日：2009-08-27
申请号：US12035109
申请日：2008-02-21
申请人： James J. Bonanno , Brian R. Prasky , John G. Rell, JR. , Anthony Saporito , Chung-Lung Kevin Shum
发明人： James J. Bonanno , Brian R. Prasky , John G. Rell, JR. , Anthony Saporito , Chung-Lung Kevin Shum
IPC分类号： G06F9/312
CPC分类号： G06F9/3017 , G06F9/30145 , G06F9/30174 , G06F9/3806
摘要： A system and method for asynchronous dynamic millicode entry prediction in a processor are provided. The system includes a branch target buffer (BTB) to hold branch information. The branch information includes: a branch type indicating that the branch represents a millicode entry (mcentry) instruction targeting a millicode subroutine, and an instruction length code (ILC) associated with the mcentry instruction. The system also includes search logic to perform a method. The method includes locating a branch address in the BTB for the mcentry instruction targeting the millicode subroutine, and determining a return address to return from the millicode subroutine as a function of the an instruction address of the mcentry instruction and the ILC. The system further includes instruction fetch controls to fetch instructions of the millicode subroutine asynchronous to the search logic. The search logic may also operate asynchronous with respect to an instruction decode unit.
摘要翻译：提供了一种用于在处理器中进行异步动态毫代码入口预测的系统和方法。该系统包括用于保存分支信息的分支目标缓冲器（BTB）。分支信息包括：分支类型，指示分支表示针对毫微米子例程的毫米条目（中心）指令，以及与中心指令相关联的指令长度代码（ILC）。该系统还包括执行方法的搜索逻辑。该方法包括将BTB中的分支地址定位到针对毫秒子程序的中心指令，以及根据中心指令和ILC的指令地址确定返回地址，以从millicode子程序返回。该系统还包括指令获取控制以获取与搜索逻辑异步的毫微数子程序的指令。搜索逻辑也可以相对于指令解码单元进行异步操作。

10. 发明申请

US20090216994A1 PROCESSOR, METHOD AND COMPUTER PROGRAM PRODUCT FOR FAST SELECTIVE INVALIDATION OF TRANSLATION LOOKASIDE BUFFER 有权
标题翻译：处理器，方法和计算机程序产品，用于快速选择性翻译翻译书写缓冲区
公开(公告)号：US20090216994A1
公开(公告)日：2009-08-27
申请号：US12036398
申请日：2008-02-25
申请人： Jonathan T. Hsieh , Chung-Lung Kevin Shum , Charles F. Webb
发明人： Jonathan T. Hsieh , Chung-Lung Kevin Shum , Charles F. Webb
IPC分类号： G06F12/10
CPC分类号： G06F12/1027
摘要： A processor including a microarchitecture adapted for invalidating mapping of at least one logical address to at least one absolute address, includes: at least one translation lookaside buffer (TLB) and a plurality of copies thereof; logic for independent indexing of each copy of the TLB; a plurality of comparators, each comparator associated with a respective output of each TLB set output for each TLB port, wherein each of the comparators is adapted for identifying mappings for invalidation; and logic for invalidating each identified mapping. A method and a computer program product are provided.
摘要翻译：一种处理器，包括适于使至少一个逻辑地址映射至少一个绝对地址无效的微体系结构，包括：至少一个翻译后备缓冲器（TLB）及其多个副本; 独立索引TLB每份副本的逻辑; 多个比较器，每个比较器与每个TLB端口的每个TLB组输出的相应输出相关联，其中每个比较器适于识别无效化的映射; 以及使每个识别的映射无效的逻辑。提供了一种方法和计算机程序产品。

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