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1. 发明授权

US09280398B2 Major branch instructions 有权
公开(公告)号：US09280398B2
公开(公告)日：2016-03-08
申请号：US13362574
申请日：2012-01-31
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F9/30 , G06F9/40 , G06F9/46 , G06F9/52 , G06F9/38 , G06F9/32
CPC分类号： G06F9/528 , G06F9/3005 , G06F9/30145 , G06F9/322 , G06F9/3804 , G06F9/3842 , G06F9/3851 , G06F9/46 , G06F9/466 , G06F9/467
摘要： Major branch instructions are provided that enable execution of a computer program to branch from one segment of code to another segment of code. These instructions also create a new stream of processing at the other segment of code enabling execution of the other segment of code to be performed in parallel with the segment of code from which the branch was taken. In one example, the other stream of processing starts a transaction for processing instructions of the other stream of processing.

2. 发明授权

US08904246B2 Variable acknowledge rate to reduce bus contention in presence of communication errors 有权
标题翻译：在存在通信错误的情况下减少总线争用的可变确认速率
公开(公告)号：US08904246B2
公开(公告)日：2014-12-02
申请号：US13458522
申请日：2012-04-27
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F11/00
CPC分类号： H04L1/08 , H04L1/1864 , H04L2001/0094
摘要： A variable write back indicator control is provided to control the amount of data to be re-transmitted when a packet error occurs. A hardware controller obtains an indication that an acknowledge rate or an amount of set write back indicators of a data frame is to be adjusted. The indication is based on an error rate of data transmission over a communication bus. Based on obtaining the indication that the amount of set write back indicators is to be adjusted, one or more write back indicators are adjusted.
摘要翻译：提供可变写回指示器控件来控制发生数据包错误时要重新发送的数据量。硬件控制器获得要调整数据帧的确认速率或设置回写指示符量的指示。该指示基于通过通信总线的数据传输的错误率。基于获取设定回写指示器的数量的指示，调整一个或多个回写指示符。

3. 发明授权

US08904100B2 Process identifier-based cache data transfer 有权
标题翻译：基于进程标识符的缓存数据传输
公开(公告)号：US08904100B2
公开(公告)日：2014-12-02
申请号：US13493636
申请日：2012-06-11
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F12/02
CPC分类号： G06F17/30982 , G06F12/0817 , G06F12/12
摘要： Embodiments of the invention relate to process identifier (PID) based cache information transfer. An aspect of the invention includes sending, by a first core of a processor, a PID associated with a cache miss in a first local cache of the first core to a second cache of the processor. Another aspect of the invention includes determining that the PID associated with the cache miss is listed in a PID table of the second cache. Yet another aspect of the invention includes based on the PID being listed in the PID table of the second cache, determining a plurality of entries in a cache directory of the second cache that are associated with the PID. Yet another aspect of the invention includes pushing cache information associated with each of the determined plurality of entries in the cache directory from the second cache to the first local cache.
摘要翻译：本发明的实施例涉及基于过程标识符（PID）的高速缓存信息传送。本发明的一个方面包括由处理器的第一核心将与第一核心的第一本地高速缓存中的高速缓存未命中相关联的PID发送到处理器的第二高速缓存。本发明的另一方面包括确定与高速缓存未命中相关联的PID被列在第二高速缓存的PID表中。本发明的另一方面包括基于PID列在第二高速缓存的PID表中，确定与PID相关联的第二高速缓存的高速缓存目录中的多个条目。本发明的另一方面包括将高速缓存目录中的确定的多个条目中的每一个相关联的缓存信息从第二高速缓存推送到第一本地高速缓存。

4. 发明申请

US20130290802A1 VARIABLE ACKNOWLEDGE RATE TO REDUCE BUS CONTENTION IN PRESENCE OF COMMUNICATION ERRORS 有权
标题翻译：在通信错误存在的情况下，可降低总线容量的可变确认值
公开(公告)号：US20130290802A1
公开(公告)日：2013-10-31
申请号：US13458522
申请日：2012-04-27
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： H03M13/00 , G06F11/08
CPC分类号： H04L1/08 , H04L1/1864 , H04L2001/0094
摘要： A variable write back indicator control is provided to control the amount of data to be re-transmitted when a packet error occurs. A hardware controller obtains an indication that an acknowledge rate or an amount of set write back indicators of a data frame is to be adjusted. The indication is based on an error rate of data transmission over a communication bus. Based on obtaining the indication that the amount of set write back indicators is to be adjusted, one or more write back indicators are adjusted.
摘要翻译：提供可变写回指示器控件来控制发生数据包错误时要重新发送的数据量。硬件控制器获得要调整数据帧的确认速率或设置回写指示符量的指示。该指示基于通过通信总线的数据传输的错误率。基于获取设定回写指示器的数量的指示，调整一个或多个回写指示符。

5. 发明授权

US08090933B2 Methods computer program products and systems for unifying program event recording for branches and stores in the same dataflow 有权
标题翻译：方法计算机程序产品和系统，用于在同一数据流中统一分支和存储的程序事件记录
公开(公告)号：US08090933B2
公开(公告)日：2012-01-03
申请号：US12029696
申请日：2008-02-12
申请人： Fadi Y. Busaba , Bruce C. Giamei
发明人： Fadi Y. Busaba , Bruce C. Giamei
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/322 , G06F9/30043 , G06F9/3005
摘要： The present invention relates to a method for the unification of PER branch and PER store operations within the same dataflow. The method comprises determining a PER range, the PER range comprising a storage area defined by a designated storage starting area and a designated storage ending area, wherein the storage starting area is designated by a value of the contents of a first control register and the storage ending area is designated by a value of the contents of a second control register. The method also comprises retrieving register field content values that are stored at a plurality of registers, wherein the retrieved content values comprises a length field content value, and setting the length field content value to zero for a PER branch instruction, thereby enabling a PER branch instruction to performed similarly to a PER storage instruction.
摘要翻译：本发明涉及在同一数据流内统一PER分支和PER存储操作的方法。该方法包括：确定PER范围，所述PER范围包括由指定的存储开始区域和指定的存储结束区域定义的存储区域，其中所述存储起始区域由第一控制寄存器的内容的值指定，结束区域由第二控制寄存器的内容的值指定。该方法还包括检索存储在多个寄存器中的寄存器字段内容值，其中所检索的内容值包括长度字段内容值，并且对于PER分支指令将长度字段内容值设置为零，从而使得PER分支执行与PER存储指令类似的指令。

6. 发明授权

US08078843B2 Facilitating processing in a computing environment using an extended drain instruction 有权
标题翻译：在计算环境中利用扩展的漏极指令促进处理
公开(公告)号：US08078843B2
公开(公告)日：2011-12-13
申请号：US12023155
申请日：2008-01-31
申请人： Khary J. Alexander , Fadi Y. Busaba , Mark S. Farrell , Bruce C. Giamei , Timothy J. Slegel , Charles F. Webb
发明人： Khary J. Alexander , Fadi Y. Busaba , Mark S. Farrell , Bruce C. Giamei , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F9/30
CPC分类号： G06F9/30079 , G06F9/30145 , G06F9/3867
摘要： An extended DRAIN instruction is used to stall processing within a computing environment. The instruction includes an indication of the one or more processing stages at which processing is to be stalled. It also includes a control that allows processing to be stalled for additional cycles, as desired. The enhanced DRAIN instruction enables its use to be more granular and to have minimal impact with respect to each individual use.
摘要翻译：扩展DRAIN指令用于在计算环境中停止处理。该指令包括处理被停止的一个或多个处理阶段的指示。它还包括一个控制，允许根据需要使处理停滞在额外的周期。增强的DRAIN指令使其使用更细致，对每个用户的影响最小。

7. 发明申请

US20090240922A1 METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND HARDWARE PRODUCT FOR IMPLEMENTING RESULT FORWARDING BETWEEN DIFFERENTLY SIZED OPERANDS IN A SUPERSCALAR PROCESSOR 失效
标题翻译：方法，系统，计算机程序产品和用于在超级处理器中执行不同尺寸操作之前的结果的硬件产品
公开(公告)号：US20090240922A1
公开(公告)日：2009-09-24
申请号：US12051792
申请日：2008-03-19
申请人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, JR. , Chung-Lung Kevin Shum , Timothy J. Slegel
发明人： David S. Hutton , Fadi Y. Busaba , Bruce C. Giamei , Christopher A. Krygowski , Edward T. Malley , Jeffrey S. Plate , John G. Rell, JR. , Chung-Lung Kevin Shum , Timothy J. Slegel
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30036 , G06F9/3828
摘要： Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction.
摘要翻译：通过对用于操作数转发的第一组指令进行分组，以及对用于结果转发的第二组指令进行分组，在超标量处理器中的不同大小的操作数之间提供结果和操作数转发，所述第一组指令包括具有第一操作数的第一源指令以及具有第二操作数的第一依赖指令，所述第一依赖指令取决于所述第一源指令; 所述第二组指令包括具有第三操作数和第二从属指令的第二源指令，所述第三操作数和第二从属指令具有第四操作数，所述第二依赖指令取决于所述第二源指令，通过转发所述第一操作数全部或部分地执行操作数转发，因为它在执行之前被读取到第一个依赖指令; 执行结果转发，将第二源指令的结果全部或部分转发到第二依赖指令; 其中通过与第一依赖指令一起执行第一源指令来执行操作数转发; 并且其中通过与第二从属指令一起执行第二源指令来执行结果转发。

8. 发明申请

US20090240921A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR SUPPORTING PARTIAL RECYCLE IN A PIPELINED MICROPROCESSOR 有权
标题翻译：用于支持管道微处理器部分回收的方法，系统和计算机程序产品
公开(公告)号：US20090240921A1
公开(公告)日：2009-09-24
申请号：US12051486
申请日：2008-03-19
申请人： Khary J. Alexander , Michael Billeci , Fadi Y. Busaba , Bruce C. Giamei
发明人： Khary J. Alexander , Michael Billeci , Fadi Y. Busaba , Bruce C. Giamei
IPC分类号： G06F9/30
CPC分类号： G06F9/3865 , G06F9/3836 , G06F9/3842
摘要： A computer processing system is provided. The computer processing system includes a first datastore that stores a subset of information associated with an instruction. A first stage of a processor pipeline writes the subset of information to the first datastore based on an execution of an operation associated with the instruction. A second stage of the pipeline initiates reprocessing of the operation associated with the instruction based on the subset of information stored in the first datastore.
摘要翻译：提供了一种计算机处理系统。计算机处理系统包括存储与指令相关联的信息的子集的第一数据存储区。处理器流水线的第一阶段基于与指令相关联的操作的执行将信息子集写入第一数据存储区。管道的第二阶段基于存储在第一数据存储区中的信息子集来启动与指令相关联的操作的再处理。

9. 发明申请

US20090210775A1 METHOD AND SYSTEM FOR INSTRUCTION ADDRESS PARITY COMPARISON 有权
标题翻译：方法和系统的指令地址的比较
公开(公告)号：US20090210775A1
公开(公告)日：2009-08-20
申请号：US12031732
申请日：2008-02-15
申请人： Fadi Y. Busaba , Brian R. Prasky , Chung-Lung Kevin Shum
发明人： Fadi Y. Busaba , Brian R. Prasky , Chung-Lung Kevin Shum
IPC分类号： G06F11/00
CPC分类号： G06F11/10
摘要： A method and system for instruction address parity comparison are provided. The method includes calculating an instruction address parity value for an instruction, and distributing the instruction address parity value to one or more functional units in processing circuitry. The method also includes receiving the distributed instruction address parity value from the one or more functional units, and calculating a completing instruction address (CIA) parity value associated with completing the instruction. The method further includes generating an error indicator in response to a mismatch between the received instruction address parity value and the CIA parity value.
摘要翻译：提供了一种用于指令地址奇偶校验比较的方法和系统。该方法包括计算指令的指令地址奇偶校验值，并将指令地址奇偶校验值分配给处理电路中的一个或多个功能单元。该方法还包括从一个或多个功能单元接收分布式指令地址奇偶校验值，以及计算与完成指令相关联的完成指令地址（CIA）奇偶校验值。该方法还包括响应于接收到的指令地址奇偶校验值和CIA奇偶校验值之间的不匹配而产生错误指示符。

10. 发明申请

US20080162618A1 METHOD AND SYSTEM FOR CHECKING ROTATE, SHIFT AND SIGN EXTENSION FUNCTIONS USING A MODULO FUNCTION 失效
标题翻译：使用模块函数检查旋转，移位和符号扩展函数的方法和系统
公开(公告)号：US20080162618A1
公开(公告)日：2008-07-03
申请号：US12047525
申请日：2008-03-13
申请人： FADI Y. BUSABA , Lawrence Joseph Powell , Martin Stanley Schmookler , Michael Thomas Vaden , David Allan Webber
发明人： FADI Y. BUSABA , Lawrence Joseph Powell , Martin Stanley Schmookler , Michael Thomas Vaden , David Allan Webber
IPC分类号： G06F11/20
CPC分类号： G06F11/2226
摘要： A method of discovering a fault in a circuit is disclosed. The method comprises generating a first result of a selected function by performing the selected function on an operand, wherein the selected function employs a mask. Once the function is performed, an antimask of the mask is created, and the modulo of the antimask is calculated. A modulo function of the first result of the selected function is calculated to obtain a third result. A modulo of the operand is then calculated to obtain a fourth result, and a second function is then performed on the second result and the third result to obtain a fifth result. In response to comparing the fifth result to the fourth result, a signal is propagated to indicate a fault in the circuit.
摘要翻译：公开了一种发现电路故障的方法。该方法包括通过在操作数上执行所选功能来产生所选功能的第一结果，其中所选功能采用掩码。一旦执行了该功能，就产生一个掩模的防范，并计算出锑的模数。计算所选函数的第一结果的模函数以获得第三结果。然后计算操作数的模以获得第四结果，然后对第二结果和第三结果执行第二函数以获得第五结果。响应于将第五结果与第四结果进行比较，传播信号以指示电路中的故障。

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