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1. 发明申请

US20090216994A1 PROCESSOR, METHOD AND COMPUTER PROGRAM PRODUCT FOR FAST SELECTIVE INVALIDATION OF TRANSLATION LOOKASIDE BUFFER 有权
标题翻译：处理器，方法和计算机程序产品，用于快速选择性翻译翻译书写缓冲区
公开(公告)号：US20090216994A1
公开(公告)日：2009-08-27
申请号：US12036398
申请日：2008-02-25
申请人： Jonathan T. Hsieh , Chung-Lung Kevin Shum , Charles F. Webb
发明人： Jonathan T. Hsieh , Chung-Lung Kevin Shum , Charles F. Webb
IPC分类号： G06F12/10
CPC分类号： G06F12/1027
摘要： A processor including a microarchitecture adapted for invalidating mapping of at least one logical address to at least one absolute address, includes: at least one translation lookaside buffer (TLB) and a plurality of copies thereof; logic for independent indexing of each copy of the TLB; a plurality of comparators, each comparator associated with a respective output of each TLB set output for each TLB port, wherein each of the comparators is adapted for identifying mappings for invalidation; and logic for invalidating each identified mapping. A method and a computer program product are provided.
摘要翻译：一种处理器，包括适于使至少一个逻辑地址映射至少一个绝对地址无效的微体系结构，包括：至少一个翻译后备缓冲器（TLB）及其多个副本; 独立索引TLB每份副本的逻辑; 多个比较器，每个比较器与每个TLB端口的每个TLB组输出的相应输出相关联，其中每个比较器适于识别无效化的映射; 以及使每个识别的映射无效的逻辑。提供了一种方法和计算机程序产品。

2. 发明授权

US08112174B2 Processor, method and computer program product for fast selective invalidation of translation lookaside buffer 有权
标题翻译：处理器，方法和计算机程序产品，用于快速选择性地无效翻译后备缓冲区
公开(公告)号：US08112174B2
公开(公告)日：2012-02-07
申请号：US12036398
申请日：2008-02-25
申请人： Jonathan T. Hsieh , Chung-Lung Kevin Shum , Charles F. Webb
发明人： Jonathan T. Hsieh , Chung-Lung Kevin Shum , Charles F. Webb
IPC分类号： G06F12/10
CPC分类号： G06F12/1027
摘要： A processor including a microarchitecture adapted for invalidating mapping of at least one logical address to at least one absolute address, includes: at least one translation lookaside buffer (TLB) and a plurality of copies thereof; logic for independent indexing of each copy of the TLB; a plurality of comparators, each comparator associated with a respective output of each TLB set output for each TLB port, wherein each of the comparators is adapted for identifying mappings for invalidation; and logic for invalidating each identified mapping. A method and a computer program product are provided.
摘要翻译：一种处理器，包括适于使至少一个逻辑地址映射至少一个绝对地址无效的微体系结构，包括：至少一个翻译后备缓冲器（TLB）及其多个副本; 独立索引TLB每份副本的逻辑; 多个比较器，每个比较器与每个TLB端口的每个TLB组输出的相应输出相关联，其中每个比较器适于识别无效化的映射; 以及使每个识别的映射无效的逻辑。提供了一种方法和计算机程序产品。

3. 发明授权

US09250913B2 Collision-based alternate hashing 有权
标题翻译：基于碰撞的交替散列
公开(公告)号：US09250913B2
公开(公告)日：2016-02-02
申请号：US13524139
申请日：2012-06-15
申请人： Khary J. Alexander , Ilia Averbouch , Ariel J. Birnbaum , Jonathan T. Hsieh , Chung-Lung K. Shum
发明人： Khary J. Alexander , Ilia Averbouch , Ariel J. Birnbaum , Jonathan T. Hsieh , Chung-Lung K. Shum
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3804 , G06F9/3808 , G06F9/3814
摘要： Embodiments relate to collision-based alternate hashing. An aspect includes receiving an incoming instruction address. Another aspect includes determining whether an entry for the incoming instruction address exists in a history table based on a hash of the incoming instruction address. Another aspect includes based on determining that the entry for the incoming instruction address exists in the history table, determining whether the incoming instruction address matches an address tag in the determined entry. Another aspect includes based on determining that the incoming instruction address does not match the address tag in the determined entry, determining whether a collision exists for the incoming instruction address. Another aspect includes based on determining that the collision exists for the incoming instruction address, activating alternate hashing for the incoming instruction address using an alternate hash buffer.
摘要翻译：实施例涉及基于冲突的交替散列。一方面包括接收输入指令地址。另一方面包括基于输入指令地址的散列来确定历史表中是否存在输入指令地址的条目。另一方面包括基于确定输入指令地址的条目存在于历史表中，确定输入指令地址是否匹配所确定条目中的地址标签。另一方面包括基于确定输入指令地址与所确定的条目中的地址标签不匹配，确定对于输入指令地址是否存在冲突。另一方面包括基于确定对于输入指令地址存在冲突，使用替代散列缓冲器激活输入指令地址的替换散列。

4. 发明授权

US09015419B2 Avoiding aborts due to associativity conflicts in a transactional environment 有权
标题翻译：避免由于交易环境中的联系冲突而中断
公开(公告)号：US09015419B2
公开(公告)日：2015-04-21
申请号：US13524378
申请日：2012-06-15
申请人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi
发明人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi
IPC分类号： G06F12/00 , G06F9/46 , G06F12/08
CPC分类号： G06F12/0804 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/467
摘要： Embodiments relate to a transactional read footprint after a cache line eviction. An aspect includes executing one or more read instructions in an active transaction. A cross invalidate (XI) request for a target cache line is received, and it is determined if the target cache line is part of a congruence class in a local cache. It is further determined whether an extension flag associated with the congruence class is set. The extension flag is used to indicate that cache lines of the congruence class associated with the active transaction have been replaced based only on being least recently used and that the target cache line is not in the cache. Execution of the active transaction continues based on determining that the extension flag is not set. Execution of the active transaction is aborted based on determining that the extension flag is set.
摘要翻译：实施例涉及缓存线驱逐之后的事务读取占用空间。一个方面包括在活动事务中执行一个或多个读取指令。接收对目标高速缓存行的交叉无效（XI）请求，并且确定目标高速缓存行是否是本地高速缓存中的同余类的一部分。进一步确定是否设置与同余类相关联的扩展标志。扩展标志用于指示仅基于最近最少使用的并且目标高速缓存行不在高速缓存中，与活动事务相关联的一致类的高速缓存行已被替换。基于确定扩展标志未设置，继续执行活动事务。基于确定扩展标志被设置，中止活动事务的执行。

5. 发明申请

US20130339650A1 PREFETCH ADDRESS TRANSLATION USING PREFETCH BUFFER 有权
标题翻译：使用PREFETCH BUFFER的前缀地址翻译
公开(公告)号：US20130339650A1
公开(公告)日：2013-12-19
申请号：US13523919
申请日：2012-06-15
申请人： Khary J. Alexander , Ilia Averbouch , Ariel J. Birnbaum , Jonathan T. Hsieh , Christian Jacobi , Shmuel Paycher , Chung-Lung K. Shum
发明人： Khary J. Alexander , Ilia Averbouch , Ariel J. Birnbaum , Jonathan T. Hsieh , Christian Jacobi , Shmuel Paycher , Chung-Lung K. Shum
IPC分类号： G06F12/10
CPC分类号： G06F12/0862 , G06F12/1009
摘要： Embodiments relate to prefetch address translation in a computer processor. An aspect includes issuing, by prefetch logic, a prefetch request comprising a virtual page address. Another aspect includes, based on the prefetch request missing the TLB and the address translation logic of the processor being busy performing a current translation request, comparing a page of the prefetch request to a page of the current translation request. Yet another aspect includes, based on the page of the prefetch request matching the page of the current translation request, storing the prefetch request in a prefetch buffer.
摘要翻译：实施例涉及计算机处理器中的预取地址转换。一方面包括通过预取逻辑发出包括虚拟页面地址的预取请求。另一方面包括：基于预取请求，丢失TLB，处理器的地址转换逻辑正在执行当前转换请求，将预取请求的页面与当前转换请求的页面进行比较。另一方面包括：基于与当前转换请求的页面匹配的预取请求的页面，将预取请求存储在预取缓冲器中。

6. 发明授权

US09218288B2 Monitoring a value in storage without repeated storage access 有权
标题翻译：在不重复存储访问的情况下监视存储中的值
公开(公告)号：US09218288B2
公开(公告)日：2015-12-22
申请号：US13524063
申请日：2012-06-15
申请人： Khary J. Alexander , Ute Gaertner , Jonathan T. Hsieh , Christian Jacobi , Timothy J. Slegel
发明人： Khary J. Alexander , Ute Gaertner , Jonathan T. Hsieh , Christian Jacobi , Timothy J. Slegel
IPC分类号： G06F12/02 , G06F12/08 , G06F3/06
CPC分类号： G06F12/0808 , G06F3/0653 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F12/0891
摘要： A technique is provided for monitoring a value without repeated storage access. A processing circuit processes an instruction of a program that specifies a memory address of a memory location to be monitored. The processing circuit configures a monitor station for monitoring the memory location. The memory location includes a state descriptor for the program. The processing circuit receives a cross-invalidate request from a memory controller. The cross-invalidate request indicates to the monitor station that content of the memory location has been changed by another processing circuit.
摘要翻译：提供了一种用于监视值而不重复存储访问的技术。处理电路处理指定要监视的存储器位置的存储器地址的程序的指令。处理电路配置用于监视存储器位置的监视站。存储器位置包括程序的状态描述符。处理电路从存储器控制器接收到交叉无效请求。交叉无效请求向监视台指示存储器位置的内容已被另一处理电路改变。

7. 发明授权

US08954678B2 Automatic pattern-based operand prefetching 有权
标题翻译：自动基于模式的操作数预取
公开(公告)号：US08954678B2
公开(公告)日：2015-02-10
申请号：US13523922
申请日：2012-06-15
申请人： Ilia Averbouch , Ariel J. Birnbaum , Jonathan T. Hsieh , Chung-Lung K. Shum
发明人： Ilia Averbouch , Ariel J. Birnbaum , Jonathan T. Hsieh , Chung-Lung K. Shum
IPC分类号： G06F12/12
CPC分类号： G06F12/0862 , G06F2212/6024 , G06F2212/6026
摘要： Embodiments relate to automatic pattern-based operand prefetching. An aspect includes receiving, by prefetch logic in a processor, an operand cache miss from a pipeline of the processor. Another aspect includes determining that an entry in a history table corresponding to the operand cache miss exists based on an instruction address of the operand cache miss. Yet another aspect includes, based on determining that the entry corresponding to the operand cache miss exists in the history table, issuing a prefetch instruction for a second operand based on the determined entry in the history table, and writing the determined entry into a miss buffer.
摘要翻译：实施例涉及自动基于模式的操作数预取。一个方面包括通过处理器中的预取逻辑从处理器的流水线接收操作数高速缓存未命中。另一方面包括基于操作数高速缓存未命中的指令地址来确定与操作数高速缓存未命中对应的历史表中的条目。另一方面包括：基于确定对应于操作数高速缓存未命中的条目存在于历史表中，基于历史表中确定的条目发布第二操作数的预取指令，并将所确定的条目写入未命中缓冲器。

8. 发明授权

US08799583B2 Atomic execution over accesses to multiple memory locations in a multiprocessor system 有权
标题翻译：通过对多处理器系统中的多个内存位置的访问进行原子执行
公开(公告)号：US08799583B2
公开(公告)日：2014-08-05
申请号：US12786787
申请日：2010-05-25
申请人： Mark S. Farrell , Jonathan T. Hsieh , Christian Jacobi , Timothy J. Slegel
发明人： Mark S. Farrell , Jonathan T. Hsieh , Christian Jacobi , Timothy J. Slegel
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F9/30043 , G06F9/30072 , G06F9/3834 , G06F9/528 , G06F12/0815 , G06F2212/62
摘要： A method and central processing unit supporting atomic access of shared data by a sequence of memory access operations. A processor status flag is reset. A processor executes, subsequent to the setting of the processor status flag, a sequence of program instructions with instructions accessing a subset of shared data contained within its local cache. During execution of the sequence of program instructions and in response to a modification by another processor of the subset of shared data, the processor status flag is set. Subsequent to the executing the sequence of program instructions and based upon the state of the processor status flag, either a first program processing or a second program processing is executed. In some examples the first program processing includes storing results data into the local cache and the second program processing includes discarding the results data.
摘要翻译：一种通过一系列存储器访问操作支持共享数据的原子访问的方法和中央处理单元。处理器状态标志被复位。在处理器状态标志的设置之后，处理器执行具有访问包含在其本地高速缓存中的共享数据的子集的指令的程序指令序列。在程序指令序列的执行期间，并且响应于另一个处理器对共享数据子集的修改，处理器状态标志被置位。在执行程序指令序列之后，并且基于处理器状态标志的状态，执行第一程序处理或第二程序处理。在一些示例中，第一程序处理包括将结果数据存储到本地高速缓存中，并且第二程序处理包括丢弃结果数据。

9. 发明申请

US20130339628A1 DETERMINING THE LOGICAL ADDRESS OF A TRANSACTION ABORT 有权
标题翻译：确定交易的逻辑地址
公开(公告)号：US20130339628A1
公开(公告)日：2013-12-19
申请号：US13524342
申请日：2012-06-15
申请人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi
发明人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/00 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F12/08 , G06F12/0808 , G06F12/0815 , G06F12/0822 , G06F12/0831 , G06F12/0833 , G06F12/0891
摘要： Embodiments relate to determining the logical address of a transaction abort. In an embodiment, one or more instructions are received are received from an application. The one or more instructions are executed within a first transaction. The first transaction delays committing stores to memory until it has completed. At least one of the one or more instructions includes a first logical memory address. The first logical memory address corresponds to a first memory address in a memory system. It is determined if the first memory address is equal to a second memory address that is stored in a conflict register. Based on determining that they are equal the first logical memory address is saved as a logical address associated with a cross invalidate (XI) signal at a location available to the application.
摘要翻译：实施例涉及确定事务中止的逻辑地址。在一个实施例中，从应用程序接收一个或多个接收的指令。一个或多个指令在第一事务中执行。第一个交易延迟将存储提交到内存，直到它完成。所述一个或多个指令中的至少一个包括第一逻辑存储器地址。第一逻辑存储器地址对应于存储器系统中的第一存储器地址。确定第一存储器地址是否等于存储在冲突寄存器中的第二存储器地址。基于确定它们相等，第一逻辑存储器地址被保存为与应用可用的位置处的交叉无效（XI）信号相关联的逻辑地址。

10. 发明申请

US20140082252A1 Combined Two-Level Cache Directory 审中-公开
标题翻译：组合二级缓存目录
公开(公告)号：US20140082252A1
公开(公告)日：2014-03-20
申请号：US13621465
申请日：2012-09-17
申请人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi , Barry W. Krumm
发明人： Khary J. Alexander , Jonathan T. Hsieh , Christian Jacobi , Barry W. Krumm
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/0811 , G06F12/1054
摘要： Responsive to receiving a logical address for a cache access, a mechanism looks up a first portion of the logical address in a local cache directory for a local cache. The local cache directory returns a set identifier for each set in the local cache directory. Each set identifier indicates a set within a higher level cache directory. The mechanism looks up a second portion of the logical address in the higher level cache directory and compares each absolute address value received from the higher level cache directory to an absolute address received from a translation look-aside buffer to generate a higher level cache hit signal. The mechanism compares the higher level cache hit signal to each set identifier to generate a local cache hit signal and responsive to the local cache hit signal indicating a local cache hit, accesses the local cache based on the local cache hit signal.
摘要翻译：响应于接收高速缓存访问的逻辑地址，机制在本地高速缓存目录中查找本地高速缓存的逻辑地址的第一部分。本地缓存目录返回本地缓存目录中每个集合的集合标识符。每个集合标识符表示较高级别的高速缓存目录中的集合。该机制查找较高级别高速缓存目录中的逻辑地址的第二部分，并将从较高级别高速缓存目录接收的每个绝对地址值与从翻译后备缓冲器接收的绝对地址进行比较，以产生更高级别的高速缓存命中信号。该机制将高级缓存命中信号与每个集合标识符进行比较以产生本地高速缓存命中信号，并且响应于指示本地高速缓存命中的本地高速缓存命中信号，基于本地高速缓存命中信号访问本地高速缓存。

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