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1. 发明授权

US07961028B2 Single supply pass gate level converter for multiple supply voltage system 有权
标题翻译：单电源通过门电平转换器用于多电源电压系统
公开(公告)号：US07961028B2
公开(公告)日：2011-06-14
申请号：US12639188
申请日：2009-12-16
申请人： Jiyeon An , Young Hwan Kim , Hyoun Soo Park
发明人： Jiyeon An , Young Hwan Kim , Hyoun Soo Park
IPC分类号： H03L5/00
CPC分类号： H03K19/018571
摘要： The present invention relates to a level converter used in a multiple supply voltage system that is required to design a low-power and high-performance semiconductor, and more particularly, to a single supply pass gate level converter (SPLC) for a multiple supply voltage system, which has low power consumption, operates at high speed, and uses only a single supply voltage. The SPLC includes an input data providing circuit unit which receives an input signal of a low supply voltage; a data inversion circuit unit which receives input data from the input data providing circuit unit and outputs inversed input data; a feedback circuit unit which is fed back by an output of the data inversion circuit unit; and a data output buffer which inverses an output of the data inversion circuit unit and outputs an inversed signal. The input data providing circuit unit, the data inversion circuit unit, the feedback circuit unit, and the data output buffer are all driven by a high supply voltage such that only a single supply voltage which is the high supply voltage is required.
摘要翻译：本发明涉及一种用于设计低功率和高性能半导体所需的多电源电压系统中的电平转换器，更具体地说，涉及一种用于多电源电压的单电源通过门电平转换器（SPLC）系统功耗低，运行速度快，仅使用单电源电压。 SPLC包括输入数据提供电路单元，其接收低电源电压的输入信号; 数据反转电路单元，其从输入数据提供电路单元接收输入数据并输出反相输入数据; 反馈电路单元，由数据反转电路单元的输出反馈; 以及数据输出缓冲器，其反转数据反转电路单元的输出并输出反相信号。输入数据提供电路单元，数据反转电路单元，反馈电路单元和数据输出缓冲器均由高电源电压驱动，使得仅需要作为高电源电压的单个电源电压。

2. 发明申请

US20100156371A1 SINGLE SUPPLY PASS GATE LEVEL CONVERTER FOR MULTIPLE SUPPLY VOLTAGE SYSTEM 有权
标题翻译：单电源电压电平转换器多电源电压系统
公开(公告)号：US20100156371A1
公开(公告)日：2010-06-24
申请号：US12639188
申请日：2009-12-16
申请人： Jiyeon An , Young Hwan Kim , Hyoun Soo Park
发明人： Jiyeon An , Young Hwan Kim , Hyoun Soo Park
IPC分类号： G05F1/10
CPC分类号： H03K19/018571
摘要： The present invention relates to a level converter used in a multiple supply voltage system that is required to design a low-power and high-performance semiconductor, and more particularly, to a single supply pass gate level converter (SPLC) for a multiple supply voltage system, which has low power consumption, operates at high speed, and uses only a single supply voltage. The SPLC includes an input data providing circuit unit which receives an input signal of a low supply voltage; a data inversion circuit unit which receives input data from the input data providing circuit unit and outputs inversed input data; a feedback circuit unit which is fed back by an output of the data inversion circuit unit; and a data output buffer which inverses an output of the data inversion circuit unit and outputs an inversed signal. The input data providing circuit unit, the data inversion circuit unit, the feedback circuit unit, and the data output buffer are all driven by a high supply voltage such that only a single supply voltage which is the high supply voltage is required.
摘要翻译：本发明涉及一种用于设计低功率和高性能半导体所需的多电源电压系统中的电平转换器，更具体地说，涉及一种用于多电源电压的单电源通过门电平转换器（SPLC）系统功耗低，运行速度快，仅使用单电源电压。 SPLC包括输入数据提供电路单元，其接收低电源电压的输入信号; 数据反转电路单元，其从输入数据提供电路单元接收输入数据并输出反相输入数据; 反馈电路单元，由数据反转电路单元的输出反馈; 以及数据输出缓冲器，其反转数据反转电路单元的输出并输出反相信号。输入数据提供电路单元，数据反转电路单元，反馈电路单元和数据输出缓冲器均由高电源电压驱动，使得仅需要作为高电源电压的单个电源电压。

3. 发明授权

US08046724B2 Method of timing criticality calculation for statistical timing optimization of VLSI circuit 有权
标题翻译： VLSI电路统计时序优化的定时临界计算方法
公开(公告)号：US08046724B2
公开(公告)日：2011-10-25
申请号：US12474547
申请日：2009-05-29
申请人： Hyoun Soo Park , Young Hwan Kim , Dai Joon Hyun , Wook Kim
发明人： Hyoun Soo Park , Young Hwan Kim , Dai Joon Hyun , Wook Kim
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G06F17/505
摘要： Provided is a method of optimizing statistical timing of an integration circuit, the method including applying subtle changes of mean arrival times with respect to each of nodes in a timing graph of an integrated circuit to ADD operations and MAX operations of a block-based statistical static timing analysis (SSTA) method and approximating the corresponding operations; generating Jacobian matrixes between each node by using matrix components including differential coefficients calculated during linear approximation of the operations; calculating changed arrival time values of the circuit by propagating the Jacobian matrixes from a virtual sink node to a virtual source node; and calculating timing yield criticalities, which are variances of timing yield of the circuit due to subtle changes of mean arrival times with respect to each node, based on values obtained by the propagation. Accordingly, timing yield criticality is calculated based on linear approximation of ADD operations and MAX operations of statistical static timing analysis (SSTA), and thus the calculation complexity is linear with respect to the total number of nodes, and critical nodes significantly affecting the timing yield of a circuit can be extracted more accurately.
摘要翻译：提供了一种优化集成电路的统计定时的方法，该方法包括对集成电路的定时图中的每个节点应用平均到达时间的微妙变化，以ADD操作和基于块的统计静态的MAX操作时序分析（SSTA）方法和近似相应的操作; 通过使用包括在操作的线性近似期间计算的微分系数的矩阵分量来生成每个节点之间的雅可比矩阵; 通过将雅可比矩阵从虚拟汇聚节点传播到虚拟源节点来计算电路的改变的到达时间值; 以及基于通过传播获得的值，计算由于平均到达时间相对于每个节点的微妙变化而导致的电路的定时收益率的定时收益率临界。因此，基于统计静态时序分析（SSTA）的ADD操作和MAX操作的线性近似来计算定时收益关键性，因此计算复杂度相对于总节点数是线性的，关键节点显着影响定时收益可以更准确地提取电路。

4. 发明申请

US20100242006A1 METHOD OF TIMING CRITICALITY CALCULATION FOR STATISTICAL TIMING OPTIMIZATION OF VLSI CIRCUIT 有权
标题翻译：定时关键度计算方法对VLSI电路的统计时序优化
公开(公告)号：US20100242006A1
公开(公告)日：2010-09-23
申请号：US12474547
申请日：2009-05-29
申请人： Hyoun Soo Park , Young Hwan Kim , Dai Joon Hyun , Wook Kim
发明人： Hyoun Soo Park , Young Hwan Kim , Dai Joon Hyun , Wook Kim
IPC分类号： G06F17/10
CPC分类号： G06F17/5031 , G06F17/505
摘要： Provided is a method of optimizing statistical timing of an integration circuit, the method including applying subtle changes of mean arrival times with respect to each of nodes in a timing graph of an integrated circuit to ADD operations and MAX operations of a block-based statistical static timing analysis (SSTA) method and approximating the corresponding operations; generating Jacobian matrixes between each node by using matrix components including differential coefficients calculated during linear approximation of the operations; calculating changed arrival time values of the circuit by propagating the Jacobian matrixes from a virtual sink node to a virtual source node; and calculating timing yield criticalities, which are variances of timing yield of the circuit due to subtle changes of mean arrival times with respect to each node, based on values obtained by the propagation. Accordingly, timing yield criticality is calculated based on linear approximation of ADD operations and MAX operations of statistical static timing analysis (SSTA), and thus the calculation complexity is linear with respect to the total number of nodes, and critical nodes significantly affecting the timing yield of a circuit can be extracted more accurately.
摘要翻译：提供了一种优化积分电路的统计定时的方法，该方法包括对集成电路的定时图中的每个节点应用平均到达时间的微妙变化，以ADD操作和基于块的统计静态的MAX操作时序分析（SSTA）方法和近似相应的操作; 通过使用包括在操作的线性近似期间计算的微分系数的矩阵分量来生成每个节点之间的雅可比矩阵; 通过将雅可比矩阵从虚拟汇聚节点传播到虚拟源节点来计算电路的改变的到达时间值; 以及基于通过传播获得的值，计算由于平均到达时间相对于每个节点的微妙变化而导致的电路的定时收益率的定时收益率临界。因此，基于统计静态时序分析（SSTA）的ADD操作和MAX操作的线性近似来计算定时收益关键性，因此计算复杂度相对于总节点数是线性的，关键节点显着影响定时收益可以更准确地提取电路。

5. 发明授权

US07987439B2 Method and apparatus for analyzing circuit model by reduction and computer program product for analyzing the circuit model 有权
标题翻译：用于分析电路模型的方法和装置以及用于分析电路模型的计算机程序产品
公开(公告)号：US07987439B2
公开(公告)日：2011-07-26
申请号：US12027732
申请日：2008-02-07
申请人： Hong Bo Che , Young Hwan Kim
发明人： Hong Bo Che , Young Hwan Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/78
摘要： Provided are a method and apparatus for analyzing a circuit model by reducing, and a computer program product for analyzing the circuit model. The circuit model at least includes independent current source models, resistance models, and capacitance models. Also, the circuit model forms a resistance capacitance (RC) network with independent current sources. The method includes selecting a node to be removed using resistance information and comparing conductance of a capacitor for a given time step and the total conductance of the node. Further, the method includes removing the selected nodes and generating RC elements and independent current sources using adjacent nodes, which maintain the accuracy of node voltages of a circuit reduced in an accuracy order used for entrywise perturbation of the corresponding circuit equation. Moreover, an efficient method of handling the independent current sources while reducing the circuit is provided.
摘要翻译：提供了一种通过减少电路模型分析的方法和装置，以及用于分析电路模型的计算机程序产品。电路模型至少包括独立的电流源模型，电阻模型和电容模型。此外，电路模型形成具有独立电流源的电阻电容（RC）网络。该方法包括使用电阻信息来选择要去除的节点，并且比较给定时间步长的电容器的电导率和节点的总电导率。此外，该方法包括使用相邻节点去除所选择的节点并产生RC元件和独立电流源，其保持电路的节点电压的精度以用于相应电路方程的入门扰动的精度顺序降低。此外，提供了一种在减少电路的同时处理独立电流源的有效方法。

6. 发明申请

US20100299114A1 METHOD OF CALCULATING GATE DELAY BASED ON CROSSTALK EFFECT DUE TO CAPACITIVE COUPLING 有权
标题翻译：基于电容耦合的波形效应计算门延迟的方法
公开(公告)号：US20100299114A1
公开(公告)日：2010-11-25
申请号：US12475544
申请日：2009-05-31
申请人： Tae Il Bae , Young Hwan Kim , Jinwook Kim
发明人： Tae Il Bae , Young Hwan Kim , Jinwook Kim
IPC分类号： G06F17/10
CPC分类号： G06F17/5022 , G06F17/5036
摘要： Provided is a method of exactly calculating the delay of a gate in a digital integrated circuit (IC) that drives a capacitive load and a noise current source based on a crosstalk effect due to capacitive coupling between adjacent conductive lines, the method calculates the delay of the gate by using an output waveform that sums an output waveform of a linear time-varying output resistance model generated by using a gate output resistance library generated by using input and output voltage values of the digital IC and an output waveform of a modified Thevenin equivalent model of the gate.
摘要翻译：提供了一种精确计算由于相邻导线之间的电容耦合引起的串扰效应驱动容性负载和噪声电流源的数字集成电路（IC）中的栅极的延迟的方法，该方法计算延迟通过使用将通过使用通过使用数字IC的输入和输出电压值产生的栅极输出电阻库生成的线性时变输出电阻模型的输出波形和修改的戴维南当量的输出波形相加的输出波形的门门的模型。

7. 发明授权

US06954985B2 Method for plugging holes in a printed circuit board 失效
标题翻译：堵塞印刷电路板上的孔的方法
公开(公告)号：US06954985B2
公开(公告)日：2005-10-18
申请号：US10043146
申请日：2002-01-14
申请人： Sung Gue Lee , Sung Sik Cho , Yong Il Kim , Yong Soon Jang , Ho Sung Choi , Sang Jin Kong , Young Hwan Kim
发明人： Sung Gue Lee , Sung Sik Cho , Yong Il Kim , Yong Soon Jang , Ho Sung Choi , Sang Jin Kong , Young Hwan Kim
IPC分类号： H05K3/28 , H05K3/00 , H05K3/12 , H05K3/42 , H05K3/46 , H01K3/10
CPC分类号： H05K3/0094 , H05K3/1225 , H05K3/28 , H05K2201/09509 , H05K2201/0959 , H05K2201/09881 , H05K2203/0278 , H05K2203/0557 , Y10T29/49117 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/49135 , Y10T29/49144 , Y10T29/49155 , Y10T29/49165 , Y10T29/49167
摘要： A hole plugging method for a printed circuit board, a hole plugging device in accordance therewith and a manufacturing method in accordance therewith where a mask for selectively exposing a via hole, a through hole and a surface pattern of the printed circuit board is positioned on the board having the via hole and the through hole to electrically connect circuit patterns formed on the surface of the board and in the board and an insulating material is plugged in the via hole by abutting and pushing the material on the surface of the board. Therefore, the insulating material can be plugged smoothly without a void, the processing is simplified by plugging the insulating material just to the height of the circuit pattern in a space between the circuit patterns and accordingly, damage to the circuit pattern can be prevented.
摘要翻译：用于印刷电路板的孔堵塞方法，根据本发明的孔堵装置及其制造方法，其中用于选择性地暴露印刷电路板的通孔，通孔和表面图案的掩模位于具有通孔和通孔的电路板电连接板和表面上形成的电路图案和绝缘材料，通过邻接和推动板的表面上的材料而被堵塞在通孔中。因此，绝缘材料可以没有空隙而平滑地插入，通过将绝缘材料刚好插入电路图案之间的空间中的电路图案的高度来简化处理，因此可以防止电路图案的损坏。

8. 发明授权

US06880103B2 Method and apparatus for radio packet data transmission 失效
标题翻译：用于无线电分组数据传输的方法和装置
公开(公告)号：US06880103B2
公开(公告)日：2005-04-12
申请号：US09986415
申请日：2001-11-08
申请人： Young Hwan Kim , Doo Young Moon , Kyung Kuk Lee
发明人： Young Hwan Kim , Doo Young Moon , Kyung Kuk Lee
IPC分类号： H04L12/56 , H04L1/18 , G06F11/00
CPC分类号： H04L1/1887
摘要： A method and device for communicating data within a packet frame unit between a terminal and a base station are disclosed. The terminal communicates the packet data to the base station. In response, the base station transmits a channel occupying signal, if the data transmission from the terminal is perceived by the base station. The terminal continues the communication of the packet data, while the channel occupying signal is active, determines whether the base station receives the communicated packet data, and ends the process for communicating the packet data if the base station receives the communicated packet data. If the base station fails to receive the communicated packet data, the terminal is informed through the channel occupying signal. Thereafter, the terminal discontinues its communication and then re-attempts to communicate the packet data from the beginning.
摘要翻译：公开了一种用于在终端和基站之间的分组帧单元内传送数据的方法和装置。终端将分组数据传送到基站。作为响应，如果来自终端的数据传输被基站感知，则基站发送信道占用信号。终端继续通信分组数据，而信道占用信号是活动的，确定基站是否接收所传送的分组数据，并且如果基站接收到传送的分组数据，则结束传送分组数据的处理。如果基站未能接收所传送的分组数据，则通过信道占用信号通知终端。此后，终端终止其通信，然后从一开始重新尝试传送分组数据。

9. 发明授权

US5770675A Cyclic oligomers comprising m-phenylene isophthalamide and polymers thereof 失效
标题翻译：包含间苯二甲酰间苯二胺的环状低聚物及其聚合物
公开(公告)号：US5770675A
公开(公告)日：1998-06-23
申请号：US664898
申请日：1996-06-18
申请人： Young Hwan Kim , Wesley Memeger, Jr.
发明人： Young Hwan Kim , Wesley Memeger, Jr.
IPC分类号： C07D259/00 , C07F3/00 , C07F15/02 , C08G69/32 , C08G73/00
CPC分类号： C07F3/003 , C07D259/00 , C07F15/025 , C08G69/32
摘要： Disclosed herein are cyclic oligomers comprising substituted or unsubstituted m-phenylene isophthalamide, complexes of these oligomers with selected metal salts, novel methods for their preparation, and polymerization of the cyclic oligomers to linear aramids. The aramids are useful, for example, as fibers for fire resistant clothing. Amino-finctional cyclic oligomers may be reacted with polyfunctional acyl halides to produce polyamides.
摘要翻译：本文公开了包含取代或未取代的间亚苯基间苯二甲酰胺的环状低聚物，这些低聚物与选择的金属盐的络合物，其制备方法和环状低聚物聚合成直链芳族聚酰胺。芳族聚酰胺是有用的，例如，作为防火服装的纤维。氨基官能的环状低聚物可以与多官能酰基卤反应生成聚酰胺。

10. 发明授权

US09193900B2 Optoelectronic device and stacking structure 有权
标题翻译：光电器件和堆叠结构
公开(公告)号：US09193900B2
公开(公告)日：2015-11-24
申请号：US13467763
申请日：2012-05-09
申请人： Hyun A Kang , Young Hwan Kim , Eun Joo Jang , Shin Ae Jun , Hyo Sook Jang
发明人： Hyun A Kang , Young Hwan Kim , Eun Joo Jang , Shin Ae Jun , Hyo Sook Jang
IPC分类号： H01L51/54 , C09K11/02 , H01L33/44
CPC分类号： C09K11/02 , C09K11/883 , H01L33/44 , H01L2224/14 , H01L2224/16145 , H01L2224/48091 , H01L2924/00014
摘要： Provided is an optoelectronic device that includes: a light source; an emission layer disposed on the light source and including light emitting particles dispersed in a matrix polymer; and a polymer film disposed on the emission layer. The polymer film includes two layers: a first layer including a first polymer and a second layer including a second polymer. The first polymer includes a polymerized product of a first monomer including at least two thiol (—SH) groups and a siloxane-based second monomer or oligomer including at least one carbon-carbon unsaturated bond at a terminal end, and the second polymer includes a polymerized product of a third monomer including at least two thiol (—SH) groups and a fourth monomer including at least two carbon-carbon unsaturated bonds at a terminal end.
摘要翻译：提供了一种光电子器件，其包括：光源; 发光层，其设置在所述光源上，并且包含分散在基质聚合物中的发光粒子; 以及设置在发光层上的聚合物膜。聚合物膜包括两层：包含第一聚合物的第一层和包含第二聚合物的第二层。第一聚合物包括包含至少两个硫醇（-SH）基团的第一单体和在末端包含至少一个碳 - 碳不饱和键的硅氧烷基第二单体或低聚物的聚合产物，第二聚合物包括包含至少两个硫醇（-SH）基团的第三单体和在末端包含至少两个碳 - 碳不饱和键的第四单体的聚合产物。

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