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1. 发明申请

US20100299114A1 METHOD OF CALCULATING GATE DELAY BASED ON CROSSTALK EFFECT DUE TO CAPACITIVE COUPLING 有权
标题翻译：基于电容耦合的波形效应计算门延迟的方法
公开(公告)号：US20100299114A1
公开(公告)日：2010-11-25
申请号：US12475544
申请日：2009-05-31
申请人： Tae Il Bae , Young Hwan Kim , Jinwook Kim
发明人： Tae Il Bae , Young Hwan Kim , Jinwook Kim
IPC分类号： G06F17/10
CPC分类号： G06F17/5022 , G06F17/5036
摘要： Provided is a method of exactly calculating the delay of a gate in a digital integrated circuit (IC) that drives a capacitive load and a noise current source based on a crosstalk effect due to capacitive coupling between adjacent conductive lines, the method calculates the delay of the gate by using an output waveform that sums an output waveform of a linear time-varying output resistance model generated by using a gate output resistance library generated by using input and output voltage values of the digital IC and an output waveform of a modified Thevenin equivalent model of the gate.
摘要翻译：提供了一种精确计算由于相邻导线之间的电容耦合引起的串扰效应驱动容性负载和噪声电流源的数字集成电路（IC）中的栅极的延迟的方法，该方法计算延迟通过使用将通过使用通过使用数字IC的输入和输出电压值产生的栅极输出电阻库生成的线性时变输出电阻模型的输出波形和修改的戴维南当量的输出波形相加的输出波形的门门的模型。

2. 发明授权

US08046725B2 Method of incremental statistical static timing analysis based on timing yield 有权
标题翻译：基于定时收益的增量统计静态时序分析方法
公开(公告)号：US08046725B2
公开(公告)日：2011-10-25
申请号：US12475545
申请日：2009-05-31
申请人： Jinwook Kim , Young Hwan Kim , Wook Kim
发明人： Jinwook Kim , Young Hwan Kim , Wook Kim
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： Provided is a method of incremental SSTA (statistical static timing analysis) of a digital circuit, the method including a first step in which, when a gate is replaced in the digital circuit, delay propagation is performed from a node of a replaced gate to a virtual sink node based on SSTA; a second step in which, if a changed value of a gate timing yield at each gate which propagates delay toward the virtual sink node is smaller than a predetermined threshold value, delay propagation with respect to a fanout gate of the corresponding gate is stopped; and a third step in which, when a delay with respect to the node of the replaced gate is propagated to the virtual sink node, a new timing yield is calculated at the virtual sink node.
摘要翻译：提供了数字电路的增量SSTA（统计静态时序分析）的方法，该方法包括第一步骤，其中当在数字电路中替换门时，从更换的门的节点执行延迟传播基于SSTA的虚拟汇聚节点; 第二步骤，如果在向虚拟汇聚节点传播延迟的每个门的门定时收益的改变值小于预定阈值，则停止相对于相应门的扇出门的延迟传播; 以及第三步骤，当相对于所替换的门的节点的延迟传播到虚拟宿节点时，在虚拟宿节点处计算新的定时收益。

3. 发明申请

US20100306724A1 METHOD OF INCREMENTAL STATISTICAL STATIC TIMING ANALYSIS BASED ON TIMING YIELD 有权
标题翻译：基于时序的增量统计静态时序分析方法
公开(公告)号：US20100306724A1
公开(公告)日：2010-12-02
申请号：US12475545
申请日：2009-05-31
申请人： Jinwook Kim , Young Hwan Kim , Wook Kim
发明人： Jinwook Kim , Young Hwan Kim , Wook Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： Provided is a method of incremental SSTA (statistical static timing analysis) of a digital circuit, the method including a first step in which, when a gate is replaced in the digital circuit, delay propagation is performed from a node of a replaced gate to a virtual sink node based on SSTA; a second step in which, if a changed value of a gate timing yield at each gate which propagates delay toward the virtual sink node is smaller than a predetermined threshold value, delay propagation with respect to a fanout gate of the corresponding gate is stopped; and a third step in which, when a delay with respect to the node of the replaced gate is propagated to the virtual sink node, a new timing yield is calculated at the virtual sink node.
摘要翻译：提供了数字电路的增量SSTA（统计静态时序分析）的方法，该方法包括第一步骤，其中当在数字电路中替换门时，从更换的门的节点执行延迟传播基于SSTA的虚拟汇聚节点; 第二步骤，如果在向虚拟汇聚节点传播延迟的每个门的门定时收益的改变值小于预定阈值，则停止相对于相应门的扇出门的延迟传播; 以及第三步骤，当相对于所替换的门的节点的延迟传播到虚拟宿节点时，在虚拟宿节点处计算新的定时收益。

4. 发明授权

US08271255B2 Method of calculating gate delay based on crosstalk effect due to capacitive coupling 有权
标题翻译：基于电容耦合的串扰效应计算门延迟的方法
公开(公告)号：US08271255B2
公开(公告)日：2012-09-18
申请号：US12475544
申请日：2009-05-31
申请人： Tae II Bae , Young Hwan Kim , Jinwook Kim
发明人： Tae II Bae , Young Hwan Kim , Jinwook Kim
IPC分类号： G06F17/50 , G06F9/455 , G06G7/62
CPC分类号： G06F17/5022 , G06F17/5036
摘要： Provided is a method of exactly calculating the delay of a gate in a digital integrated circuit (IC) that drives a capacitive load and a noise current source based on a crosstalk effect due to capacitive coupling between adjacent conductive lines, the method calculates the delay of the gate by using an output waveform that sums an output waveform of a linear time-varying output resistance model generated by using a gate output resistance library generated by using input and output voltage values of the digital IC and an output waveform of a modified Thevenin equivalent model of the gate.
摘要翻译：提供了一种精确计算由于相邻导线之间的电容耦合引起的串扰效应驱动容性负载和噪声电流源的数字集成电路（IC）中的栅极的延迟的方法，该方法计算延迟通过使用将通过使用通过使用数字IC的输入和输出电压值产生的栅极输出电阻库生成的线性时变输出电阻模型的输出波形和修改的戴维南当量的输出波形相加的输出波形的栅极门的模型。

5. 发明授权

US07987439B2 Method and apparatus for analyzing circuit model by reduction and computer program product for analyzing the circuit model 有权
标题翻译：用于分析电路模型的方法和装置以及用于分析电路模型的计算机程序产品
公开(公告)号：US07987439B2
公开(公告)日：2011-07-26
申请号：US12027732
申请日：2008-02-07
申请人： Hong Bo Che , Young Hwan Kim
发明人： Hong Bo Che , Young Hwan Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/78
摘要： Provided are a method and apparatus for analyzing a circuit model by reducing, and a computer program product for analyzing the circuit model. The circuit model at least includes independent current source models, resistance models, and capacitance models. Also, the circuit model forms a resistance capacitance (RC) network with independent current sources. The method includes selecting a node to be removed using resistance information and comparing conductance of a capacitor for a given time step and the total conductance of the node. Further, the method includes removing the selected nodes and generating RC elements and independent current sources using adjacent nodes, which maintain the accuracy of node voltages of a circuit reduced in an accuracy order used for entrywise perturbation of the corresponding circuit equation. Moreover, an efficient method of handling the independent current sources while reducing the circuit is provided.
摘要翻译：提供了一种通过减少电路模型分析的方法和装置，以及用于分析电路模型的计算机程序产品。电路模型至少包括独立的电流源模型，电阻模型和电容模型。此外，电路模型形成具有独立电流源的电阻电容（RC）网络。该方法包括使用电阻信息来选择要去除的节点，并且比较给定时间步长的电容器的电导率和节点的总电导率。此外，该方法包括使用相邻节点去除所选择的节点并产生RC元件和独立电流源，其保持电路的节点电压的精度以用于相应电路方程的入门扰动的精度顺序降低。此外，提供了一种在减少电路的同时处理独立电流源的有效方法。

6. 发明授权

US06954985B2 Method for plugging holes in a printed circuit board 失效
标题翻译：堵塞印刷电路板上的孔的方法
公开(公告)号：US06954985B2
公开(公告)日：2005-10-18
申请号：US10043146
申请日：2002-01-14
申请人： Sung Gue Lee , Sung Sik Cho , Yong Il Kim , Yong Soon Jang , Ho Sung Choi , Sang Jin Kong , Young Hwan Kim
发明人： Sung Gue Lee , Sung Sik Cho , Yong Il Kim , Yong Soon Jang , Ho Sung Choi , Sang Jin Kong , Young Hwan Kim
IPC分类号： H05K3/28 , H05K3/00 , H05K3/12 , H05K3/42 , H05K3/46 , H01K3/10
CPC分类号： H05K3/0094 , H05K3/1225 , H05K3/28 , H05K2201/09509 , H05K2201/0959 , H05K2201/09881 , H05K2203/0278 , H05K2203/0557 , Y10T29/49117 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/49135 , Y10T29/49144 , Y10T29/49155 , Y10T29/49165 , Y10T29/49167
摘要： A hole plugging method for a printed circuit board, a hole plugging device in accordance therewith and a manufacturing method in accordance therewith where a mask for selectively exposing a via hole, a through hole and a surface pattern of the printed circuit board is positioned on the board having the via hole and the through hole to electrically connect circuit patterns formed on the surface of the board and in the board and an insulating material is plugged in the via hole by abutting and pushing the material on the surface of the board. Therefore, the insulating material can be plugged smoothly without a void, the processing is simplified by plugging the insulating material just to the height of the circuit pattern in a space between the circuit patterns and accordingly, damage to the circuit pattern can be prevented.
摘要翻译：用于印刷电路板的孔堵塞方法，根据本发明的孔堵装置及其制造方法，其中用于选择性地暴露印刷电路板的通孔，通孔和表面图案的掩模位于具有通孔和通孔的电路板电连接板和表面上形成的电路图案和绝缘材料，通过邻接和推动板的表面上的材料而被堵塞在通孔中。因此，绝缘材料可以没有空隙而平滑地插入，通过将绝缘材料刚好插入电路图案之间的空间中的电路图案的高度来简化处理，因此可以防止电路图案的损坏。

7. 发明授权

US06880103B2 Method and apparatus for radio packet data transmission 失效
标题翻译：用于无线电分组数据传输的方法和装置
公开(公告)号：US06880103B2
公开(公告)日：2005-04-12
申请号：US09986415
申请日：2001-11-08
申请人： Young Hwan Kim , Doo Young Moon , Kyung Kuk Lee
发明人： Young Hwan Kim , Doo Young Moon , Kyung Kuk Lee
IPC分类号： H04L12/56 , H04L1/18 , G06F11/00
CPC分类号： H04L1/1887
摘要： A method and device for communicating data within a packet frame unit between a terminal and a base station are disclosed. The terminal communicates the packet data to the base station. In response, the base station transmits a channel occupying signal, if the data transmission from the terminal is perceived by the base station. The terminal continues the communication of the packet data, while the channel occupying signal is active, determines whether the base station receives the communicated packet data, and ends the process for communicating the packet data if the base station receives the communicated packet data. If the base station fails to receive the communicated packet data, the terminal is informed through the channel occupying signal. Thereafter, the terminal discontinues its communication and then re-attempts to communicate the packet data from the beginning.
摘要翻译：公开了一种用于在终端和基站之间的分组帧单元内传送数据的方法和装置。终端将分组数据传送到基站。作为响应，如果来自终端的数据传输被基站感知，则基站发送信道占用信号。终端继续通信分组数据，而信道占用信号是活动的，确定基站是否接收所传送的分组数据，并且如果基站接收到传送的分组数据，则结束传送分组数据的处理。如果基站未能接收所传送的分组数据，则通过信道占用信号通知终端。此后，终端终止其通信，然后从一开始重新尝试传送分组数据。

8. 发明授权

US5770675A Cyclic oligomers comprising m-phenylene isophthalamide and polymers thereof 失效
标题翻译：包含间苯二甲酰间苯二胺的环状低聚物及其聚合物
公开(公告)号：US5770675A
公开(公告)日：1998-06-23
申请号：US664898
申请日：1996-06-18
申请人： Young Hwan Kim , Wesley Memeger, Jr.
发明人： Young Hwan Kim , Wesley Memeger, Jr.
IPC分类号： C07D259/00 , C07F3/00 , C07F15/02 , C08G69/32 , C08G73/00
CPC分类号： C07F3/003 , C07D259/00 , C07F15/025 , C08G69/32
摘要： Disclosed herein are cyclic oligomers comprising substituted or unsubstituted m-phenylene isophthalamide, complexes of these oligomers with selected metal salts, novel methods for their preparation, and polymerization of the cyclic oligomers to linear aramids. The aramids are useful, for example, as fibers for fire resistant clothing. Amino-finctional cyclic oligomers may be reacted with polyfunctional acyl halides to produce polyamides.
摘要翻译：本文公开了包含取代或未取代的间亚苯基间苯二甲酰胺的环状低聚物，这些低聚物与选择的金属盐的络合物，其制备方法和环状低聚物聚合成直链芳族聚酰胺。芳族聚酰胺是有用的，例如，作为防火服装的纤维。氨基官能的环状低聚物可以与多官能酰基卤反应生成聚酰胺。

9. 发明授权

US09193900B2 Optoelectronic device and stacking structure 有权
标题翻译：光电器件和堆叠结构
公开(公告)号：US09193900B2
公开(公告)日：2015-11-24
申请号：US13467763
申请日：2012-05-09
申请人： Hyun A Kang , Young Hwan Kim , Eun Joo Jang , Shin Ae Jun , Hyo Sook Jang
发明人： Hyun A Kang , Young Hwan Kim , Eun Joo Jang , Shin Ae Jun , Hyo Sook Jang
IPC分类号： H01L51/54 , C09K11/02 , H01L33/44
CPC分类号： C09K11/02 , C09K11/883 , H01L33/44 , H01L2224/14 , H01L2224/16145 , H01L2224/48091 , H01L2924/00014
摘要： Provided is an optoelectronic device that includes: a light source; an emission layer disposed on the light source and including light emitting particles dispersed in a matrix polymer; and a polymer film disposed on the emission layer. The polymer film includes two layers: a first layer including a first polymer and a second layer including a second polymer. The first polymer includes a polymerized product of a first monomer including at least two thiol (—SH) groups and a siloxane-based second monomer or oligomer including at least one carbon-carbon unsaturated bond at a terminal end, and the second polymer includes a polymerized product of a third monomer including at least two thiol (—SH) groups and a fourth monomer including at least two carbon-carbon unsaturated bonds at a terminal end.
摘要翻译：提供了一种光电子器件，其包括：光源; 发光层，其设置在所述光源上，并且包含分散在基质聚合物中的发光粒子; 以及设置在发光层上的聚合物膜。聚合物膜包括两层：包含第一聚合物的第一层和包含第二聚合物的第二层。第一聚合物包括包含至少两个硫醇（-SH）基团的第一单体和在末端包含至少一个碳 - 碳不饱和键的硅氧烷基第二单体或低聚物的聚合产物，第二聚合物包括包含至少两个硫醇（-SH）基团的第三单体和在末端包含至少两个碳 - 碳不饱和键的第四单体的聚合产物。

10. 发明申请

US20150283033A1 FILTER CAP FOR SYRINGE 审中-公开
标题翻译：灌装过滤嘴
公开(公告)号：US20150283033A1
公开(公告)日：2015-10-08
申请号：US14437218
申请日：2013-07-23
申请人： Young Sang KIM , Young Hwan KIM
发明人： Young Sang Kim , Young Hwan Kim
IPC分类号： A61J1/20
CPC分类号： A61J1/2096 , A61J1/2086 , A61M5/165 , A61M5/3145 , A61M5/3202 , A61M5/3213 , A61M5/34 , A61M5/38
摘要： The present invention relates to a filter cap for a syringe, and, more specifically, to one comprising: a housing having a through-passing injection-liquid inflow passage, a syringe needle insertion passage that passes through so as to link through to the injection-liquid inflow passage in such a way that a syringe needle can be inserted therein, and an injection needle tight-fitting passage that passes through so as to link through to the syringe needle insertion passage in such a way that it is possible to tightly fit the syringe needle therein and form a negative pressure; and a filter which is fitted by melt adhesion to a through-linking portion of the injection-liquid inflow passage and the syringe needle insertion passage in such a way that it is possible to filter the injection liquid.
摘要翻译：本发明涉及一种用于注射器的过滤帽，更具体地说，涉及一种包括：具有通过注入液体流入通道的壳体，穿过以连接到注射器的注射器针插入通道液体流入通道，使得注射器针头可以插入其中;以及注射针紧固通道，其穿过以便连接到注射器针插入通道，使得可以紧密配合注射器针头内部形成负压; 以及过滤器，其通过熔融粘附装配到注射液流入通道和注射器针插入通道的通过连接部分，使得可以过滤注射液体。

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