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1. 发明申请

US20120080723A1 FABRICATING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATED USING THE SAME METHOD 审中-公开
标题翻译：使用相同方法制作的半导体器件和半导体器件的制造方法
公开(公告)号：US20120080723A1
公开(公告)日：2012-04-05
申请号：US13213364
申请日：2011-08-19
申请人： Jin-Wook LEE , Myeong-Cheol Kim , Sang-Min Lee , Young-Ju Park , Hyung-Yong Kim , Myung-Hoon Jung
发明人： Jin-Wook LEE , Myeong-Cheol Kim , Sang-Min Lee , Young-Ju Park , Hyung-Yong Kim , Myung-Hoon Jung
IPC分类号： H01L21/336 , H01L21/28 , H01L29/78 , H01L21/3065
CPC分类号： H01L29/7848 , H01L21/26506 , H01L21/30608 , H01L21/3065 , H01L21/823412 , H01L21/823425 , H01L21/823807 , H01L21/823814 , H01L27/11 , H01L29/66636 , H01L29/78
摘要： A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch, forming a plurality of second gates in the second region of the substrate, such that the second gates are spaced apart from each other at a second pitch different from the first pitch, implanting an etch rate adjusting dopant into the second region to form implanted regions, while blocking the first region, forming a first trench by etching the first region between the plurality of first gates, and forming a second trench by etching the second region between the plurality of second gates.
摘要翻译：半导体器件的制造方法包括提供具有第一区域和第二区域的衬底，在衬底的第一区域中形成多个第一栅极，使得第一栅极以第一间距相互间隔开，在所述衬底的所述第二区域中形成多个第二栅极，使得所述第二栅极以不同于所述第一间距的第二间距彼此间隔开，将蚀刻速率调节掺杂剂注入所述第二区域以形成注入区域，同时阻挡第一区域，通过蚀刻多个第一栅极之间的第一区域形成第一沟槽，并且通过蚀刻多个第二栅极之间的第二区域形成第二沟槽。

2. 发明申请

US20120164809A1 SEMICONDUCTOR DEVICES INCLUDING STRAINED SEMICONDUCTOR REGIONS, METHODS OF FABRICATING THE SAME, AND ELECTRONIC SYSTEMS INCLUDING THE DEVICES 审中-公开
标题翻译：包括应变半导体区域的半导体器件，其制造方法以及包括器件的电子系统
公开(公告)号：US20120164809A1
公开(公告)日：2012-06-28
申请号：US13298732
申请日：2011-11-17
申请人： Jun-Ho YOON , Kyoung-Sub SHIN , Jin-Wook LEE , Je-Woo HAN , Hyung-Yong KIM
发明人： Jun-Ho YOON , Kyoung-Sub SHIN , Jin-Wook LEE , Je-Woo HAN , Hyung-Yong KIM
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/30608 , H01L21/3065 , H01L21/32137 , H01L29/66636 , H01L29/7848
摘要： A method of fabricating a semiconductor device includes forming a gate pattern on a substrate, forming an amorphous silicon (a-Si) region adjacent to the gate pattern by implanting a dopant containing a Group IV or VIII element into portions of the semiconductor substrate, forming gate spacers on sidewalls of the gate pattern, forming a first cavity by etching the a-Si region and the substrate using a first etching process, forming a second cavity by etching the substrate, such that the second cavity expands a profile of the first cavity in lateral and vertical directions, and forming a strained semiconductor region in the second cavity.
摘要翻译：制造半导体器件的方法包括在衬底上形成栅极图案，通过将含有IV或VIII族元素的掺杂剂注入到半导体衬底的部分中形成与栅极图案相邻的非晶硅（a-Si）区域，形成在栅极图案的侧壁上的栅极间隔物，通过使用第一蚀刻工艺蚀刻a-Si区域和衬底形成第一腔体，通过蚀刻衬底形成第二腔体，使得第二腔体扩展第一腔体的轮廓在横向和垂直方向上，并在第二腔中形成应变半导体区域。

3. 发明申请

US20090003064A1 FLASH MEMORY DEVICE AND METHOD OF PROGRAMMING FLASH MEMORY DEVICE 有权
标题翻译：闪存存储器件和编程闪速存储器件的方法
公开(公告)号：US20090003064A1
公开(公告)日：2009-01-01
申请号：US12126080
申请日：2008-05-23
申请人： Kyong-Ae KIM , Jin-Wook LEE , Yun-Ho CHOI
发明人： Kyong-Ae KIM , Jin-Wook LEE , Yun-Ho CHOI
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/349
摘要： A flash memory device and a method of programming the same include a memory cell array, a pass/fail check circuit and a control logic circuit. The memory cell array includes multiple memory cells arranged in rows and columns. The pass/fail check circuit verifies whether data bits selected by a column address during a column scan operation have program data values. The control logic circuit detects fail data bits from the selected data bits and stores the column address in response to the verification result of the pass/fail check circuit. The control logic circuit also compares a number of the fail data bits with a reference value and controls generation of the column address according to the comparison result.
摘要翻译：闪速存储器件及其编程方法包括存储单元阵列，通过/失败校验电路和控制逻辑电路。存储单元阵列包括以行和列排列的多个存储单元。通过/失败检查电路验证在列扫描操作期间由列地址选择的数据位是否具有程序数据值。控制逻辑电路根据所选数据位检测故障数据位，并响应于通过/不通过检查电路的验证结果存储列地址。控制逻辑电路还将多个故障数据位与参考值进行比较，并根据比较结果控制列地址的生成。

4. 发明申请

US20060249760A1 HIGH-VOLTAGE TRANSISTOR OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：半导体器件的高电压晶体管及其形成方法
公开(公告)号：US20060249760A1
公开(公告)日：2006-11-09
申请号：US11379206
申请日：2006-04-18
申请人： Gyoung-Ho Buh , Yu-Gyun Shin , Tai-Su Park , Jin-Wook LEE , Guk-Hyon Yon
发明人： Gyoung-Ho Buh , Yu-Gyun Shin , Tai-Su Park , Jin-Wook LEE , Guk-Hyon Yon
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/1045 , H01L29/66659 , H01L29/78
摘要： There are provided a high-voltage transistor and a method of forming the same. A channel region of the high-voltage transistor includes a first region and a second region. The first region has high impurity concentration that is higher than that of the second region. In addition, the first region may be in contact with the isolation layer. Thus, it is possible to enhance leakage current characteristics of the high-voltage transistor.
摘要翻译：提供了高压晶体管及其形成方法。高压晶体管的沟道区域包括第一区域和第二区域。第一区域的杂质浓度高于第二区域。此外，第一区域可以与隔离层接触。因此，可以提高高压晶体管的漏电流特性。

5. 发明申请

US20110126907A1 SOLAR CELL AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：太阳能电池及其制造方法
公开(公告)号：US20110126907A1
公开(公告)日：2011-06-02
申请号：US12819346
申请日：2010-06-21
申请人： Jin-Wook LEE , Doo-Youl LEE , Hwa-Young KO
发明人： Jin-Wook LEE , Doo-Youl LEE , Hwa-Young KO
IPC分类号： H01L31/00 , H01L31/18
CPC分类号： H01L31/022425 , H01L31/02167 , H01L31/02168 , H01L31/0682 , Y02E10/547
摘要： A solar cell includes; a semiconductor substrate, an n+ region disposed on a surface of the semiconductor substrate, a plurality of first electrodes connected to the n+ region, a p+ region disposed on the surface of the semiconductor substrate and separated from the n+ region, a second electrode connected to the p+ region, and a first dielectric layer which has a positive fixed charge and is disposed between adjacent first electrodes of the plurality of first electrodes, and a method of manufacturing the same.
摘要翻译：太阳能电池包括：半导体衬底，设置在半导体衬底的表面上的n +区，连接到n +区的多个第一电极，设置在半导体衬底的表面上并与n +区分离的p +区，连接到 p +区，以及具有正固定电荷且设置在多个第一电极的相邻第一电极之间的第一电介质层及其制造方法。

6. 发明申请

US20080195803A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE FOR SUPPORTING HIGH SPEED SEARCH IN CACHE MEMORY 有权
标题翻译：用于支持高速缓存搜索的非易失性半导体存储器件
公开(公告)号：US20080195803A1
公开(公告)日：2008-08-14
申请号：US12029665
申请日：2008-02-12
申请人： Chan-Ik PARK , Jin-Wook LEE , Byoung-Kook LEE
发明人： Chan-Ik PARK , Jin-Wook LEE , Byoung-Kook LEE
IPC分类号： G06F12/00
CPC分类号： G06F12/0866 , G06F12/0246 , G06F2212/222 , G06F2212/7201 , G06F2212/7203
摘要： A method for reducing a memory map table search time when employing a semiconductor memory device as a temporary memory of large capacity storage device, and a semiconductor memory device therefore, are provided. A MAP RAM is prepared for storing map table data related to the nonvolatile memory area in the volatile memory area. At an initial power-up operation, it is determined whether a logical address is searched for from the map table data while the map table data existing in a map storage area of the nonvolatile memory area is loaded into the MAP RAM. A physical address corresponding to the logical address is provided as an output, when the logical address is searched for. Search time for a memory map table is reduced and read performance in a high speed map information search is increased.
摘要翻译：提供一种用于在采用半导体存储器件作为大容量存储器件的临时存储器时减少存储器映射表搜索时间的方法，以及半导体存储器件。准备MAP RAM用于存储与易失性存储器区域中的非易失性存储器区域相关的映射表数据。在初始加电操作中，确定存在于非易失存储器区域的映射存储区域中的映射表数据是否被加载到MAP RAM中时，从地图表数据中搜索逻辑地址。当搜索逻辑地址时，提供与逻辑地址对应的物理地址作为输出。降低了存储器映射表的搜索时间，并且增加了在高速地图信息搜索中的读取性能。

7. 发明申请

US20110183459A1 METHOD OF MANUFACTURING SOLAR CELL 失效
标题翻译：制造太阳能电池的方法
公开(公告)号：US20110183459A1
公开(公告)日：2011-07-28
申请号：US12828701
申请日：2010-07-01
申请人： Dong-Kyun KIM , Yun-Gi KIM , Jin-Wook LEE , Hwa-Young KO
发明人： Dong-Kyun KIM , Yun-Gi KIM , Jin-Wook LEE , Hwa-Young KO
IPC分类号： H01L31/18 , H01L31/04
CPC分类号： H01L31/02168 , H01L31/022425 , H01L31/056 , H01L31/0682 , H01L31/1804 , Y02E10/52 , Y02E10/547 , Y02P70/521
摘要： A method of manufacturing a solar cell includes providing a semiconductor substrate; disposing a reflection layer on one side of the semiconductor substrate, wherein the disposing the reflection layer comprises implanting gas into a surface of the one side of the semiconductor substrate and heating the gas; disposing an n+ region and a p+ region separated from each other on the other opposite facing side of the semiconductor substrate; disposing a first electrode connected to the n+ region; and disposing a second electrode connected to the p+ region.
摘要翻译：一种制造太阳能电池的方法包括提供半导体衬底; 在半导体衬底的一侧上设置反射层，其中设置反射层包括将气体注入到半导体衬底的一侧的表面中并加热气体; 在所述半导体衬底的另一个相对的面上设置彼此分离的n +区域和p +区域; 设置连接到n +区的第一电极; 以及设置连接到p +区域的第二电极。

8. 发明申请

US20110140775A1 COMBINED CELL DOHERTY POWER AMPLIFICATION APPARATUS AND METHOD 有权
标题翻译：组合式电池功率放大装置和方法
公开(公告)号：US20110140775A1
公开(公告)日：2011-06-16
申请号：US12967404
申请日：2010-12-14
申请人： Sungchul HONG , Jin-Wook LEE
发明人： Sungchul HONG , Jin-Wook LEE
IPC分类号： H03F3/68
CPC分类号： H03F1/0288 , H03F3/602
摘要： A Doherty power amplification apparatus and method using a combined cell are provided. The Doherty power amplification apparatus includes, a power splitter for splitting an input power, and outputting the split powers to a carrier amplification unit and (N−1) peaking amplification units, wherein the carrier amplification unit, including M carrier power amplifiers, for amplifying power output from the power splitter; the (N−1) peaking amplification units, each of which includes M peaking power amplifiers, for amplifying the respective split powers output from the power splitter, and a power combiner for combining a power amplified by the carrier amplification unit and the respective split powers amplified by the (N−1) peaking amplification units, and for outputting the combined power, wherein N represents an integer obtained by adding a number of the carrier amplification units and a number of the (N−1) peaking amplification units, and M represents an integer which is equal to or more than 1.
摘要翻译：提供了一种使用组合电池的Doherty功率放大装置和方法。 Doherty功率放大装置包括：功率分配器，用于分离输入功率，并将分离功率输出到载波放大单元和（N-1）峰化放大单元，其中载波放大单元包括M个载波功率放大器，用于放大功率分配器的功率输出; 每个包括M个峰值功率放大器的（N-1）个峰值放大单元，用于放大从功率分配器输出的相应的分离功率;以及功率组合器，用于组合由载波放大单元放大的功率和相应的分离功率（N-1）峰化放大单元放大，并输出组合功率，其中N表示通过将多个载波放大单元和多个（N-1）个峰值放大单元相加得到的整数，M 表示等于或大于1的整数。

9. 发明申请

US20080170440A1 FLASH MEMORY DEVICE WITH SPLIT STRING SELECTION LINE STRUCTURE 有权
标题翻译：具有分选线选择线结构的闪存存储器件
公开(公告)号：US20080170440A1
公开(公告)日：2008-07-17
申请号：US12014902
申请日：2008-01-16
申请人： Jin-Wook LEE , Sang-Won HWANG
发明人： Jin-Wook LEE , Sang-Won HWANG
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/24 , G11C16/3427
摘要： A flash memory device is disclosed and includes a memory cell array including a plurality of sectors. Each one of the plurality of sectors includes a plurality of strings, and each of the plurality of strings includes a plurality of memory cells series connected between a string select transistor and a ground select transistor. The flash memory device also includes a plurality of string selection lines, wherein each one of the plurality of string selection lines is respectively connected to string select transistors associated the plurality of strings in one of the plurality of sectors.
摘要翻译：闪存器件被公开并且包括包括多个扇区的存储单元阵列。多个扇区中的每一个包括多个串，并且多个串中的每一个包括连接在串选择晶体管和接地选择晶体管之间的多个存储单元串联。闪存装置还包括多个串选择线，其中多个串选择线中的每一个分别连接到与多个扇区中的一个扇区中的多个扇区中的多个字符串相关联的串选择晶体管。

10. 发明申请

US20130037921A1 RESIST UNDERLAYER COMPOSITION AND PROCESS OF PRODUCING INTEGRATED CIRCUIT DEVICES USING SAME 有权
标题翻译：使用相同的底漆组合物和制造集成电路装置的方法
公开(公告)号：US20130037921A1
公开(公告)日：2013-02-14
申请号：US13571751
申请日：2012-08-10
申请人： Kwen-Woo HAN , Mi-Young KIM , Woo-Jin LEE , Han-Song LEE , Seung-Hee HONG , Sang-Kyun KIM , Jin-Wook LEE
发明人： Kwen-Woo HAN , Mi-Young KIM , Woo-Jin LEE , Han-Song LEE , Seung-Hee HONG , Sang-Kyun KIM , Jin-Wook LEE
IPC分类号： C08L83/06 , H01L29/02 , H01L21/32 , C08K5/101 , C08K5/42
CPC分类号： C08L83/06 , G03F7/0752 , G03F7/091 , G03F7/094
摘要： A resist underlayer composition, including a solvent, and an organosilane condensation polymerization product of hydrolyzed products produced from a compound represented by Chemical Formula 1, a compound represented by Chemical Formula 2, and a compound represented by Chemical Formula 3.
摘要翻译：包含溶剂的抗蚀剂底层组合物和由化学式1表示的化合物，由化学式2表示的化合物和由化学式3表示的化合物制备的水解产物的有机硅烷缩聚产物。

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