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1. 发明授权

US07871897B2 Method of forming shallow trench isolation regions in devices with NMOS and PMOS regions 失效
标题翻译：在具有NMOS和PMOS区域的器件中形成浅沟槽隔离区的方法
公开(公告)号：US07871897B2
公开(公告)日：2011-01-18
申请号：US12466178
申请日：2009-05-14
申请人： Dong-woon Shin , Soo-jin Hong , Guk-hyon Yon , Si-young Choi , Sun-ghil Lee
发明人： Dong-woon Shin , Soo-jin Hong , Guk-hyon Yon , Si-young Choi , Sun-ghil Lee
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , H01L21/823878 , H01L27/10894 , H01L27/11546
摘要： A mask pattern is formed on a semiconductor substrate in which a cell region, a PMOS region, and an NMOS region are defined. Trenches are formed in the cell region, the PMOS region, and the NMOS region. A sidewall oxide layer and a protection layer are formed in the trenches, and a portion of the protection layer in the PMOS region is removed. A first device isolation insulating layer is formed on the substrate, filling the trenches. Portions of the first device isolation insulating layer are removed to expose the mask pattern and the trenches of the cell region and the NMOS region and to leave a portion of the first device isolation insulating layer in the trench in the PMOS region. A liner is formed on the portion of the first device isolation region in the trench in the PMOS region and conforming to sidewalls of the trenches in the cell region and the NMOS region. A second device isolation insulating layer is formed on the substrate, filling the trenches in the cell region and the NMOS region. Portions of the second device isolation insulating layer are removed to expose the mask pattern and to leave portions of the second device isolation insulating layer in the trenches of the cell region and the NMOS region.
摘要翻译：在其中限定了单元区域，PMOS区域和NMOS区域的半导体衬底上形成掩模图案。在单元区域，PMOS区域和NMOS区域中形成沟槽。在沟槽中形成侧壁氧化物层和保护层，并且去除PMOS区域中的保护层的一部分。在衬底上形成第一器件隔离绝缘层，填充沟槽。去除第一器件隔离绝缘层的部分以露出掩模图案和单元区域和NMOS区域的沟槽，并且在PMOS区域的沟槽中留下第一器件隔离绝缘层的一部分。衬垫形成在PMOS区域的沟槽中的第一器件隔离区域的部分上，并且与衬底区域和NMOS区域中的沟槽的侧壁一致。在衬底上形成第二器件隔离绝缘层，填充单元区域和NMOS区域中的沟槽。去除第二器件隔离绝缘层的部分以暴露掩模图案并且将第二器件隔离绝缘层的部分留在单元区域和NMOS区域的沟槽中。

2. 发明申请

US20080083944A1 NAND-TYPE FLASH MEMORY DEVICES INCLUDING SELECTION TRANSISTORS WITH AN ANTI-PUNCHTHROUGH IMPURITY REGION AND METHODS OF FABRICATING THE SAME 有权
标题翻译： NAND型闪存存储器件，其中包括具有防伪突变区域的选择晶体管及其制造方法
公开(公告)号：US20080083944A1
公开(公告)日：2008-04-10
申请号：US11849533
申请日：2007-09-04
申请人： Gyoung-Ho Buh , Sun-Ghil Lee , Jong-Ryeol Yoo , Deok-Hyung Lee , Guk-Hyon Yon
发明人： Gyoung-Ho Buh , Sun-Ghil Lee , Jong-Ryeol Yoo , Deok-Hyung Lee , Guk-Hyon Yon
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/12 , H01L29/1083 , H01L29/78
摘要： A NAND-type flash memory device including selection transistors is provided. The device includes first and second impurity regions formed in a semiconductor substrate, and first and second selection gate patterns disposed on the semiconductor substrate between the first and second impurity regions. The first and second selection gate patterns are disposed adjacent to the first and second impurity regions, respectively. A plurality of cell gate patterns are disposed between the first and second selection gate patterns. A first anti-punchthrough impurity region that surrounds the first impurity region is provided in the semiconductor substrate. The first anti-punchthrough impurity region overlaps with a first edge of the first selection gate pattern adjacent to the first impurity region. A second anti-punchthrough impurity region that surrounds the second impurity region is provided in the semiconductor substrate. The second anti-punchthrough impurity region overlaps with a first edge of the second selection gate pattern adjacent to the second impurity region.
摘要翻译：提供了包括选择晶体管的NAND型闪速存储器件。该器件包括形成在半导体衬底中的第一和第二杂质区，以及设置在第一和第二杂质区之间的半导体衬底上的第一和第二选择栅极图案。第一和第二选择栅极图案分别与第一和第二杂质区相邻设置。多个单元栅极图案设置在第一和第二选择栅极图案之间。在半导体衬底中设置围绕第一杂质区的第一抗穿透杂质区。第一抗穿透杂质区域与第一选择栅极图案的与第一杂质区域相邻的第一边缘重叠。在半导体衬底中设置有围绕第二杂质区的第二抗穿透杂质区。第二抗穿透杂质区域与第二选择栅极图案的与第二杂质区域相邻的第一边缘重叠。

3. 发明申请

US20060138478A1 Semiconductor device and method of forming same 审中-公开
标题翻译：半导体器件及其形成方法
公开(公告)号：US20060138478A1
公开(公告)日：2006-06-29
申请号：US11318827
申请日：2005-12-27
申请人： Gyoung-Ho Buh , Yu-Gyun Shin , Chang-Woo Ryoo , Soo-Jin Hong , Jin-Wook Lee , Guk-Hyon Yon
发明人： Gyoung-Ho Buh , Yu-Gyun Shin , Chang-Woo Ryoo , Soo-Jin Hong , Jin-Wook Lee , Guk-Hyon Yon
IPC分类号： H01L29/76 , H01L29/788 , H01L29/94
CPC分类号： H01L21/26506 , H01L29/40114 , H01L29/40117 , H01L29/6659 , H01L29/66825 , H01L29/66833 , H01L29/78 , H01L29/7833 , H01L29/7881
摘要： A semiconductor device includes a gate pattern disposed on a semiconductor substrate, a gate spacer disposed on both sidewalls of the gate pattern, and a fixed charge layer disposed in the semiconductor substrate below the gate spacer. Elements generating fixed charges are injected into the fixed charge layer. A layer in which carriers induced by the fixed charge layer are accumulated is disposed below the fixed charge layer. The elements are segregated to a substrate of the semiconductor substrate from the inside of the semiconductor substrate by heat.
摘要翻译：半导体器件包括设置在半导体衬底上的栅极图案，设置在栅极图案的两个侧壁上的栅极隔离物和设置在栅极间隔物下方的半导体衬底中的固定电荷层。产生固定电荷的元件被注入到固定电荷层中。由固定电荷层感应的载流子被累积的层设置在固定电荷层的下方。元件通过加热从半导体衬底的内部分离到半导体衬底的衬底。

4. 发明申请

US20140061757A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140061757A1
公开(公告)日：2014-03-06
申请号：US13971279
申请日：2013-08-20
申请人： SUNGGIL KIM , Sunghoi Hur , Jung-Hwan Kim , HongSuk Kim , Guk-Hyon Yon , JaeHo Choi
发明人： SUNGGIL KIM , Sunghoi Hur , Jung-Hwan Kim , HongSuk Kim , Guk-Hyon Yon , JaeHo Choi
IPC分类号： H01L29/788 , H01L29/66
CPC分类号： H01L29/788 , H01L21/764 , H01L27/11521 , H01L27/11556 , H01L27/11568 , H01L27/11582 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/66833
摘要： A semiconductor device includes a semiconductor substrate having a plurality of active regions defined by a trench. A gate electrode crosses the plurality of active regions. A plurality of charge storing cells is disposed between the gate electrode and each of the plurality of active regions. A porous insulating layer is disposed between the gate electrode and the plurality of charge storing cells. The porous insulating layer includes a portion extended over the trench. An air gap is disposed between the extended portion of the porous insulating layer and a bottom surface of the trench.
摘要翻译：半导体器件包括具有由沟槽限定的多个有源区的半导体衬底。栅电极与多个有源区交叉。多个电荷存储单元设置在栅电极和多个有源区域中的每一个之间。多孔绝缘层设置在栅电极和多个电荷存储单元之间。多孔绝缘层包括在沟槽上延伸的部分。空隙设置在多孔绝缘层的延伸部分和沟槽的底表面之间。

5. 发明申请

US20090311846A1 METHOD OF FORMING SHALLOW TRENCH ISOLATION REGIONS IN DEVICES WITH NMOS AND PMOS REGIONS 失效
标题翻译：在具有NMOS和PMOS区域的器件中形成低温分离区的方法
公开(公告)号：US20090311846A1
公开(公告)日：2009-12-17
申请号：US12466178
申请日：2009-05-14
申请人： Dong-Woon Shin , Soo-jin Hong , Guk-hyon Yon , Si-young Choi , Sun-ghil Lee
发明人： Dong-Woon Shin , Soo-jin Hong , Guk-hyon Yon , Si-young Choi , Sun-ghil Lee
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , H01L21/823878 , H01L27/10894 , H01L27/11546
摘要： A mask pattern is formed on a semiconductor substrate in which a cell region, a PMOS region, and an NMOS region are defined. Trenches are formed in the cell region, the PMOS region, and the NMOS region. A sidewall oxide layer and a protection layer are formed in the trenches, and a portion of the protection layer in the PMOS region is removed. A first device isolation insulating layer is formed on the substrate, filling the trenches. Portions of the first device isolation insulating layer are removed to expose the mask pattern and the trenches of the cell region and the NMOS region and to leave a portion of the first device isolation insulating layer in the trench in the PMOS region. A liner is formed on the portion of the first device isolation region in the trench in the PMOS region and conforming to sidewalls of the trenches in the cell region and the NMOS region. A second device isolation insulating layer is formed on the substrate, filling the trenches in the cell region and the NMOS region. Portions of the second device isolation insulating layer are removed to expose the mask pattern and to leave portions of the second device isolation insulating layer in the trenches of the cell region and the NMOS region.
摘要翻译：在其中限定了单元区域，PMOS区域和NMOS区域的半导体衬底上形成掩模图案。在单元区域，PMOS区域和NMOS区域中形成沟槽。在沟槽中形成侧壁氧化物层和保护层，并且去除PMOS区域中的保护层的一部分。在衬底上形成第一器件隔离绝缘层，填充沟槽。去除第一器件隔离绝缘层的部分以露出掩模图案和单元区域和NMOS区域的沟槽，并且在PMOS区域的沟槽中留下第一器件隔离绝缘层的一部分。衬垫形成在PMOS区域的沟槽中的第一器件隔离区域的部分上，并且与衬底区域和NMOS区域中的沟槽的侧壁一致。在衬底上形成第二器件隔离绝缘层，填充单元区域和NMOS区域中的沟槽。去除第二器件隔离绝缘层的部分以暴露掩模图案并且将第二器件隔离绝缘层的部分留在单元区域和NMOS区域的沟槽中。

6. 发明授权

US07492006B2 Semiconductor transistors having surface insulation layers and methods of fabricating such transistors 失效
标题翻译：具有表面绝缘层的半导体晶体管和制造这种晶体管的方法
公开(公告)号：US07492006B2
公开(公告)日：2009-02-17
申请号：US11215217
申请日：2005-08-30
申请人： Gyoung-Ho Buh , Yu-Gyun Shin , Sang-Jin Hyun , Guk-Hyon Yon
发明人： Gyoung-Ho Buh , Yu-Gyun Shin , Sang-Jin Hyun , Guk-Hyon Yon
IPC分类号： H01L23/62
CPC分类号： H01L29/4983 , H01L21/28194 , H01L21/28273 , H01L21/28282 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78 , H01L29/7881 , H01L29/792
摘要： Semiconductor devices having a transistor and methods of fabricating such devices are disclosed. The device may include a gate pattern formed on a substrate, spacers formed on sidewalls of the gate pattern, a surface insulation layer that may contact the substrate is interposed between the spacers and the substrate. An inversion layer is provided in the surface region of the substrate under the surface insulation layer. The surface insulation layer is formed of a material generating large quantities of surface states at an interface between the substrate and the surface insulation layer.
摘要翻译：公开了具有晶体管的半导体器件及其制造方法。器件可以包括形成在衬底上的栅极图案，形成在栅极图案的侧壁上的间隔物，可以接触衬底的表面绝缘层插入在衬垫和衬底之间。在表面绝缘层下方的基板的表面区域设置反转层。表面绝缘层由在基板和表面绝缘层之间的界面处产生大量表面状态的材料形成。

7. 发明授权

US07176049B2 Method of increasing a free carrier concentration in a semiconductor substrate 失效
公开(公告)号：US07176049B2
公开(公告)日：2007-02-13
申请号：US10845589
申请日：2004-05-14
申请人： Gyoung Ho Buh , Ji-Sang Yahng , Yu Gyun Shin , Guk-Hyon Yon , Sangjin Hyun
发明人： Gyoung Ho Buh , Ji-Sang Yahng , Yu Gyun Shin , Guk-Hyon Yon , Sangjin Hyun
IPC分类号： H01L21/00
CPC分类号： H01L21/266 , H01L21/2022 , H01L21/26513 , H01L21/268 , H01L21/2686 , H01L21/28211 , H01L21/324 , H01L21/76232 , H01L21/823462 , H01L21/823481
摘要： A method of selectively heating a predetermined region of a semiconductor substrate includes providing a semiconductor substrate, selectively focusing a free carrier generation light on only a predetermined region of the semiconductor substrate, irradiating the free carrier generation light on the predetermined region of the semiconductor substrate to increase a free carrier concentration within the predetermined region of the semiconductor substrate, wherein the free carrier generation light causes the predetermined region to increase in temperature by less than a temperature necessary to change the solid phase of the predetermined region, and irradiating the semiconductor substrate with a heating light to selectively heat the predetermined region of the semiconductor substrate.

8. 发明申请

US20160172372A1 SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件
公开(公告)号：US20160172372A1
公开(公告)日：2016-06-16
申请号：US14963987
申请日：2015-12-09
申请人： JU-MI YUN , YOUNG-JIN NOH , KWANG-MIN PARK , JAE-YOUNG AHN , GUK-HYON YON , DONG-CHUL YOO , JOONG-YUN RA , YOUNG-SEON SON , JEON-IL LEE , HUN-HYEONG LIM
发明人： JU-MI YUN , YOUNG-JIN NOH , KWANG-MIN PARK , JAE-YOUNG AHN , GUK-HYON YON , DONG-CHUL YOO , JOONG-YUN RA , YOUNG-SEON SON , JEON-IL LEE , HUN-HYEONG LIM
IPC分类号： H01L27/115 , H01L29/51 , H01L29/49 , H01L29/788
CPC分类号： H01L27/11582 , H01L21/28273 , H01L21/28282 , H01L27/11556 , H01L29/513 , H01L29/518 , H01L29/7883
摘要： A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.
摘要翻译：如下提供半导体器件。隧道绝缘层设置在基板上。隧道绝缘层包括第一氧化硅层，第二氧化硅层和介于第一氧化硅层和第二氧化硅层之间的硅层。硅层的厚度小于第一氧化硅层和第二氧化硅层的厚度。栅极图案设置在隧道绝缘层上。

9. 发明申请

US20120104485A1 Nonvolatile Memory Devices And Methods Of Manufacturing The Same 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20120104485A1
公开(公告)日：2012-05-03
申请号：US13281784
申请日：2011-10-26
申请人： Junkyu Yang , HongSuk Kim , Kihyun Hwang , Jaeyoung Ahn , Guk-Hyon Yon
发明人： Junkyu Yang , HongSuk Kim , Kihyun Hwang , Jaeyoung Ahn , Guk-Hyon Yon
IPC分类号： H01L29/792
CPC分类号： H01L27/11521 , H01L21/764 , H01L27/11568
摘要： A method of manufacturing a nonvolatile memory device includes forming a tunnel dielectric layer, a charge storage layer, and a hard mask layer on a substrate in sequential order. Active portions are defined by forming trenches in the substrate. A tunnel dielectric pattern, a preliminary charge storage pattern, and a hard mask pattern are formed on each of the active portions in sequential order by sequentially patterning the hard mask layer, the charge storage layer, the tunnel dielectric layer, and the substrate. A capping pattern is formed covering an upper surface of the trenches such that a first void remains in a lower portion of the trenches, the capping pattern including etch particles formed by etching the hard mask pattern through a sputtering etch process.
摘要翻译：一种制造非易失性存储器件的方法包括在衬底上依次形成隧道介电层，电荷存储层和硬掩模层。通过在衬底中形成沟槽来限定活性部分。通过对硬掩模层，电荷存储层，隧道介电层和衬底进行顺序构图，按顺序在有源部分的每一个上形成隧道电介质图案，初电电荷存储图案和硬掩模图案。形成覆盖沟槽的上表面的覆盖图案，使得第一空隙保留在沟槽的下部，封盖图案包括通过溅射蚀刻工艺蚀刻硬掩模图案形成的蚀刻颗粒。

10. 发明授权

US07514744B2 Semiconductor device including carrier accumulation layers 失效
标题翻译：半导体器件包括载流子堆积层
公开(公告)号：US07514744B2
公开(公告)日：2009-04-07
申请号：US11322335
申请日：2005-12-30
申请人： Gyoung-Ho Buh , Yu-Gyun Shin , Soo-Jin Hong , Guk-Hyon Yon
发明人： Gyoung-Ho Buh , Yu-Gyun Shin , Soo-Jin Hong , Guk-Hyon Yon
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/4983 , H01L21/28247 , H01L21/28273 , H01L21/28282 , H01L29/6659 , H01L29/7833 , H01L29/7881 , H01L29/792
摘要： A semiconductor device includes a gate structure on a channel region of a semiconductor substrate adjacent to a source/drain region therein and a surface insulation layer directly on the source/drain region of the substrate adjacent to the gate structure. The device further includes a spacer on a sidewall of the gate structure adjacent to the source/drain region. A portion of the surface insulation layer adjacent the gate structure is sandwiched between the substrate and the spacer. An interface between the surface insulation layer and the source/drain region includes a plurality of interfacial states. Portions of the source/drain region immediately adjacent the interface define a carrier accumulation layer having a greater carrier concentration than other portions thereof. The carrier accumulation layer extends along the interface under the spacer. Related methods are also discussed.
摘要翻译：半导体器件包括与半导体衬底的与源极/漏极区域相邻的沟道区域上的栅极结构，以及直接位于与栅极结构相邻的衬底的源极/漏极区域上的表面绝缘层。该器件还包括邻近源极/漏极区的栅极结构的侧壁上的间隔物。与栅极结构相邻的表面绝缘层的一部分夹在基板和间隔件之间。表面绝缘层与源极/漏极区之间的界面包括多个界面状态。紧邻界面的源极/漏极区域的部分限定了具有比其它部分更大的载流子浓度的载流子积累层。载体积聚层沿着间隔物下的界面延伸。还讨论了相关方法。

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