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1. 发明授权

US5948701A Self-aligned contact (SAC) etching using polymer-building chemistry 失效
标题翻译：使用聚合物构建化学的自对准接触（SAC）蚀刻
公开(公告)号：US5948701A
公开(公告)日：1999-09-07
申请号：US902846
申请日：1997-07-30
申请人： Simon Chooi , Mei-Sheng Zhou , Jian Xun Li
发明人： Simon Chooi , Mei-Sheng Zhou , Jian Xun Li
IPC分类号： H01L21/311 , H01L21/60 , H01L21/768 , H01L21/3065
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/76802 , H01L21/76804
摘要： A method for forming a via through a dielectric layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed upon the substrate a pair of microelectronic structures. There is then formed sequentially upon the substrate including the pair of microelectronic structures a first conformal dielectric layer followed by a second conformal dielectric layer followed by a third dielectric layer, where the second conformal dielectric layer serves as an etch stop layer with respect to the third dielectric layer in a first plasma etch method employed in forming in part a via through the third dielectric layer, the second conformal dielectric layer and the first conformal dielectric layer at a location between the pair of microelectronic structures. The first plasma etch method employs an etchant gas composition which forms a passivating fluorocarbon polymer layer upon non-horizontal portions of the third dielectric layer, the second conformal dielectric layer and the first conformal dielectric layer. There is then formed upon the third dielectric layer a patterned photoresist layer which defines the location between the pair of structures to be formed the via through the third dielectric layer, the second conformal dielectric layer and the first conformal dielectric layer. There is then etched through the first plasma etch method the third dielectric layer and the second conformal dielectric layer to form a partial via while forming the passivating fluorocarbon polymer layer upon non-horizontal portions of the third dielectric layer, the second conformal dielectric layer and the first dielectric layer. Finally, there is then etched through a second plasma etch method the first conformal dielectric layer to form the via through the third dielectric layer, the second conformal dielectric layer and the first conformal dielectric layer.
摘要翻译：在微电子学制造中通过介电层形成通孔的方法。首先提供了在微电子制造中使用的衬底。然后在衬底上形成一对微电子结构。然后在包括一对微电子结构的基板上依次形成第一共形介电层，随后是第二共形介电层，随后是第三介电层，其中第二共形绝缘层用作相对于第三绝缘层的蚀刻停止层在第一等离子体蚀刻方法中使用的介电层，其用于在所述一对微电子结构之间的位置处部分地通过所述第三介电层，所述第二共形介电层和所述第一共形介电层形成通孔。第一等离子体蚀刻方法采用蚀刻剂气体组合物，其在第三介电层，第二共形介电层和第一共形介电层的非水平部分上形成钝化氟碳聚合物层。然后在第三电介质层上形成图案化的光致抗蚀剂层，该图案化的光致抗蚀剂层限定通过第三介电层，第二共形介电层和第一共形介电层形成通孔的一对结构之间的位置。然后通过第一等离子体蚀刻方法蚀刻第三介电层和第二共形介电层以形成部分通孔，同时在第三介电层，第二共形介电层和第二保形介电层的非水平部分上形成钝化氟碳聚合物层第一电介质层。最后，然后通过第二等离子体蚀刻方法蚀刻第一共形介电层，以通过第三介电层，第二共形介电层和第一共形介电层形成通孔。

2. 发明授权

US5792692A Method of fabricating a twin hammer tree shaped capacitor structure for a dram device 失效
标题翻译：制造用于电容器的双锤树形电容器结构的方法
公开(公告)号：US5792692A
公开(公告)日：1998-08-11
申请号：US912323
申请日：1997-08-18
申请人： Jian-Xun Li , Simon Chooi , Mei-Sheng Zhou
发明人： Jian-Xun Li , Simon Chooi , Mei-Sheng Zhou
IPC分类号： H01L21/02 , H01L21/311 , H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10852 , H01L21/31116 , H01L27/10817 , H01L28/87 , H01L28/91 , H01L28/88
摘要： A process for fabricating a large surface area, storage node structure, for a DRAM device, has been developed. The storage node structure is comprised of a lower level polysilicon structure, exhibiting a "twin hammer tree" shape, and connected to an upper polysilicon level, exhibiting a "branch" type shape. The fabrication process used to create this storage node structure, features various deposition procedures, used for insulator and polysilicon layers, and various anisotropic and isotropic, dry etch procedures, as well as wet etch procedures, used for creation of the "twin hammer tree" shaped structure.
摘要翻译：已经开发了用于制造用于DRAM器件的大表面积，存储节点结构的工艺。存储节点结构包括呈现“双锤树”形状的较低级多晶硅结构，并连接到上多晶硅层，呈现“分支”型形状。用于创建这种存储节点结构的制造工艺，具有用于绝缘体和多晶硅层的各种沉积工艺以及用于创建“双锤树”的各种各向异性和各向同性的干蚀刻工艺以及湿式蚀刻工艺，形结构。

3. 发明授权

US06358842B1 Method to form damascene interconnects with sidewall passivation to protect organic dielectrics 有权
标题翻译：形成具有侧壁钝化的镶嵌互连以保护有机电介质的方法
公开(公告)号：US06358842B1
公开(公告)日：2002-03-19
申请号：US09633770
申请日：2000-08-07
申请人： Mei-Sheng Zhou , Simon Chooi , Yi Xu
发明人： Mei-Sheng Zhou , Simon Chooi , Yi Xu
IPC分类号： H01L213205
CPC分类号： H01L21/76831 , H01L21/31138 , H01L21/76808
摘要： A new method of forming a damascene interconnect in the manufacture of an integrated circuit device has been achieved. The damascene interconnect may be a single damascene or a dual damascene. Copper conductors are provided overlying a semiconductor substrate. A first passivation layer is provided overlying the copper conductors. A low dielectric constant layer is deposited overlying the first passivation layer. An optional capping layer is deposited overlying the low dielectric constant layer. A photoresist layer is deposited overlying the capping layer. The capping layer and the low dielectric constant layer are etched through to form via openings. The photoresist layer is simultaneously stripped away while forming a sidewall passivation layer on the sidewalls of the via openings using a sulfur-containing gas. Sidewall bowing and via poisoning are thereby prevented. The first passivation layer is etched through to expose the underlying copper conductors. A copper layer is deposited overlying the capping layer and filling the via openings. The copper layer is polished down to complete the damascene interconnects in the manufacture of the integrated circuit device.
摘要翻译：已经实现了在集成电路器件的制造中形成镶嵌互连的新方法。镶嵌互连可以是单镶嵌或双镶嵌。提供铜导体覆盖在半导体衬底上。第一钝化层被提供在铜导体上。沉积在第一钝化层上的低介电常数层。沉积覆盖在低介电常数层上的可选的覆盖层。沉积在覆盖层上的光致抗蚀剂层。覆盖层和低介电常数层被蚀刻通过以形成通孔。同时剥离光致抗蚀剂层，同时使用含硫气体在通路孔的侧壁上形成侧壁钝化层。从而防止侧壁弯曲和通过中毒。蚀刻第一钝化层以暴露下面的铜导体。沉积覆盖覆盖层并填充通孔的铜层。铜层被抛光以在集成电路器件的制造中完成镶嵌互连。

4. 发明授权

US06350675B1 Integration of silicon-rich material in the self-aligned via approach of dual damascene interconnects 失效
标题翻译：将富硅材料集成在双镶嵌互连的自对准通孔中
公开(公告)号：US06350675B1
公开(公告)日：2002-02-26
申请号：US09686282
申请日：2000-10-12
申请人： Simon Chooi , Mei-Sheng Zhou , Subhash Gupta , Yi Xu
发明人： Simon Chooi , Mei-Sheng Zhou , Subhash Gupta , Yi Xu
IPC分类号： H01L214763
CPC分类号： H01L21/76832 , H01L21/0274 , H01L21/31116 , H01L21/31144 , H01L21/7681 , H01L21/76825 , H01L21/76826
摘要： This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically, in the formation of self-aligned dual damascene interconnects and vias, which incorporates low dielectric constant intermetal dielectrics (IMD) and utilizes silylated top surface imaging (TSI) photoresist, with a single or multi-step selective reactive ion etch (RIE) process, to form trench/via opening. The invention incorporates the use of a silylated top surface imaging (TSI) resist etch barrier layer to form the via pattern, in the first level of a dual damascene process. Two variations of using the top surface imaging (TSI) resist, with and without leaving an exposed region in place, are described in the first and second embodiment of the invention, and in addition, a thin dielectric layer is made use of just below the resist layer. Provided adhesion between the top surface imaging (TSI) photoresist and the low dielectric constant intermetal dielectric (IMD) is good, the thin dielectric layer described above can be omitted, yielding the third and fourth embodiment of the invention. Special attention in the process is given to protecting the integrity of the low dielectric constant intermetal dielectric (ILD) material, selected from the group consisting of organic based or carbon doped silicon dioxide.
摘要翻译：本发明涉及用于半导体集成电路器件的制造方法，更具体地说，涉及形成自对准的双镶嵌互连和通孔，其结合了低介电常数金属间电介质（IMD）并利用甲硅烷基化的顶表面成像（TSI ）光致抗蚀剂，具有单步或多步选择性反应离子蚀刻（RIE）工艺，以形成沟槽/通孔。本发明包括在双镶嵌工艺的第一水平中使用甲硅烷基化的顶表面成像（TSI）抗蚀剂蚀刻阻挡层以形成通孔图案。在本发明的第一和第二实施例中描述了使用顶表面成像（TSI）抗蚀剂的两种变型，其具有和不具有将暴露区域保持在适当位置，此外，使用刚好低于抗蚀剂层。提供顶表面成像（TSI）光致抗蚀剂和低介电常数金属间电介质（IMD）之间的粘附性是好的，可以省略上述薄介电层，产生本发明的第三和第四实施例。该方法中特别注意保护低介电常数金属间电介质（ILD）材料的完整性，该材料选自有机基或掺碳二氧化硅。

5. 发明授权

US06835989B2 Methods to form dual metal gates by incorporating metals and their conductive oxides 失效
标题翻译：通过引入金属及其导电氧化物形成双金属栅极的方法
公开(公告)号：US06835989B2
公开(公告)日：2004-12-28
申请号：US10736943
申请日：2003-12-16
申请人： Wenhe Lin , Mei-Sheng Zhou , Kin Leong Pey , Simon Chooi
发明人： Wenhe Lin , Mei-Sheng Zhou , Kin Leong Pey , Simon Chooi
IPC分类号： H01L2976
CPC分类号： H01L21/823842 , H01L29/66545
摘要： Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted into the metal layer in one active area to form an implanted metal layer which is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in one active area and a metal oxide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal oxide gates wherein the oxide concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are oxygen implanted and oxidized. The PMOS gate has the higher work function.
摘要翻译：描述形成双金属栅极CMOS晶体管的方法。半导体衬底的NMOS和PMOS有源区由隔离区隔开。金属层沉积在每个有源区域中的栅极电介质层上。将氧离子注入到一个活性区域中的金属层中，以形成被氧化形成金属氧化物层的注入金属层。此后，金属层和金属氧化物层被图案化以在一个有源区域中形成金属栅极，而在另一个有源区域中形成金属氧化物栅极，其中具有较高功函数的栅极的有源区是PMOS有源区。或者，两个栅极可以是金属氧化物栅极，其中两个栅极的氧化物浓度不同。或者，可以在每个有源区域中形成伪栅极并且被电介质层覆盖。介电层被平坦化，从而暴露虚拟栅极。去除虚拟栅极留下栅极开口到半导体衬底。金属层沉积在栅极开口内的栅极电介质层上，形成金属栅极。一个或两个栅极是氧注入和氧化的。 PMOS栅极具有较高的功函数。

6. 发明授权

US06475908B1 Dual metal gate process: metals and their silicides 有权
标题翻译：双金属栅极工艺：金属及其硅化物
公开(公告)号：US06475908B1
公开(公告)日：2002-11-05
申请号：US09981415
申请日：2001-10-18
申请人： Wenhe Lin , Mei-Sheng Zhou , Kin Leong Pey , Simon Chooi
发明人： Wenhe Lin , Mei-Sheng Zhou , Kin Leong Pey , Simon Chooi
IPC分类号： H01L2144
CPC分类号： H01L29/66545 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L29/517
摘要： Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are silicon implanted and silicided. The PMOS gate has the higher work function.
摘要翻译：描述形成双金属栅极CMOS晶体管的方法。半导体衬底的NMOS和PMOS有源区由隔离区隔开。金属层沉积在每个有源区域中的栅极电介质层上。将硅离子注入到一个有源区域中的金属层中以形成硅化物以形成金属硅化物层的注入金属层。此后，金属层和金属硅化物层被图案化以在一个有源区域中形成金属栅极，在另一个有源区域中形成金属硅化物栅极，其中具有较高功函数的栅极的有源区是PMOS有源区。或者，两个栅极可以是金属硅化物栅极，其中两个栅极的硅浓度不同。或者，可以在每个有源区域中形成伪栅极并且被电介质层覆盖。介电层被平坦化，从而暴露虚拟栅极。去除虚拟栅极留下栅极开口到半导体衬底。金属层沉积在栅极开口内的栅极电介质层上，形成金属栅极。一个或两个栅极是硅植入和硅化的。 PMOS栅极具有较高的功函数。

7. 发明授权

US06429122B2 Non metallic barrier formations for copper damascene type interconnects 失效
公开(公告)号：US06429122B2
公开(公告)日：2002-08-06
申请号：US09925820
申请日：2001-08-10
申请人： Simon Chooi , Subhash Gupta , Mei-Sheng Zhou , Sangki Hong
发明人： Simon Chooi , Subhash Gupta , Mei-Sheng Zhou , Sangki Hong
IPC分类号： H01L214763
CPC分类号： H01L21/76832 , H01L21/76801 , H01L21/76807 , H01L21/76826 , H01L21/76831
摘要： A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.

8. 发明授权

US06352917B1 Reversed damascene process for multiple level metal interconnects 有权
标题翻译：用于多级金属互连的反向镶嵌工艺
公开(公告)号：US06352917B1
公开(公告)日：2002-03-05
申请号：US09598691
申请日：2000-06-21
申请人： Subhash Gupta , Mei-Sheng Zhou , Simon Chooi , Sangki Hong
发明人： Subhash Gupta , Mei-Sheng Zhou , Simon Chooi , Sangki Hong
IPC分类号： H01L214763
CPC分类号： H01L21/76885 , H01L21/76801 , H01L21/76802 , H01L21/76831 , H01L21/76834 , H01L21/76883 , H01L21/76897 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A new method of forming metal interconnect levels containing damascene interconnects and via plugs in the manufacture of an integrated circuit device has been achieved. The method creates a reversed dual damascene structure. A first dielectric layer is provided overlying a semiconductor substrate. The dielectric layer is patterned to form trenches for planned damascene interconnects. Insulating spacers may optionally be formed on the trench sidewalls. A conductive barrier layer is deposited overlying the dielectric layer and lining the trenches. A metal layer, preferably comprising copper, is deposited overlying the conductive barrier layer and filling the trenches. The metal layer and the conductive barrier layer are polished down to thereby form the damascene interconnects. A passivation layer may optionally be deposited. The damascene interconnects are patterned to form via plugs overlying the damascene interconnects. The patterning comprises partially etching down the damascene interconnects using a via mask overlying and protecting portions of the damascene interconnects. A trench mask also overlies and protects the first dielectric layer from metal contamination during the etching down.
摘要翻译：已经实现了在集成电路器件的制造中形成包含镶嵌互连和通孔插塞的金属互连级别的新方法。该方法创建一个反向的双镶嵌结构。第一电介质层设置在半导体衬底上。图案化电介质层以形成用于计划的大马士革互连的沟槽。可以可选地在沟槽侧壁上形成绝缘间隔物。导电阻挡层沉积在电介质层上并衬在沟槽上。沉积优选包含铜的金属层，覆盖在导电阻挡层上并填充沟槽。金属层和导电阻挡层被抛光，从而形成镶嵌互连。可以任选地沉积钝化层。大马士革互连被图案化以形成覆盖大马士革互连的通孔塞。图案化包括使用覆盖并保护大马士革互连部分的通孔掩模部分地蚀刻镶嵌互连。在蚀刻过程中，沟槽掩模也覆盖并保护第一介电层免受金属污染。

9. 发明授权

US06225202B1 Selective etching of unreacted nickel after salicidation 有权
标题翻译：腐蚀后对未反应的镍进行选择性蚀刻
公开(公告)号：US06225202B1
公开(公告)日：2001-05-01
申请号：US09598689
申请日：2000-06-21
申请人： Subhash Gupta , Mei-Sheng Zhou , Simon Chooi , Sangki Hong
发明人： Subhash Gupta , Mei-Sheng Zhou , Simon Chooi , Sangki Hong
IPC分类号： H01L214763
CPC分类号： H01L29/665 , C23F4/00 , H01L21/32136
摘要： A method for removing unreacted nickel or cobalt after silicidation using carbon monoxide dry stripping is described. Shallow trench isolation regions are formed in a semiconductor substrate surrounding and electrically isolating an active area from other active areas. A gate electrode and associated source and drain regions are formed in the active area wherein dielectric spacers are formed on sidewalls of the gate electrode. A nickel or cobalt layer is deposited over the gate electrode and associated source and drain regions, shallow trench isolation regions, and dielectric spacers. The semiconductor substrate is annealed whereby the nickel or cobalt layer overlying the gate electrode and said source and drain regions is transformed into a nickel or cobalt silicide layer and wherein the nickel or cobalt layer overlying the dielectric spacers and the shallow trench isolation regions is unreacted. The unreacted nickel or cobalt layer is exposed to a plasma containing carbon monoxide gas wherein the carbon monoxide gas reacts with the unreacted nickel or cobalt thereby removing the unreacted nickel or cobalt from the substrate to complete salicidation of the integrated circuit device.
摘要翻译：描述了使用一氧化碳干燥汽提在硅化后除去未反应的镍或钴的方法。在半导体衬底中形成浅沟槽隔离区域，该半导体衬底围绕并使活性区域与其它有源区域电隔离。在有源区域中形成栅电极和相关源极和漏极区，其中在栅电极的侧壁上形成有电介质间隔物。在栅极电极和相关的源极和漏极区域，浅沟槽隔离区域和介电间隔物上沉积镍或钴层。半导体衬底被退火，由此将覆盖在栅电极和所述源极和漏极区域上的镍或钴层转变成镍或钴硅化物层，并且其中覆盖电介质间隔物和浅沟槽隔离区的镍或钴层是未反应的。将未反应的镍或钴层暴露于含有一氧化碳气体的等离子体中，其中一氧化碳气体与未反应的镍或钴反应，从而从基板除去未反应的镍或钴，以完成集成电路器件的水化。

10. 发明授权

US06677652B2 Methods to form dual metal gates by incorporating metals and their conductive oxides 有权
公开(公告)号：US06677652B2
公开(公告)日：2004-01-13
申请号：US10227697
申请日：2002-08-26
申请人： Wenhe Lin , Mei-Sheng Zhou , Kin Leong Pey , Simon Chooi
发明人： Wenhe Lin , Mei-Sheng Zhou , Kin Leong Pey , Simon Chooi
IPC分类号： H01L2976
CPC分类号： H01L21/823842 , H01L29/66545
摘要： Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted into the metal layer in one active area to form an implanted metal layer which is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in one active area and a metal oxide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal oxide gates wherein the oxide concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are oxygen implanted and oxidized. The PMOS gate has the higher work function.

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