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1. 发明申请

US20080150003A1 Electron blocking layers for electronic devices 审中-公开
标题翻译：电子器件用电子阻挡层
公开(公告)号：US20080150003A1
公开(公告)日：2008-06-26
申请号：US11641956
申请日：2006-12-20
申请人： Jian Chen , Xiangfeng Duan , Karen Cruden , Chao Liu , Madhuri L. Nallabolu , Srikanth Ranganathan , Francisco Leon , J. Wallace Parce
发明人： Jian Chen , Xiangfeng Duan , Karen Cruden , Chao Liu , Madhuri L. Nallabolu , Srikanth Ranganathan , Francisco Leon , J. Wallace Parce
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/7881 , H01L29/42324 , H01L29/42332 , H01L29/517
摘要： Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multistate (e.g., two, three or four bit) operation.
摘要翻译：描述诸如非易失性存储器件的电子设备的方法和装置。存储器件包括多层控制电介质，例如双层或三层。多层控制电介质包括高k电介质材料如氧化铝（Al 2 O 3），氧化铪（HfO 2）和/或铪铝氧化物的混合膜的组合。多层控制电介质提供增强的特性，包括增加的电荷保留，增强的存储器编程/擦除窗口，改进的可靠性和稳定性，具有单或多（例如二，三或四位）操作的可行性。

2. 发明申请

US20100155786A1 Methods and devices for forming nanostructure monolayers and devices including such monolayers 有权
标题翻译：用于形成纳米结构单层的方法和装置以及包括这种单层的装置
公开(公告)号：US20100155786A1
公开(公告)日：2010-06-24
申请号：US11881739
申请日：2007-07-27
申请人： David L. Heald , Jian Chen , Karen Chu Cruden , Xiangfeng Duan , Chao Liu , Madhuri L. Nallabolu , J. Wallace Parce , Srikanth Ranganathan
发明人： David L. Heald , Jian Chen , Karen Chu Cruden , Xiangfeng Duan , Chao Liu , Madhuri L. Nallabolu , J. Wallace Parce , Srikanth Ranganathan
IPC分类号： H01L29/772 , H01L21/302 , H01L21/31
CPC分类号： H01L29/66477 , B82Y10/00 , B82Y30/00 , G03F7/0754 , G03F7/165 , G03F7/168 , H01L21/28273 , H01L21/823437 , H01L21/823828 , H01L29/42332 , H01L29/78
摘要： Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing are also provided.
摘要翻译：提供了形成或构图纳米结构阵列的方法。所述方法包括在包含纳米结构缔合基团，自旋电介质中阵列形成，纳米结构沉积后的溶剂退火，使用抗蚀剂图案化和/或使用促进阵列形成的器件的涂层上形成阵列。还提供了用于形成纳米结构阵列的相关器件，以及包括纳米结构阵列（例如，存储器件）的器件。还提供了在高温处理过程中保护纳米结构不熔化的方法。

3. 发明申请

US20110204432A1 Methods and Devices for Forming Nanostructure Monolayers and Devices Including Such Monolayers 有权
标题翻译：用于形成包括这种单层的纳米结构单层和器件的方法和装置
公开(公告)号：US20110204432A1
公开(公告)日：2011-08-25
申请号：US13098082
申请日：2011-04-29
申请人： Jian Chen , Xiangfeng Duan , Chao Liu , Madhuri L. Nallabolu , J. Wallace Parce , Srikanth Ranganathan
发明人： Jian Chen , Xiangfeng Duan , Chao Liu , Madhuri L. Nallabolu , J. Wallace Parce , Srikanth Ranganathan
IPC分类号： H01L29/792
CPC分类号： H01L29/66477 , B82Y10/00 , B82Y30/00 , G03F7/0754 , G03F7/165 , G03F7/168 , H01L21/28273 , H01L21/823437 , H01L21/823828 , H01L29/42332 , H01L29/78
摘要： Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing are also provided.
摘要翻译：提供了形成或构图纳米结构阵列的方法。所述方法包括在包含纳米结构缔合基团，自旋电介质中阵列形成，纳米结构沉积后的溶剂退火，使用抗蚀剂图案化和/或使用促进阵列形成的器件的涂层上形成阵列。还提供了用于形成纳米结构阵列的相关器件，以及包括纳米结构阵列（例如，存储器件）的器件。还提供了在高温处理过程中保护纳米结构不熔化的方法。

4. 发明授权

US07968273B2 Methods and devices for forming nanostructure monolayers and devices including such monolayers 有权
标题翻译：用于形成纳米结构单层的方法和装置以及包括这种单层的装置
公开(公告)号：US07968273B2
公开(公告)日：2011-06-28
申请号：US11881739
申请日：2007-07-27
申请人： Jian Chen , Xiangfeng Duan , Chao Liu , Madhuri L. Nallabolu , J. Wallace Parce , Srikanth Ranganathan
发明人： Jian Chen , Xiangfeng Duan , Chao Liu , Madhuri L. Nallabolu , J. Wallace Parce , Srikanth Ranganathan
IPC分类号： G03F7/26
CPC分类号： H01L29/66477 , B82Y10/00 , B82Y30/00 , G03F7/0754 , G03F7/165 , G03F7/168 , H01L21/28273 , H01L21/823437 , H01L21/823828 , H01L29/42332 , H01L29/78
摘要： Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing are also provided.
摘要翻译：提供了形成或构图纳米结构阵列的方法。所述方法包括在包含纳米结构缔合基团，自旋电介质中阵列形成，纳米结构沉积后的溶剂退火，使用抗蚀剂图案化和/或使用促进阵列形成的器件的涂层上形成阵列。还提供了用于形成纳米结构阵列的相关器件，以及包括纳米结构阵列（例如，存储器件）的器件。还提供了在高温处理过程中保护纳米结构不熔化的方法。

5. 发明申请

US20080150004A1 Electron Blocking Layers for Electronic Devices 审中-公开
公开(公告)号：US20080150004A1
公开(公告)日：2008-06-26
申请号：US11688087
申请日：2007-03-19
申请人： Jian Chen , Xiangfeng Duan , Karen Cruden , Chao Liu , Madhuri L. Nallabolu , Srikanth Ranganathan , Francisco Leon , J. Wallace Parce
发明人： Jian Chen , Xiangfeng Duan , Karen Cruden , Chao Liu , Madhuri L. Nallabolu , Srikanth Ranganathan , Francisco Leon , J. Wallace Parce
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/42332 , H01L29/517 , H01L29/7881
摘要： Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multistate (e.g., two, three or four bit) operation.

6. 发明授权

US08558304B2 Methods and devices for forming nanostructure monolayers and devices including such monolayers 有权
标题翻译：用于形成纳米结构单层的方法和装置以及包括这种单层的装置
公开(公告)号：US08558304B2
公开(公告)日：2013-10-15
申请号：US13098082
申请日：2011-04-29
申请人： Jian Chen , Xiangfeng Duan , Chao Liu , Madhuri Nallabolu , J. Wallace Parce , Srikanth Ranganathan
发明人： Jian Chen , Xiangfeng Duan , Chao Liu , Madhuri Nallabolu , J. Wallace Parce , Srikanth Ranganathan
IPC分类号： H01L29/792
CPC分类号： H01L29/66477 , B82Y10/00 , B82Y30/00 , G03F7/0754 , G03F7/165 , G03F7/168 , H01L21/28273 , H01L21/823437 , H01L21/823828 , H01L29/42332 , H01L29/78
摘要： Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing are also provided.
摘要翻译：提供了形成或构图纳米结构阵列的方法。所述方法包括在包含纳米结构缔合基团，自旋电介质中阵列形成，纳米结构沉积后的溶剂退火，使用抗蚀剂图案化和/或使用促进阵列形成的器件的涂层上形成阵列。还提供了用于形成纳米结构阵列的相关器件，以及包括纳米结构阵列（例如，存储器件）的器件。还提供了在高温处理过程中保护纳米结构不熔化的方法。

7. 发明申请

US20110034038A1 Methods and devices for forming nanostructure monolayers and devices including such monolayers 有权
标题翻译：用于形成纳米结构单层的方法和装置以及包括这种单层的装置
公开(公告)号：US20110034038A1
公开(公告)日：2011-02-10
申请号：US12803568
申请日：2010-06-29
申请人： Jian Chen , Karen Chu Cruden , Xiangfeng Duan , Chao Liu , J. Wallace Parce
发明人： Jian Chen , Karen Chu Cruden , Xiangfeng Duan , Chao Liu , J. Wallace Parce
IPC分类号： H01L21/3105
CPC分类号： H01L21/28008 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L21/28229 , H01L21/28273 , H01L21/3105 , Y10S977/774 , Y10S977/782 , Y10S977/845 , Y10S977/855 , Y10S977/89 , Y10S977/891
摘要： Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).
摘要翻译：提供了形成或构图纳米结构阵列的方法。所述方法包括在包含纳米结构缔合基团，自旋电介质中阵列形成，纳米结构沉积后的溶剂退火，使用抗蚀剂图案化和/或使用促进阵列形成的器件的涂层上形成阵列。还提供了用于形成纳米结构阵列的相关器件，以及包括纳米结构阵列（例如，存储器件）的器件。

8. 发明授权

US08507390B2 Methods and devices for forming nanostructure monolayers and devices including such monolayers 有权
标题翻译：用于形成纳米结构单层的方法和装置以及包括这种单层的装置
公开(公告)号：US08507390B2
公开(公告)日：2013-08-13
申请号：US12803568
申请日：2010-06-29
申请人： Jian Chen , Karen Chu Cruden , Xiangfeng Duan , Chao Liu , J. Wallace Parce
发明人： Jian Chen , Karen Chu Cruden , Xiangfeng Duan , Chao Liu , J. Wallace Parce
IPC分类号： H01L21/3105
CPC分类号： H01L21/28008 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L21/28229 , H01L21/28273 , H01L21/3105 , Y10S977/774 , Y10S977/782 , Y10S977/845 , Y10S977/855 , Y10S977/89 , Y10S977/891
摘要： Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).
摘要翻译：提供了形成或构图纳米结构阵列的方法。所述方法包括在包含纳米结构缔合基团，自旋电介质中阵列形成，纳米结构沉积后的溶剂退火，使用抗蚀剂图案化和/或使用促进阵列形成的器件的涂层上形成阵列。还提供了用于形成纳米结构阵列的相关器件，以及包括纳米结构阵列（例如，存储器件）的器件。

9. 发明授权

US08030161B2 Gate electrode for a nonvolatile memory cell 有权
标题翻译：用于非易失性存储单元的栅电极
公开(公告)号：US08030161B2
公开(公告)日：2011-10-04
申请号：US12121591
申请日：2008-05-15
申请人： Xiangfeng Duan , Jian Chen , J. Wallace Parce , Francisco A. Leon
发明人： Xiangfeng Duan , Jian Chen , J. Wallace Parce , Francisco A. Leon
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L29/42324 , H01L29/42332 , H01L29/7883 , H01L29/7885
摘要： A nonvolatile memory cell includes a substrate comprising a source, drain, and channel between the source and the drain. A tunnel dielectric layer overlies the channel, and a localized charge storage layer is disposed between the tunnel dielectric layer and a control dielectric layer. A gate electrode has a first surface adjacent to the control dielectric layer, and the first surface includes a midsection and two edge portions. According to one embodiment, the midsection defines a plane, and at least one edge portion extends away from the plane. Preferably, the edge portion extending away from the plane converges toward an opposing second surface of the gate electrode. According to another embodiment, the gate electrode of the nonvolatile memory cell includes a first sublayer and a second sublayer of a different width on the first sublayer.
摘要翻译：非易失性存储单元包括在源极和漏极之间包括源极，漏极和沟道的衬底。隧道介电层覆盖在沟道上，并且局部电荷存储层设置在隧道介电层和控制电介质层之间。栅电极具有与控制电介质层相邻的第一表面，并且第一表面包括中部和两个边缘部分。根据一个实施例，中段限定一个平面，并且至少一个边缘部分远离平面延伸。优选地，远离平面延伸的边缘部分朝向栅电极的相对的第二表面会聚。根据另一实施例，非易失性存储单元的栅极包括第一子层和第一子层上具有不同宽度的第二子层。

10. 发明授权

US07851841B2 Large-area nanoenabled macroelectronic substrates and uses therefor 有权
标题翻译：大面积纳米大电子基板及其用途
公开(公告)号：US07851841B2
公开(公告)日：2010-12-14
申请号：US11760382
申请日：2007-06-08
申请人： Xiangfeng Duan , Chunming Niu , Stephen A. Empedocles , Linda T. Romano , Jian Chen , Vijendra Sahi , Lawrence Bock , David P. Stumbo , J. Wallace Parce , Jay L. Goldman
发明人： Xiangfeng Duan , Chunming Niu , Stephen A. Empedocles , Linda T. Romano , Jian Chen , Vijendra Sahi , Lawrence Bock , David P. Stumbo , J. Wallace Parce , Jay L. Goldman
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L29/0665 , B82Y10/00 , H01F1/405 , H01L27/092 , H01L27/12 , H01L27/1292 , H01L29/0673 , H01L29/068 , H01L29/78696 , H01L31/035281 , H01L33/18 , H01L33/20 , H01L33/24 , H01L51/0048 , H01L51/0504 , H01L51/0545 , H01L51/0595 , Y10S977/742 , Y10S977/762 , Y10S977/781 , Y10S977/789 , Y10S977/938
摘要： A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.
摘要翻译：描述了具有多个半导体器件的电子基片的方法和装置。在衬底上形成纳米线薄膜。纳米线的薄膜形成为具有足够的纳米线密度以达到工作电流水平。在纳米线的薄膜中限定多个半导体区域。在半导体器件区域处形成触点，从而提供与多个半导体器件的电连接。此外，用于制造纳米线的各种材料，包括p掺杂纳米线和n掺杂纳米线的薄膜，纳米线异质结构，发光纳米线异质结构，用于在衬底上定位纳米线的流动掩模，用于沉积纳米线的纳米线喷涂技术，用于减少或消除声子的技术描述了纳米线中的电子散射，以及用于降低纳米线中的表面状态的技术。

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