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1. 发明授权

US08068268B2 MEMS devices having improved uniformity and methods for making them 失效
标题翻译：具有改进的均匀性的MEMS器件和制造它们的方法
公开(公告)号：US08068268B2
公开(公告)日：2011-11-29
申请号：US11773357
申请日：2007-07-03
申请人： David L Heald , Fan Zhong , Philip Don Floyd
发明人： David L Heald , Fan Zhong , Philip Don Floyd
IPC分类号： G02B26/00
CPC分类号： G02B26/001 , B81B3/0072 , B81B2201/047
摘要： Disclosed is a microelectromechanical system (MEMS) device and method of manufacturing the same. In one aspect, MEMS such as an interferometric modulator include one or more elongated interior posts and support rails supporting a deformable reflective layer, where the elongated interior posts are entirely within an interferometric cavity and aligned parallel with the support rails. In another aspect, the interferometric modulator includes one or more elongated etch release holes formed in the deformable reflective layer and aligned parallel with channels formed in the deformable reflective layer defining parallel strips of the deformable reflective layer.
摘要翻译：公开了一种微机电系统（MEMS）装置及其制造方法。在一个方面，诸如干涉式调制器的MEMS包括一个或多个细长的内部柱和支撑可变形的反射层的支撑轨道，其中细长的内部柱完全在干涉式空腔内并与支撑轨平行排列。在另一方面，干涉式调制器包括形成在可变形反射层中的一个或多个细长蚀刻释放孔，并且与形成在可变形反射层中形成的沟道平行排列，所述可变形反射层限定可变形反射层的平行条带。

2. 发明申请

US20090009444A1 MEMS DEVICES HAVING IMPROVED UNIFORMITY AND METHODS FOR MAKING THEM 失效
标题翻译：具有改进的均匀性的MEMS器件及其制造方法
公开(公告)号：US20090009444A1
公开(公告)日：2009-01-08
申请号：US11773357
申请日：2007-07-03
申请人： David L. Heald , Fan Zhong , Philip Don Floyd
发明人： David L. Heald , Fan Zhong , Philip Don Floyd
IPC分类号： G09G3/34 , B05D5/12 , G02F1/21
CPC分类号： G02B26/001 , B81B3/0072 , B81B2201/047
摘要： Disclosed is a microelectromechanical system (MEMS) device and method of manufacturing the same. In one aspect, MEMS such as an interferometric modulator include one or more elongated interior posts and support rails supporting a deformable reflective layer, where the elongated interior posts are entirely within an interferometric cavity and aligned parallel with the support rails. In another aspect, the interferometric modulator includes one or more elongated etch release holes formed in the deformable reflective layer and aligned parallel with channels formed in the deformable reflective layer defining parallel strips of the deformable reflective layer.
摘要翻译：公开了一种微机电系统（MEMS）装置及其制造方法。在一个方面，诸如干涉式调制器的MEMS包括一个或多个细长的内部柱和支撑可变形的反射层的支撑轨道，其中细长的内部柱完全在干涉式空腔内并与支撑轨平行排列。在另一方面，干涉式调制器包括形成在可变形反射层中的一个或多个细长蚀刻释放孔，并且与形成在可变形反射层中形成的沟道平行排列，所述可变形反射层限定可变形反射层的平行条带。

3. 发明授权

US07339184B2 Systems and methods for harvesting and integrating nanowires 有权
标题翻译：用于收获和整合纳米线的系统和方法
公开(公告)号：US07339184B2
公开(公告)日：2008-03-04
申请号：US11117707
申请日：2005-04-29
申请人： Linda T. Romano , Jian Chen , Xiangfeng Duan , Robert S. Dubrow , Stephen A. Empedocles , Jay L. Goldman , James M. Hamilton , David L. Heald , Francesco Lemmi , Chunming Niu , Yaoling Pan , George Pontis , Vijendra Sahi , Erik C. Scher , David P. Stumbo , Jeffery A. Whiteford
发明人： Linda T. Romano , Jian Chen , Xiangfeng Duan , Robert S. Dubrow , Stephen A. Empedocles , Jay L. Goldman , James M. Hamilton , David L. Heald , Francesco Lemmi , Chunming Niu , Yaoling Pan , George Pontis , Vijendra Sahi , Erik C. Scher , David P. Stumbo , Jeffery A. Whiteford
IPC分类号： H01L29/00
CPC分类号： C30B29/605 , B82Y10/00 , C30B11/12 , H01L21/02439 , H01L21/02513 , H01L21/02521 , H01L21/02532 , H01L21/02603 , H01L21/02606 , H01L21/02639 , H01L21/02645 , H01L21/02653 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/125 , H01L29/66469 , H01L29/775 , H01L29/78684 , H01L29/7869 , H01L29/78696 , H01L51/0048 , Y10S977/762 , Y10S977/938 , Y10T428/139 , Y10T428/2902 , Y10T428/2949
摘要： The present invention is directed to methods to harvest, integrate and exploit nanomaterials, and particularly elongated nanowire materials. The invention provides methods for harvesting nanowires that include selectively etching a sacrificial layer placed on a nanowire growth substrate to remove nanowires. The invention also provides methods for integrating nanowires into electronic devices that include placing an outer surface of a cylinder in contact with a fluid suspension of nanowires and rolling the nanowire coated cylinder to deposit nanowires onto a surface. Methods are also provided to deposit nanowires using an ink-jet printer or an aperture to align nanowires. Additional aspects of the invention provide methods for preventing gate shorts in nanowire based transistors. Additional methods for harvesting and integrating nanowires are provided.
摘要翻译：本发明涉及收获，整合和利用纳米材料，特别是细长的纳米线材料的方法。本发明提供了收获纳米线的方法，其包括选择性地蚀刻放置在纳米线生长衬底上以去除纳米线的牺牲层。本发明还提供了将纳米线整合到电子器件中的方法，包括将圆筒的外表面与纳米线的流体悬浮液接触并滚动纳米线涂覆的圆筒以将纳米线沉积到表面上。还提供了使用喷墨打印机或孔径以纳米线排列纳米线的方法。本发明的另外的方面提供了用于防止基于纳米线的晶体管中的栅极短路的方法。提供了收获和集成纳米线的其他方法。

4. 发明授权

US07595528B2 Nano-enabled memory devices and anisotropic charge carrying arrays 有权
标题翻译：具有纳米功能的存储器件和各向异性带电载体阵列
公开(公告)号：US07595528B2
公开(公告)日：2009-09-29
申请号：US11018572
申请日：2004-12-21
申请人： Xiangfeng Duan , Calvin Y. H. Chow , David L. Heald , Chunming Niu , J. Wallace Parce , David P. Stumbo
发明人： Xiangfeng Duan , Calvin Y. H. Chow , David L. Heald , Chunming Niu , J. Wallace Parce , David P. Stumbo
IPC分类号： H01L29/788
CPC分类号： G11C11/56 , B82Y10/00 , G03G5/00 , G03G5/02 , G03G5/04 , G03G5/043 , G03G5/08 , G03G5/082 , G03G5/08214 , G11C13/02 , G11C13/025 , G11C2213/17 , G11C2213/18 , G11C2216/08 , H01L21/28273 , H01L21/28282 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/42332 , H01L29/7881 , H01L29/7887 , Y10S977/936 , Y10S977/943
摘要： Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.
摘要翻译：描述了用于纳米存储器件和各向异性带电载体阵列的方法和装置。在一方面，存储器件包括衬底，衬底的源极区域和衬底的漏极区域。纳米元素的群体沉积在通道区域上方的衬底上，在一个实施方案中纳米的群体包括金属量子点。隧道介电层形成在覆盖沟道区的衬底上，金属迁移势垒层沉积在电介质层上。在纳米元件的薄膜上形成栅极接触。纳米元件允许减少横向电荷转移。存储器件可以是单个或多个存储器件。在包括具有多个离散能级的一个或多个量子点或分子的多状态存储器件中，公开了一种用于对该器件进行充电和/或放电的方法，该方法包括填充每个点或分子的多个离散能级中的每一个与一个或多个电子，并随后从一个或多个点或分子的每个离散能级一次去除单个电子。

5. 发明授权

US08143703B2 Methods and devices for forming nanostructure monolayers and devices including such monolayers 有权
标题翻译：用于形成纳米结构单层的方法和装置以及包括这种单层的装置
公开(公告)号：US08143703B2
公开(公告)日：2012-03-27
申请号：US12291101
申请日：2008-11-05
申请人： David L. Heald , Karen Chu Cruden , Xiangfeng Duan , Chao Liu , J. Wallace Parce
发明人： David L. Heald , Karen Chu Cruden , Xiangfeng Duan , Chao Liu , J. Wallace Parce
IPC分类号： H01L29/06
CPC分类号： G03F7/0757 , B82Y10/00 , B82Y30/00 , G11C13/00 , H01L21/02137 , H01L21/02282 , H01L21/02304 , H01L21/28273 , H01L21/3124 , Y10S977/755 , Y10S977/845 , Y10S977/855 , Y10S977/936 , Y10S977/938
摘要： Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).
摘要翻译：提供了形成或构图纳米结构阵列的方法。所述方法包括在包含纳米结构缔合基团的涂层上形成阵列，使用抗蚀剂进行图案化和/或使用便于阵列形成的装置。还提供了用于形成纳米结构阵列的相关器件，以及包括纳米结构阵列（例如，存储器件）的器件。

6. 发明申请

US20100155786A1 Methods and devices for forming nanostructure monolayers and devices including such monolayers 有权
标题翻译：用于形成纳米结构单层的方法和装置以及包括这种单层的装置
公开(公告)号：US20100155786A1
公开(公告)日：2010-06-24
申请号：US11881739
申请日：2007-07-27
申请人： David L. Heald , Jian Chen , Karen Chu Cruden , Xiangfeng Duan , Chao Liu , Madhuri L. Nallabolu , J. Wallace Parce , Srikanth Ranganathan
发明人： David L. Heald , Jian Chen , Karen Chu Cruden , Xiangfeng Duan , Chao Liu , Madhuri L. Nallabolu , J. Wallace Parce , Srikanth Ranganathan
IPC分类号： H01L29/772 , H01L21/302 , H01L21/31
CPC分类号： H01L29/66477 , B82Y10/00 , B82Y30/00 , G03F7/0754 , G03F7/165 , G03F7/168 , H01L21/28273 , H01L21/823437 , H01L21/823828 , H01L29/42332 , H01L29/78
摘要： Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing are also provided.
摘要翻译：提供了形成或构图纳米结构阵列的方法。所述方法包括在包含纳米结构缔合基团，自旋电介质中阵列形成，纳米结构沉积后的溶剂退火，使用抗蚀剂图案化和/或使用促进阵列形成的器件的涂层上形成阵列。还提供了用于形成纳米结构阵列的相关器件，以及包括纳米结构阵列（例如，存储器件）的器件。还提供了在高温处理过程中保护纳米结构不熔化的方法。

7. 发明授权

US07501315B2 Methods and devices for forming nanostructure monolayers and devices including such monolayers 有权
公开(公告)号：US07501315B2
公开(公告)日：2009-03-10
申请号：US11148001
申请日：2005-06-07
申请人： David L. Heald , Karen Chu Cruden , Xiangfeng Duan , Chao Liu , J. Wallace Parce
发明人： David L. Heald , Karen Chu Cruden , Xiangfeng Duan , Chao Liu , J. Wallace Parce
IPC分类号： H01L21/82 , H01L27/10
CPC分类号： G03F7/0757 , B82Y10/00 , B82Y30/00 , G11C13/00 , H01L21/02137 , H01L21/02282 , H01L21/02304 , H01L21/28273 , H01L21/3124 , Y10S977/755 , Y10S977/845 , Y10S977/855 , Y10S977/936 , Y10S977/938
摘要： Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).

8. 发明授权

US4482909A Signal equalization in quadrilinear imaging CCD arrays 失效
标题翻译：四线成像CCD阵列中的信号均衡
公开(公告)号：US4482909A
公开(公告)日：1984-11-13
申请号：US404179
申请日：1982-08-02
申请人： David L. Heald
发明人： David L. Heald
IPC分类号： H01L27/148 , H01L29/78 , G11C19/28 , H01L27/14 , H01L31/00
CPC分类号： H01L27/14825
摘要： In the operation of a high density quadrilinear CCD imaging array, photogenerate charge is transferred from the photosites, transversely through one inner CCD register to a second outer CCD register, before clocking the CCD registers. During the transfer from the inner to the outer registers, the signal charge passes through a region defined by boundaries spaced relatively widely to a region in which the boundaries are required to be spaced closely. In the latter region, two dimensional fringing fields from the boundaries elevate the minimum potential which defines the signal charge path and creates a potential step which traps a significant percentage of the signal charge. This trapping creates a large offset between the output signals from the inner and outer register. The concept proposed is to use a fat zero, i.e., an intentionally introduced small packet of charge, injected into the input of both the inner and outer CCD registers in order to totally eliminate the offset. The input structure for fat zero injection would be designed so that the size of the fat zero would be determined by the same factors creating the potential step, thereby totally eliminating any charge loss from the signal packet during the initial transfer from the photosites, and eliminating any dependance on processing variations.
摘要翻译：在高密度四线CCD成像阵列的操作中，在对CCD寄存器进行计时之前，将光生电荷从光电子元件横向通过一个内部CCD寄存器传输到第二个外部CCD寄存器。在从内部寄存器到外部寄存器的传输期间，信号电荷通过由相对广泛地间隔的边界限定的区域到需要间隔的区域。在后一个区域中，来自边界的二维边缘场提高了定义信号电荷路径的最小电位，并产生了陷阱相当大百分比的信号电荷的电位。这种捕获在内部寄存器和外部寄存器的输出信号之间产生较大的偏移量。所提出的概念是将脂肪零，即有意引入的小包电荷注入到内部和外部CCD寄存器的输入中，以便完全消除偏移。脂肪零注入的输入结构将被设计成使脂肪零点的大小由相同的因素确定，从而产生潜在的步骤，从而完全消除了在从白光初始转移过程中信号包的任何电荷损失，并消除任何依赖于处理变化。

9. 发明授权

US07382017B2 Nano-enabled memory devices and anisotropic charge carrying arrays 有权
标题翻译：具有纳米功能的存储器件和各向异性带电载体阵列
公开(公告)号：US07382017B2
公开(公告)日：2008-06-03
申请号：US11695728
申请日：2007-04-03
申请人： Xiangfeng Duan , Calvin Y. H. Cho , David L. Heald , Chunming Niu , J. Wallace Parce , David P. Stumbo
发明人： Xiangfeng Duan , Calvin Y. H. Cho , David L. Heald , Chunming Niu , J. Wallace Parce , David P. Stumbo
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , B82Y10/00 , G03G5/00 , G03G5/02 , G03G5/04 , G03G5/043 , G03G5/08 , G03G5/082 , G03G5/08214 , G11C11/56 , G11C13/02 , G11C13/025 , G11C2213/17 , G11C2213/18 , G11C2216/08 , H01L29/42332 , H01L29/7881 , H01L29/7887 , Y10S977/774 , Y10S977/785 , Y10S977/936
摘要： Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.
摘要翻译：描述了用于纳米存储器件和各向异性带电载体阵列的方法和装置。在一方面，存储器件包括衬底，衬底的源极区域和衬底的漏极区域。纳米元素的群体沉积在通道区域上方的衬底上，在一个实施方案中纳米的群体包括金属量子点。隧道介电层形成在覆盖沟道区的衬底上，金属迁移势垒层沉积在电介质层上。在纳米元件的薄膜上形成栅极接触。纳米元件允许减少横向电荷转移。存储器件可以是单个或多个存储器件。在包括具有多个离散能级的一个或多个量子点或分子的多状态存储器件中，公开了一种用于对该器件进行充电和/或放电的方法，该方法包括填充每个点或分子的多个离散能级中的每一个与一个或多个电子，并随后从一个或多个点或分子的每个离散能级一次去除单个电子。

10. 发明申请

US20090065764A1 Methods and devices for forming nanostructure monolayers and devices including such monolayers 有权
标题翻译：用于形成纳米结构单层的方法和装置以及包括这种单层的装置
公开(公告)号：US20090065764A1
公开(公告)日：2009-03-12
申请号：US12291101
申请日：2008-11-05
申请人： David L. Heald , Karen Chu Cruden , Xiangfeng Duan , Chao Liu , J. Wallace Parce
发明人： David L. Heald , Karen Chu Cruden , Xiangfeng Duan , Chao Liu , J. Wallace Parce
IPC分类号： H01L29/00 , H01L29/06
CPC分类号： G03F7/0757 , B82Y10/00 , B82Y30/00 , G11C13/00 , H01L21/02137 , H01L21/02282 , H01L21/02304 , H01L21/28273 , H01L21/3124 , Y10S977/755 , Y10S977/845 , Y10S977/855 , Y10S977/936 , Y10S977/938
摘要： Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).
摘要翻译：提供了形成或构图纳米结构阵列的方法。所述方法包括在包含纳米结构缔合基团的涂层上形成阵列，使用抗蚀剂进行图案化和/或使用便于阵列形成的装置。还提供了用于形成纳米结构阵列的相关器件，以及包括纳米结构阵列（例如，存储器件）的器件。

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