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1. 发明申请

US20090269878A1 EMBEDDED WAVEGUIDE DETECTORS 审中-公开
标题翻译：嵌入式波形检测器
公开(公告)号：US20090269878A1
公开(公告)日：2009-10-29
申请号：US12420558
申请日：2009-04-08
申请人： Francisco A. Leon , Lawrence C. West , Yuichi Wada , Gregory L. Wojcik , Stephen Moffatt
发明人： Francisco A. Leon , Lawrence C. West , Yuichi Wada , Gregory L. Wojcik , Stephen Moffatt
IPC分类号： H01L21/20
CPC分类号： G02B6/12004 , G02B2006/12061 , H01L31/0232 , H01L31/0288 , H01L31/105 , H01L31/1812 , Y02E10/50
摘要： A method of fabricating a detector that involves: forming a trench in a substrate, the substrate having an upper surface; forming a first doped semiconductor layer on the substrate and in the trench; forming a second semiconductor layer on the first doped semiconductor layer and extending into the trench, the second semiconductor layer having a conductivity that is less than the conductivity of the first doped semiconductor layer; forming a third doped semiconductor layer on the second semiconductor layer and extending into the trench; removing portions of the first, second and third layers that are above a plane defined by the surface of the substrate to produce an upper, substantially planar surface and expose an upper end of the first doped semiconductor layer in the trench; forming a first electrical contact to the first semiconductor doped layer; and forming a second electrical contact to the third semiconductor doped layer.
摘要翻译：一种制造检测器的方法，包括：在衬底中形成沟槽，所述衬底具有上表面; 在所述衬底和所述沟槽中形成第一掺杂半导体层; 在所述第一掺杂半导体层上形成第二半导体层并延伸到所述沟槽中，所述第二半导体层的导电率小于所述第一掺杂半导体层的导电性; 在所述第二半导体层上形成第三掺杂半导体层并延伸到所述沟槽中; 去除在由衬底的表面限定的平面之上的第一层，第二层和第三层的部分，以产生上部基本平坦的表面，并且暴露沟槽中的第一掺杂半导体层的上端; 形成第一电接触到第一半导体掺杂层; 以及向所述第三半导体掺杂层形成第二电接触。

2. 发明申请

US20080290394A1 GATE ELECTRODE FOR A NONVOLATILE MEMORY CELL 有权
标题翻译：用于非易失性存储单元的门电极
公开(公告)号：US20080290394A1
公开(公告)日：2008-11-27
申请号：US12121591
申请日：2008-05-15
申请人： Xiangfeng DUAN , Jian Chen , J. Wallace Parce , Francisco A. Leon
发明人： Xiangfeng DUAN , Jian Chen , J. Wallace Parce , Francisco A. Leon
IPC分类号： H01L29/00 , H01L21/3205
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L29/42324 , H01L29/42332 , H01L29/7883 , H01L29/7885
摘要： A nonvolatile memory cell includes a substrate comprising a source, drain, and channel between the source and the drain. A tunnel dielectric layer overlies the channel, and a localized charge storage layer is disposed between the tunnel dielectric layer and a control dielectric layer. A gate electrode has a first surface adjacent to the control dielectric layer, and the first surface includes a midsection and two edge portions. According to one embodiment, the midsection defines a plane, and at least one edge portion extends away from the plane. Preferably, the edge portion extending away from the plane converges toward an opposing second surface of the gate electrode. According to another embodiment, the gate electrode of the nonvolatile memory cell includes a first sublayer and a second sublayer of a different width on the first sublayer.
摘要翻译：非易失性存储单元包括在源极和漏极之间包括源极，漏极和沟道的衬底。隧道介电层覆盖在沟道上，并且局部电荷存储层设置在隧道介电层和控制电介质层之间。栅电极具有与控制电介质层相邻的第一表面，并且第一表面包括中部和两个边缘部分。根据一个实施例，中段限定一个平面，并且至少一个边缘部分远离平面延伸。优选地，远离平面延伸的边缘部分朝向栅电极的相对的第二表面会聚。根据另一实施例，非易失性存储单元的栅电极包括第一子层和第一子层上具有不同宽度的第二子层。

3. 发明授权

US06730988B2 Method of fabrication to sharpen corners of Y-branches in integrated optical components and other micro-devices 有权
公开(公告)号：US06730988B2
公开(公告)日：2004-05-04
申请号：US10338435
申请日：2003-01-08
申请人： Francisco A. Leon , Everett X. Wang
发明人： Francisco A. Leon , Everett X. Wang
IPC分类号： H01L2906
CPC分类号： G02B6/136 , G02B6/125 , G02B2006/1213
摘要： Substantially sharp corners for optical waveguides in integrated optical devices, photonic crystal devices, or for micro-devices, can be fabricated. Non-sharp corners such as rounded corners, are first formed using lithographic patterning and vertical etching. Next, isotropic etching is used to sharpen the rounded corners. A monitor can be used to determine if the rounded corners have been sufficiently sharpened by the isotropic etching.

4. 发明授权

US5367465A Solids surface grid generation for three-dimensional topography simulation 失效
标题翻译：固体表面网格生成用于三维地形模拟
公开(公告)号：US5367465A
公开(公告)日：1994-11-22
申请号：US904005
申请日：1992-06-24
申请人： Satoshi Tazawa , Kazuyuki Saito , Francisco A. Leon
发明人： Satoshi Tazawa , Kazuyuki Saito , Francisco A. Leon
IPC分类号： H01L21/302 , G06F17/50 , G06T17/20 , H01L21/3065 , G06F15/72
CPC分类号： G06T17/20
摘要： A method for creating regular triangular grid representations of a solid surface from a representation comprised of a plurality of polygons. Such a regular grid is necessary in order to accurately deform a solid during simulation of a process step. The method of the preferred embodiment is comprised generally of the steps of: removing any holes defined by the polygon face; placing a new edge between a first and second vertex of the polygon face; discarding the new edge if the new edge lies outside the polygon face or if the new edge intersects an existing edge of the polygon face; adding the new edge to the polygon face if the new edge does not lie outside the polygon face; identifying a triangle being created by the new edge and existing edges of the polygon; forming a new polygon face from the edges creating a triangle; and repeating the above steps until all polygon faces are triangulated. Once the triangulation of the polygons is completed, adjustments to the triangles is made in order to have only triangles of uniform size.
摘要翻译：一种从由多个多边形构成的表示形成固体表面的规则三角形网格表示的方法。为了在模拟过程步骤期间准确地变形固体，需要这样的规则网格。优选实施例的方法通常包括以下步骤：去除由多边形面限定的任何孔; 在多边形面的第一和第二顶点之间放置新的边缘; 如果新边缘位于多边形面之外或如果新边缘与多边形面的现有边缘相交，则丢弃新边缘; 如果新边缘不在多边形面之外，则将新边添加到多边形面; 识别由新边缘和多边形的现有边缘创建的三角形; 从边缘形成新的多边形面，创建三角形; 并重复上述步骤直到所有多边形面被三角测量。一旦完成了多边形的三角测量，就可以对三角形进行调整，以便仅具有均匀尺寸的三角形。

5. 发明授权

US08030161B2 Gate electrode for a nonvolatile memory cell 有权
标题翻译：用于非易失性存储单元的栅电极
公开(公告)号：US08030161B2
公开(公告)日：2011-10-04
申请号：US12121591
申请日：2008-05-15
申请人： Xiangfeng Duan , Jian Chen , J. Wallace Parce , Francisco A. Leon
发明人： Xiangfeng Duan , Jian Chen , J. Wallace Parce , Francisco A. Leon
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L29/42324 , H01L29/42332 , H01L29/7883 , H01L29/7885
摘要： A nonvolatile memory cell includes a substrate comprising a source, drain, and channel between the source and the drain. A tunnel dielectric layer overlies the channel, and a localized charge storage layer is disposed between the tunnel dielectric layer and a control dielectric layer. A gate electrode has a first surface adjacent to the control dielectric layer, and the first surface includes a midsection and two edge portions. According to one embodiment, the midsection defines a plane, and at least one edge portion extends away from the plane. Preferably, the edge portion extending away from the plane converges toward an opposing second surface of the gate electrode. According to another embodiment, the gate electrode of the nonvolatile memory cell includes a first sublayer and a second sublayer of a different width on the first sublayer.
摘要翻译：非易失性存储单元包括在源极和漏极之间包括源极，漏极和沟道的衬底。隧道介电层覆盖在沟道上，并且局部电荷存储层设置在隧道介电层和控制电介质层之间。栅电极具有与控制电介质层相邻的第一表面，并且第一表面包括中部和两个边缘部分。根据一个实施例，中段限定一个平面，并且至少一个边缘部分远离平面延伸。优选地，远离平面延伸的边缘部分朝向栅电极的相对的第二表面会聚。根据另一实施例，非易失性存储单元的栅极包括第一子层和第一子层上具有不同宽度的第二子层。

6. 发明授权

US07151881B2 Impurity-based waveguide detectors 失效
标题翻译：基于杂质的波导检测器
公开(公告)号：US07151881B2
公开(公告)日：2006-12-19
申请号：US10856127
申请日：2004-05-28
申请人： Lawrence C. West , Thomas P. Pearsall , Francisco A. Leon , Stephen Moffatt
发明人： Lawrence C. West , Thomas P. Pearsall , Francisco A. Leon , Stephen Moffatt
IPC分类号： G02B6/10
CPC分类号： G02B6/42 , G02B6/136 , G02B2006/12123 , H01L31/02327 , H01L31/0312 , H01L31/09 , H01L31/105 , H01L31/1105 , H01L31/1812 , Y02E10/50
摘要： An optical circuit including a semiconductor substrate; an optical waveguide formed in or on the substrate; and an optical detector formed in or on the semiconductor substrate, wherein the optical detector is aligned with the optical waveguide so as to receive an optical signal from the optical waveguide during operation, and wherein the optical detector has: a first electrode; a second electrode; and an intermediate layer between the first and second electrodes, the intermediate layer being made of a semiconductor material characterized by a conduction band, a valence band, and deep level energy states introduced between the conduction and valence bands.
摘要翻译：一种包括半导体衬底的光学电路; 形成在基板中或基板上的光波导; 以及形成在所述半导体衬底中或之上的光学检测器，其中所述光学检测器与所述光波导对准，以便在操作期间从所述光波导接收光信号，并且其中所述光学检测器具有：第一电极; 第二电极; 以及在所述第一和第二电极之间的中间层，所述中间层由导电带和导带之间引入的导带，价带和深能级状态的半导体材料制成。

7. 发明授权

US07075165B2 Embedded waveguide detectors 失效
标题翻译：嵌入式波导检测器
公开(公告)号：US07075165B2
公开(公告)日：2006-07-11
申请号：US10856750
申请日：2004-05-28
申请人： Francisco A. Leon , Lawrence C. West , Yuichi Wada , Gregory L. Wojcik , Stephen Moffatt
发明人： Francisco A. Leon , Lawrence C. West , Yuichi Wada , Gregory L. Wojcik , Stephen Moffatt
IPC分类号： H01L31/075
CPC分类号： G02B6/12004 , G02B2006/12061 , H01L31/0232 , H01L31/0288 , H01L31/105 , H01L31/1812 , Y02E10/50
摘要： A method of fabricating a detector that involves: forming a trench in a substrate, the substrate having an upper surface; forming a first doped semiconductor layer on the substrate and in the trench; forming a second semiconductor layer on the first doped semiconductor layer and extending into the trench, the second semiconductor layer having a conductivity that is less than the conductivity of the first doped semiconductor layer; forming a third doped semiconductor layer on the second semiconductor layer and extending into the trench; removing portions of the first, second and third layers that are above a plane defined by the surface of the substrate to produce an upper, substantially planar surface and expose an upper end of the first doped semiconductor layer in the trench; forming a first electrical contact to the first semiconductor doped layer; and forming a second electrical contact to the third semiconductor doped layer.
摘要翻译：一种制造检测器的方法，包括：在衬底中形成沟槽，所述衬底具有上表面; 在所述衬底和所述沟槽中形成第一掺杂半导体层; 在所述第一掺杂半导体层上形成第二半导体层并延伸到所述沟槽中，所述第二半导体层的导电率小于所述第一掺杂半导体层的导电性; 在所述第二半导体层上形成第三掺杂半导体层并延伸到所述沟槽中; 去除在由衬底的表面限定的平面之上的第一层，第二层和第三层的部分，以产生上部基本平坦的表面，并且暴露沟槽中的第一掺杂半导体层的上端; 形成第一电接触到第一半导体掺杂层; 以及向所述第三半导体掺杂层形成第二电接触。

8. 发明授权

US07001788B2 Maskless fabrication of waveguide mirrors 失效
标题翻译：波导镜无掩模制造
公开(公告)号：US07001788B2
公开(公告)日：2006-02-21
申请号：US10858524
申请日：2004-05-28
申请人： Francisco A. Leon , Lawrence C. West , Gregory L. Wojcik , Yuichi Wada
发明人： Francisco A. Leon , Lawrence C. West , Gregory L. Wojcik , Yuichi Wada
IPC分类号： H01L21/00
CPC分类号： G02B6/12004 , G02B6/122 , G02B6/132 , G02B6/136 , G02B2006/121 , G02B2006/12104
摘要： A method of fabricating a waveguide mirror that involves etching a trench in a silicon substrate; depositing a film (e.g. silicon dioxide) over the surface of the silicon substrate and into the trench; ion etching the film to remove at least some of the deposited silicon dioxide and to leave a facet of film in inside corners of the trench; depositing a layer of SiGe over the substrate to fill up the trench; and planarizing the deposited SiGe to remove the SiGe from above the level of the trench.
摘要翻译：一种制造波导反射镜的方法，涉及蚀刻硅衬底中的沟槽; 在硅衬底的表面上沉积膜（例如二氧化硅）并进入沟槽; 离子蚀刻膜以去除沉积的二氧化硅中的至少一些并且在沟槽的内部角落留下膜的小面; 在衬底上沉积一层SiGe以填充沟槽; 并且平坦化沉积的SiGe以从沟槽的高度上方除去SiGe。

9. 发明授权

US5377118A Method for accurate calculation of vertex movement for three-dimensional topography simulation 失效
标题翻译：用于三维地形模拟的顶点运动的精确计算方法
公开(公告)号：US5377118A
公开(公告)日：1994-12-27
申请号：US252062
申请日：1994-06-01
申请人： Francisco A. Leon , Donald L. Scharfetter , Satoshi Tazawa , Kazuyuki Saito , Akira Yoshii
发明人： Francisco A. Leon , Donald L. Scharfetter , Satoshi Tazawa , Kazuyuki Saito , Akira Yoshii
IPC分类号： G06F17/50 , G06F19/00 , G06T17/20 , H01L21/00 , G06F15/46 , G06F15/72
CPC分类号： G06T17/20 , G06F17/5018 , G06F2217/74
摘要： A method for accurately calculating the movement of a vertex in a three-dimensional (3-D) topography simulator. The method is particularly suited for calculating vertex movement for cases in which etch/deposition rate depends on the angle between the surface normal and the vertical direction. A workpiece is represented as a collection of material solids. Each of the material solids has a boundary model representation. The method of the present invention is comprised primarily of the steps of: advancing edges and surface planes adjacent to the vertex, creating a set of 2-D solutions by clipping with pairs of adjacent surface planes; creating a set of combined 2-D solutions by clipping invalid sections of combined 2-D solutions; construct an arbitrary vertical plane that intersects the surface at the vertex point; constructing vertex trajectories for the vertex to be moved; and clipping constructed vertex trajectories at intersections of created surface and the constructed vertical plane.
摘要翻译：一种精确计算三维（3-D）地形模拟器中顶点移动的方法。该方法特别适合于在蚀刻/沉积速率取决于表面法线和垂直方向之间的角度的情况下计算顶点移动。工件被表示为材料固体的集合。每个材料实体都具有边界模型表示。本发明的方法主要包括以下步骤：使靠近顶点的边缘和表面平行前进，通过相邻的表面平面对剪切形成一组二维解; 通过剪切合并的2-D解决方案的无效部分创建一组组合的二维解决方案; 构造在顶点与表面相交的任意垂直平面; 构造要移动的顶点的顶点轨迹; 并在创建的表面和构造的垂直平面的交点处剪切构造的顶点轨迹。

10. 发明授权

US07205624B2 Self-aligned implanted waveguide detector 失效
标题翻译：自对准植入波导检测器
公开(公告)号：US07205624B2
公开(公告)日：2007-04-17
申请号：US10959897
申请日：2004-10-06
申请人： Francisco A. Leon , Lawrence C. West
发明人： Francisco A. Leon , Lawrence C. West
IPC分类号： H01L31/00
CPC分类号： H01L31/035254 , B82Y20/00 , G02B6/12004
摘要： A method of fabricating a detector, the method including forming an island of detector core material on a substrate, the island having a horizontally oriented top end, a vertically oriented first sidewall, and a vertically oriented second sidewall that is opposite said first sidewall; implanting a first dopant into the first sidewall to form a first conductive region that has a top end that is part of the top end of the island; implanting a second dopant into the second sidewall to form a second conductive region that has a top end that is part of the top end of the island; fabricating a first electrical connection to the top end of the first conductive region; and fabricating a second electrical connection to the top end of the second conductive region.
摘要翻译：一种制造检测器的方法，所述方法包括在衬底上形成检测器芯材料岛，所述岛具有水平取向的顶端，垂直取向的第一侧壁和与所述第一侧壁相对的垂直取向的第二侧壁; 将第一掺杂剂注入到所述第一侧壁中以形成具有作为所述岛的顶端的一部分的顶端的第一导电区域; 将第二掺杂剂注入所述第二侧壁中以形成具有作为所述岛的顶端的一部分的顶端的第二导电区域; 制造到第一导电区域的顶端的第一电连接; 以及制造到所述第二导电区域的顶端的第二电连接。

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