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    • 2. 发明授权
    • Fully asynchronous interface with programmable metastability settling
time synchronizer
    • 具有可编程亚稳态建立时间同步器的完全异步接口
    • US5598113A
    • 1997-01-28
    • US375361
    • 1995-01-19
    • Jerry JexCharles DikeKeith Self
    • Jerry JexCharles DikeKeith Self
    • G06F5/06H04J3/04H03K19/00H03K5/135
    • G06F5/06H04J3/047
    • A fully asynchronous parallel synchronizer having staged write and read enables and an asynchronous interface for same. The asynchronous interface can be used to interconnect two processor systems (e.g., within a multiple processor system or a parallel processor system). The parallel programmable synchronizer contains n latches coupled in parallel having n individual enable lines having staggered enable signals. The latches are coupled such that they output to a multiplexing circuit that also receives individual staggered read enable signals which are based on the write enable signals. According to the parallel programmable synchronizer, data is written into a particular latch in clock cycle (i) just after other data was read from the same particular latch in a just prior clock cycle (i-1). While the synchronizer contains n latches, the number of latches used, x, for any particular embodiment is programmable and the enable signals adjust to accommodate the number of latches selected. The settling time for the synchronizer is therefore programmable while the synchronizer also provides a maximum throughput frequency (sampling rate). A novel empty flag generation is also described.
    • 具有分级写入和读取功能的完全异步并行同步器使能和异步接口相同。 异步接口可用于互连两个处理器系统(例如,在多处理器系统或并行处理器系统内)。 并行可编程同步器包含并联耦合的n个锁存器,其具有具有交错使能信号的n个单独使能线。 锁存器被耦合,使得它们输出到多路复用电路,该多路复用电路还接收基于写入使能信号的单独的交错读取使能信号。 根据并行可编程同步器,在紧随其后的时钟周期(i-1)中从相同的特定锁存器读取其它数据之后,数据被写入时钟周期(i)中的特定锁存器。 虽然同步器包含n个锁存器,但是对于任何特定实施例,所使用的锁存器的数量x是可编程的,并且使能信号被调整以适应所选择的锁存器的数量。 因此,同步器的建立时间是可编程的,而同步器也提供最大吞吐量频率(采样率)。 还描述了一个新的空旗生成。