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1. 发明申请

US20050018761A1 Transmitters providing cycle encoded signals 有权
标题翻译：发射机提供循环编码信号
公开(公告)号：US20050018761A1
公开(公告)日：2005-01-27
申请号：US10625945
申请日：2003-07-23
申请人： Jerry Jex , Jed Griffin , Arnaud Forestier , Kersi Vakil , Abhimanyu Kolla
发明人： Jerry Jex , Jed Griffin , Arnaud Forestier , Kersi Vakil , Abhimanyu Kolla
IPC分类号： H04L27/24 , H04B1/38
CPC分类号： H04L25/4904 , H04L25/0272 , H04L27/24
摘要： In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal. Still other embodiments are described and claimed.
摘要翻译：在一些实施例中，本发明包括发射机，其包括用于接收数据输入信号的周期编码电路，并通过连续地连接不同编码信号的部分来响应于此提供全周期编码信号。编码信号中的一些具有与编码信号的其他编码信号不同的频率，并且一些编码信号与编码信号的其它信号具有不同的相位。数据在全周期编码信号的数据时间段中表示，并且没有数据时间段具有多于一个编码信号的周期。在一些实施例中，接收器接收周期编码信号并恢复数据输入信号的数据。还描述和要求保护其他实施例。

2. 发明申请

US20080101505A1 RECEIVERS FOR CYCLE ENCODED SIGNALS 有权
标题翻译：循环编码信号的接收器
公开(公告)号：US20080101505A1
公开(公告)日：2008-05-01
申请号：US11925474
申请日：2007-10-26
申请人： Jed Griffin , Jerry Jex , Arnaud Forestier , Kersi Vakil , Abhimanyu Kolla
发明人： Jed Griffin , Jerry Jex , Arnaud Forestier , Kersi Vakil , Abhimanyu Kolla
IPC分类号： H04L7/00 , H04L27/06
CPC分类号： H04L27/24 , H04L1/06 , H04L25/4904
摘要： In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.
摘要翻译：在一些实施例中，本发明包括发射机，其包括用于接收数据输入信号的周期编码电路，并通过连续地连接不同编码信号的部分来响应于此提供全周期编码信号。编码信号中的一些具有与编码信号的其他编码信号不同的频率，并且一些编码信号与编码信号的其它信号具有不同的相位。数据在全周期编码信号的数据时间段中表示，并且没有数据时间段具有多于一个编码信号的周期。在一些实施例中，接收器接收周期编码信号并恢复数据输入信号的数据。

3. 发明申请

US20050018779A1 Receivers for cycle encoded signals 有权
标题翻译：接收器用于循环编码信号
公开(公告)号：US20050018779A1
公开(公告)日：2005-01-27
申请号：US10625944
申请日：2003-07-23
申请人： Jed Griffin , Jerry Jex , Arnaud Forestier , Kersi Vakil , Abhimanyu Kolla
发明人： Jed Griffin , Jerry Jex , Arnaud Forestier , Kersi Vakil , Abhimanyu Kolla
IPC分类号： H04L1/06 , H04L25/49 , H04L27/24 , H04L27/00
CPC分类号： H04L27/24 , H04L1/06 , H04L25/4904
摘要： In some embodiments, the inventions include a receiver to receive a full cycle encoded signal in which data is represented in data time segments and no data time segment has more than one cycle. The receiver provides a data output signal responsive to the full cycle encoding signal. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，本发明包括接收器，用于接收全周期编码信号，其中在数据时间段中表示数据，并且没有数据时间段具有多于一个周期。接收机响应于全周期编码信号提供数据输出信号。描述和要求保护其他实施例。

4. 发明申请

US20050280452A1 Interpolator testing system 失效
标题翻译：内插测试系统
公开(公告)号：US20050280452A1
公开(公告)日：2005-12-22
申请号：US10869573
申请日：2004-06-16
申请人： Kersi Vakil , Adarsh Panikkar , Abhimanyu Kolla , Arnaud Forestier
发明人： Kersi Vakil , Adarsh Panikkar , Abhimanyu Kolla , Arnaud Forestier
IPC分类号： G01R31/317 , G11C29/02 , H03K5/00 , H03K5/13 , H03L7/00
CPC分类号： G01R31/31727 , G11C29/02 , G11C29/023 , H03K5/13 , H03K2005/00052
摘要： According to some embodiments, a device includes an interpolator to receive at least a first clock signal having a first clock phase and to receive a second clock signal having a second clock phase. The interpolator may include a first plurality of interpolator legs associated with the first clock signal, a second plurality of interpolator legs associated with the second clock signal, and an output node to provide an output clock signal having an output clock phase based on the first clock signal, the second clock signal, and on a number of the first plurality and the second plurality of interpolator legs that are activated. The device may also include an interpolator control to activate only one of the first plurality and the second plurality of interpolator legs.
摘要翻译：根据一些实施例，一种设备包括内插器，用于接收具有第一时钟相位的至少第一时钟信号并且接收具有第二时钟相位的第二时钟信号。内插器可以包括与第一时钟信号相关联的第一多个内插器支路，与第二时钟信号相关联的第二多个内插器支路，以及输出节点，用于提供具有基于第一时钟的输出时钟相位的输出时钟信号信号，第二时钟信号，以及被激活的多个第一和第二多个内插器支路的数量。该装置还可以包括内插器控制，以仅激活第一多个和第二多个内插器腿中的一个。

5. 发明申请

US20050285652A1 Interpolator linearity testing system 失效
标题翻译：内插线性度测试系统
公开(公告)号：US20050285652A1
公开(公告)日：2005-12-29
申请号：US10879676
申请日：2004-06-29
申请人： Adarsh Panikkar , Kersi Vakil , Abhimanyu Kolla , Arnaud Forestier
发明人： Adarsh Panikkar , Kersi Vakil , Abhimanyu Kolla , Arnaud Forestier
IPC分类号： H03K5/00 , H03K5/13 , H03K5/135 , H03K5/22 , H03L7/081 , H03L7/091
CPC分类号： H03L7/0814 , H03K5/133 , H03K5/135 , H03K2005/00156 , H03L7/091
摘要： According to some embodiments, an interpolated clock signal having a first frequency is received, and the interpolated clock signal is periodically sampled based on a reference clock signal to generate periodically-sampled values, the reference clock signal having substantially the first frequency. A phase of the interpolated clock signal may be set to a phase degree at which the periodically-sampled values resolve to more than one value, and the phase of the interpolated clock signal may be incrementally changed until the periodically-sampled values resolve to one value. A non-linearity of the interpolated clock signal may be determined based on the number of incremental changes.
摘要翻译：根据一些实施例，接收具有第一频率的内插时钟信号，并且基于参考时钟信号周期性地采样内插时钟信号，以产生周期性采样的值，该参考时钟信号基本上具有第一频率。内插时钟信号的相位可以被设置为周期采样值解析为多于一个值的相位程度，并且内插时钟信号的相位可以被增量地改变，直到周期性采样值解析为一个值。内插时钟信号的非线性可以基于增量变化的数量来确定。

6. 发明授权

US06549031B1 Point to point alternating current (AC) impedance compensation for impedance mismatch 有权
标题翻译：阻抗匹配的点对点交流（AC）阻抗补偿
公开(公告)号：US06549031B1
公开(公告)日：2003-04-15
申请号：US10002418
申请日：2001-11-13
申请人： Jerry G. Jex , Arnaud Forestier , Kersi Vakil , Abhimanyu Kolla
发明人： Jerry G. Jex , Arnaud Forestier , Kersi Vakil , Abhimanyu Kolla
IPC分类号： H03K1716
CPC分类号： H04L25/0278 , H05K1/0237 , H05K1/148
摘要： Point-to-point AC impedance compensation calculates and matches AC impedance for integrated circuit input and output buffers, taking into consideration impedances of printed circuit boards, connectors, cards, cables, and/or other interfaces on a computer bus, upon computer system power-up or on demand during operation using no additional package pins or traces in the printed circuit board, connector, card, or cable.
摘要翻译：考虑到计算机系统电源上的印刷电路板，连接器，卡，电缆和/或计算机总线上的其他接口的阻抗，点对点交流阻抗补偿计算并匹配集成电路输入和输出缓冲器的交流阻抗在操作期间不需要额外的封装引脚或迹线，在印刷电路板，连接器，卡或电缆中。

7. 发明授权

US07009431B2 Interpolator linearity testing system 失效
标题翻译：内插线性度测试系统
公开(公告)号：US07009431B2
公开(公告)日：2006-03-07
申请号：US10879676
申请日：2004-06-29
申请人： Adarsh Panikkar , Kersi H. Vakil , Abhimanyu Kolla , Arnaud Forestier
发明人： Adarsh Panikkar , Kersi H. Vakil , Abhimanyu Kolla , Arnaud Forestier
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03K5/133 , H03K5/135 , H03K2005/00156 , H03L7/091
摘要： According to some embodiments, an interpolated clock signal having a first frequency is received, and the interpolated clock signal is periodically sampled based on a reference clock signal to generate periodically-sampled values, the reference clock signal having substantially the first frequency. A phase of the interpolated clock signal may be set to a phase degree at which the periodically-sampled values resolve to more than one value, and the phase of the interpolated clock signal may be incrementally changed until the periodically-sampled values resolve to one value. A non-linearity of the interpolated clock signal may be determined based on the number of incremental changes.
摘要翻译：根据一些实施例，接收具有第一频率的内插时钟信号，并且基于参考时钟信号周期性地采样内插时钟信号，以产生周期性采样的值，该参考时钟信号基本上具有第一频率。内插时钟信号的相位可以被设置为周期采样值解析为多于一个值的相位程度，并且内插时钟信号的相位可以被增量地改变，直到周期性采样值解析为一个值。内插时钟信号的非线性可以基于增量变化的数量来确定。

8. 发明授权

US07043392B2 Interpolator testing system 失效
标题翻译：内插测试系统
公开(公告)号：US07043392B2
公开(公告)日：2006-05-09
申请号：US10869573
申请日：2004-06-16
申请人： Kersi H. Vakil , Adarsh Panikkar , Abhimanyu Kolla , Arnaud Forestier
发明人： Kersi H. Vakil , Adarsh Panikkar , Abhimanyu Kolla , Arnaud Forestier
IPC分类号： G06F1/12
CPC分类号： G01R31/31727 , G11C29/02 , G11C29/023 , H03K5/13 , H03K2005/00052
摘要： According to some embodiments, a device includes an interpolator to receive at least a first clock signal having a first clock phase and to receive a second clock signal having a second clock phase. The interpolator may include a first plurality of interpolator legs associated with the first clock signal, a second plurality of interpolator legs associated with the second clock signal, and an output node to provide an output clock signal having an output clock phase based on the first clock signal, the second clock signal, and on a number of the first plurality and the second plurality of interpolator legs that are activated. The device may also include an interpolator control to activate only one of the first plurality and the second plurality of interpolator legs.
摘要翻译：根据一些实施例，一种设备包括内插器，用于接收具有第一时钟相位的至少第一时钟信号并且接收具有第二时钟相位的第二时钟信号。内插器可以包括与第一时钟信号相关联的第一多个内插器支路，与第二时钟信号相关联的第二多个内插器支路，以及输出节点，用于提供具有基于第一时钟的输出时钟相位的输出时钟信号信号，第二时钟信号，以及被激活的多个第一和第二多个内插器支路的数量。该装置还可以包括内插器控制，以仅激活第一多个和第二多个内插器腿中的一个。

9. 发明申请

US20080130815A1 Selective tracking of serial communication link data 审中-公开
标题翻译：选择性跟踪串行通信链路数据
公开(公告)号：US20080130815A1
公开(公告)日：2008-06-05
申请号：US11633917
申请日：2006-12-05
申请人： S. Reji Kumar , Arnaud Forestier , Adarsh Panikkar , Kersi H. Vakil
发明人： S. Reji Kumar , Arnaud Forestier , Adarsh Panikkar , Kersi H. Vakil
IPC分类号： H03D3/24
CPC分类号： H03C5/00
摘要： Embodiments to selectively track serial communication link data are presented herein.
摘要翻译：本文给出了选择性跟踪串行通信链路数据的实施例。

10. 发明授权

US06922077B2 Hybrid compensated buffer design 有权
标题翻译：混合补偿缓冲设计
公开(公告)号：US06922077B2
公开(公告)日：2005-07-26
申请号：US10608633
申请日：2003-06-27
申请人： James E. Chandler , John F. Zumkehr , Arnaud Forestier
发明人： James E. Chandler , John F. Zumkehr , Arnaud Forestier
IPC分类号： H03K19/00 , H03K19/003
CPC分类号： H03K19/0005
摘要： According to one embodiment of the present invention, a circuit is disclosed. The circuit includes a plurality of driver slices, a portion of the plurality of the devices being used to provide a target impedance; a digital matching logic to select the portion of the plurality of the driver slices; and an analog matching circuit to produce a bias voltage to match pull-up and pull-down.
摘要翻译：根据本发明的一个实施例，公开了一种电路。电路包括多个驱动器片，多个器件的一部分用于提供目标阻抗; 数字匹配逻辑，用于选择所述多个所述驱动器片段的所述部分; 以及模拟匹配电路，以产生一个偏置电压，以匹配上拉和下拉。

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