专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07157947B2 Power supplies noise detector for integrated circuits 失效
标题翻译：集成电路用电源噪声检测器
公开(公告)号：US07157947B2
公开(公告)日：2007-01-02
申请号：US10731393
申请日：2003-12-09
申请人： Chaiyuth Chansungsan , Keith Self
发明人： Chaiyuth Chansungsan , Keith Self
IPC分类号： H03K4/06 , H03K3/02
CPC分类号： G01R19/16552 , H04B15/005
摘要： In some embodiments, a circuit includes a reference current source to provide a substantially noise free current signal, and a detector coupled to one or two power supplies. In some embodiments, a method includes receiving a substantially noise free current signal, receiving one or two power supply signals, processing the substantially noise free current signal and the one or two power supply signals to detect a noise signal in the one or two power supply signals, and generating a noise detection signal in response to detection of the noise signal.
摘要翻译：在一些实施例中，电路包括参考电流源以提供基本上无噪声的电流信号，以及耦合到一个或两个电源的检测器。在一些实施例中，一种方法包括接收基本无噪声的电流信号，接收一个或两个电源信号，处理基本上无噪声的电流信号和一个或两个电源信号以检测一个或两个电源中的噪声信号信号，并且响应于噪声信号的检测而产生噪声检测信号。

2. 发明授权

US06721918B2 Method and apparatus for encoding a bus to minimize simultaneous switching outputs effect 有权
标题翻译：用于编码总线以最小化同时切换输出效果的方法和装置
公开(公告)号：US06721918B2
公开(公告)日：2004-04-13
申请号：US09750297
申请日：2000-12-29
申请人： Keith Self , John Urbanski
发明人： Keith Self , John Urbanski
IPC分类号： H03M1300
CPC分类号： G06F13/4204 , G06F13/4068
摘要： A bus has a first set of data lines and a second set of data lines. In an embodiment, the bus has a selector circuit to count the number of data lines in the first set of data lines and second set of data lines that have a certain value and to select one set of data lines to be inverted based on the count. In an embodiment, the bus has a first inverter to invert the set of data lines selected and a second inverter to re-invert the set of data lines selected at a receiver based on the value of an added control line.
摘要翻译：总线具有第一组数据线和第二组数据线。在一个实施例中，总线具有选择器电路，用于对第一组数据线中的数据线的数量和具有一定值的第二组数据线进行计数，并且基于计数来选择要反转的一组数据线。在一个实施例中，总线具有第一反相器，用于反转所选择的数据线组和第二反相器，以基于添加的控制线的值重新反转在接收机处选择的数据线组。

3. 发明授权

US06715111B2 Method and apparatus for detecting strobe errors 有权
标题翻译：用于检测频闪错误的方法和装置
公开(公告)号：US06715111B2
公开(公告)日：2004-03-30
申请号：US09748233
申请日：2000-12-27
申请人： Keith Self , Michael Sandhinti , Sanjay Dabral
发明人： Keith Self , Michael Sandhinti , Sanjay Dabral
IPC分类号： G06F1100
CPC分类号： G06F11/0745 , G06F11/076
摘要： A method and apparatus for detecting data strobe errors. A strobe error detection circuit has a strobe input and a counter coupled to the strobe input to count strobe pulses received. The circuit also has a comparator to determine if a strobe error has occurred based on the magnitude of the difference between a first count of strobe pulses and a second count of strobe pulses. In an embodiment, the first count is read from a memory location at a first time and the second count is read at a second time.
摘要翻译：一种用于检测数据选通错误的方法和装置。选通错误检测电路具有选通输入和耦合到选通输入的计数器以对接收到的选通脉冲进行计数。该电路还具有一个比较器，用于根据第一次选通脉冲计数和第二个选通脉冲计数之间的差值的大小来确定是否发生了选通脉冲错误。在一个实施例中，在第一时间从存储器位置读取第一计数，并且在第二时间读取第二计数。

4. 发明授权

US06601196B1 Method and apparatus for debugging ternary and high speed busses 有权
标题翻译：用于调试三元和高速总线的方法和装置
公开(公告)号：US06601196B1
公开(公告)日：2003-07-29
申请号：US09608449
申请日：2000-06-29
申请人： Sanjay Dabral , Ramesh Senthinathan , Ming Zeng , Keith Self , Ernest Khaw , Chung-Wai Yue
发明人： Sanjay Dabral , Ramesh Senthinathan , Ming Zeng , Keith Self , Ernest Khaw , Chung-Wai Yue
IPC分类号： G06F1100
CPC分类号： G06F11/221
摘要： An apparatus and method for debugging a bus including interposing a device that monitors the data transferred between two devices on the bus such that the bus is split into two busses, with data being copied for transmission to a diagnostics device as the data is transferred between the two busses.
摘要翻译：一种用于调试总线的装置和方法，包括插入监视总线上的两个设备之间传输的数据的设备，使得总线被分成两个总线，当数据被复制以传输到诊断设备时，数据在两辆巴士。

5. 发明授权

US5539739A Asynchronous interface between parallel processor nodes 失效
标题翻译：并行处理器节点之间的异步接口
公开(公告)号：US5539739A
公开(公告)日：1996-07-23
申请号：US315284
申请日：1994-09-29
申请人： Charles Dike , Robert Gatlin , Jerry Jex , Craig Peterson , Keith Self , Jim Sutton
发明人： Charles Dike , Robert Gatlin , Jerry Jex , Craig Peterson , Keith Self , Jim Sutton
IPC分类号： G06F15/173 , H04L7/04
CPC分类号： G06F15/17381
摘要： An asynchronous interface enabling a processor node operating at a first clocking frequency to transfer and receive information from a communications network operating at a second clocking frequency. The asynchronous interface comprises an input synchronizer and an output synchronizer. The input synchronizer asynchronously receives a first plurality of information packets from the processor node and synchronously transfers the first plurality of information packets into the communications network. The output synchronizer, however, synchronously receives a second plurality of information packets from the communications network and asynchronously transfers the second plurality of information packets into the processor node. Both the input and output synchronizers are coupled between the communications network and the processor node.
摘要翻译：异步接口使处理器节点能够以第一时钟频率工作，以便以第二时钟频率工作的通信网络传送和接收信息。异步接口包括输入同步器和输出同步器。输入同步器异步地从处理器节点接收第一多个信息分组，并且将第一多个信息分组同步地传送到通信网络中。然而，输出同步器同步地从通信网络接收第二多个信息分组，并将第二多个信息分组异步传送到处理器节点。输入和输出同步器都连接在通信网络和处理器节点之间。

6. 发明申请

US20050122138A1 Power supplies noise detector for integrated circuits 失效
标题翻译：集成电路用电源噪声检测器
公开(公告)号：US20050122138A1
公开(公告)日：2005-06-09
申请号：US10731393
申请日：2003-12-09
申请人： Chaiyuth Chansungsan , Keith Self
发明人： Chaiyuth Chansungsan , Keith Self
IPC分类号： G01R19/165 , H03K5/153 , H04B15/00
CPC分类号： G01R19/16552 , H04B15/005
摘要： In some embodiments, a circuit includes a reference current source to provide a substantially noise free current signal, and a detector coupled to one or two power supplies. In some embodiments, a method includes receiving a substantially noise free current signal, receiving one or two power supply signals, processing the substantially noise free current signal and the one or two power supply signals to detect a noise signal in the one or two power supply signals, and generating a noise detection signal in response to detection of the noise signal.
摘要翻译：在一些实施例中，电路包括参考电流源以提供基本上无噪声的电流信号，以及耦合到一个或两个电源的检测器。在一些实施例中，一种方法包括接收基本无噪声的电流信号，接收一个或两个电源信号，处理基本上无噪声的电流信号和一个或两个电源信号以检测一个或两个电源中的噪声信号信号，并且响应于噪声信号的检测而产生噪声检测信号。

7. 发明授权

US5598113A Fully asynchronous interface with programmable metastability settling time synchronizer 失效
标题翻译：具有可编程亚稳态建立时间同步器的完全异步接口
公开(公告)号：US5598113A
公开(公告)日：1997-01-28
申请号：US375361
申请日：1995-01-19
申请人： Jerry Jex , Charles Dike , Keith Self
发明人： Jerry Jex , Charles Dike , Keith Self
IPC分类号： G06F5/06 , H04J3/04 , H03K19/00 , H03K5/135
CPC分类号： G06F5/06 , H04J3/047
摘要： A fully asynchronous parallel synchronizer having staged write and read enables and an asynchronous interface for same. The asynchronous interface can be used to interconnect two processor systems (e.g., within a multiple processor system or a parallel processor system). The parallel programmable synchronizer contains n latches coupled in parallel having n individual enable lines having staggered enable signals. The latches are coupled such that they output to a multiplexing circuit that also receives individual staggered read enable signals which are based on the write enable signals. According to the parallel programmable synchronizer, data is written into a particular latch in clock cycle (i) just after other data was read from the same particular latch in a just prior clock cycle (i-1). While the synchronizer contains n latches, the number of latches used, x, for any particular embodiment is programmable and the enable signals adjust to accommodate the number of latches selected. The settling time for the synchronizer is therefore programmable while the synchronizer also provides a maximum throughput frequency (sampling rate). A novel empty flag generation is also described.
摘要翻译：具有分级写入和读取功能的完全异步并行同步器使能和异步接口相同。异步接口可用于互连两个处理器系统（例如，在多处理器系统或并行处理器系统内）。并行可编程同步器包含并联耦合的n个锁存器，其具有具有交错使能信号的n个单独使能线。锁存器被耦合，使得它们输出到多路复用电路，该多路复用电路还接收基于写入使能信号的单独的交错读取使能信号。根据并行可编程同步器，在紧随其后的时钟周期（i-1）中从相同的特定锁存器读取其它数据之后，数据被写入时钟周期（i）中的特定锁存器。虽然同步器包含n个锁存器，但是对于任何特定实施例，所使用的锁存器的数量x是可编程的，并且使能信号被调整以适应所选择的锁存器的数量。因此，同步器的建立时间是可编程的，而同步器也提供最大吞吐量频率（采样率）。还描述了一个新的空旗生成。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式