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1. 发明授权

US06242362B1 Etch process for fabricating a vertical hard mask/conductive pattern profile to improve T-shaped profile for a silicon oxynitride hard mask 有权
标题翻译：用于制造垂直硬掩模/导电图案轮廓以改善氮氧化硅硬掩模的T形轮廓的蚀刻工艺
公开(公告)号：US06242362B1
公开(公告)日：2001-06-05
申请号：US09366736
申请日：1999-08-04
申请人： Jen-Cheng Liu , Huan-Just Lin , Chia-Shiung Tsai , Yung-Kuan Hsaio
发明人： Jen-Cheng Liu , Huan-Just Lin , Chia-Shiung Tsai , Yung-Kuan Hsaio
IPC分类号： H01L21302
CPC分类号： H01L21/32137 , H01L21/32139
摘要： The present invention provides a method of fabricating a vertical hard mask/conductive pattern profile. The process begins by forming a polysilicon or more preferably a polysilicon and silicide conductive layer over a semiconductor substrate. A silicon oxynitride hard mask layer is formed over the conductive layer. The silicon oxynitride hard mask layer is patterned to form a hard mask pattern. The conductive layer is patterned to form a conductive pattern using Cl2/He—O2/N2 etch chemistry, thereby forming a hard mask/conductive pattern profile that is vertical.
摘要翻译：本发明提供了制造垂直硬掩模/导电图案轮廓的方法。该过程通过在半导体衬底上形成多晶硅或更优选多晶硅和硅化物导电层开始。在导电层上形成氧氮化硅硬掩模层。将氮氧化硅硬掩模层图案化以形成硬掩模图案。使用Cl 2 / He-O 2 / N 2蚀刻化学法将导电层图案化以形成导电图案，从而形成垂直的硬掩模/导电图案轮廓。

2. 发明授权

US06174818B1 Method of patterning narrow gate electrode 有权
标题翻译：窄栅电极图案方法
公开(公告)号：US06174818B1
公开(公告)日：2001-01-16
申请号：US09443424
申请日：1999-11-19
申请人： Hun-Jan Tao , Huan-Just Lin , Hung-Chang Hsieh , Chu-Yun Fu , Ying-Ying Wang , Chia-Shiung Tsai , Fang-Cheng Chen
发明人： Hun-Jan Tao , Huan-Just Lin , Hung-Chang Hsieh , Chu-Yun Fu , Ying-Ying Wang , Chia-Shiung Tsai , Fang-Cheng Chen
IPC分类号： H01L21302
CPC分类号： H01L21/0276 , H01L21/0332 , H01L21/28123 , H01L21/32139
摘要： A process is described for forming very narrow polysilicon gate lines for use as gate electrodes in FETs. The process uses a consumable hard mask of silicon oxynitride covered by a thin layer of silicon oxide during the etching of the polysilicon. The thicknesses of the two layers that make up the hard mask are chosen so that the structure also serves as an ARC for the photoresist coating immediately above it. A relatively thin layer of the latter is used in order to improve resolution. After the photoresist has been patterned it may be trimmed or it may be removed and re-formed, since the silicon oxide layer provides protection for the underlying silicon oxynitride. After the hard mask has been formed, all photoresist is removed and the polysilicon is etched. During etching there is simultaneous removal of the silicon oxide layer and part of the silicon oxynitride as well.
摘要翻译：描述了用于形成用于FET中的栅电极的非常窄的多晶硅栅极线的工艺。该方法在蚀刻多晶硅期间使用由氧化硅薄层覆盖的氮氧化硅的消耗性硬掩模。选择构成硬掩模的两层的厚度，使得该结构也用作其上方的光致抗蚀剂涂层的ARC。为了提高分辨率，使用后者的较薄层。在光致抗蚀剂被图案化之后，可以对其进行修整或者可以将其去除并重新形成，因为氧化硅层为下面的氮氧化硅提供保护。在形成硬掩模之后，除去所有光致抗蚀剂并蚀刻多晶硅。在蚀刻期间，同时去除氧化硅层和部分氮氧化硅。

3. 发明授权

US6140218A Method for fabricating a T-shaped hard mask/conductor profile to improve self-aligned contact isolation 有权
标题翻译：用于制造T形硬掩模/导体轮廓以改善自对准接触隔离的方法
公开(公告)号：US6140218A
公开(公告)日：2000-10-31
申请号：US329782
申请日：1999-06-10
申请人： Jen-Cheng Liu , Li-Chih Chao , Huan-Just Lin , Yung-Kuan Hsiao
发明人： Jen-Cheng Liu , Li-Chih Chao , Huan-Just Lin , Yung-Kuan Hsiao
IPC分类号： H01L21/033 , H01L21/28 , H01L21/60 , H01L21/44
CPC分类号： H01L21/76897 , H01L21/0334 , H01L21/28123
摘要： The present invention provides a method of fabricating a T-shaped hard mask/conductive pattern profile and a process of etching a self-aligned contact opening using a T-shaped hard mask/conductive pattern profile to improve the self-aligned contact isolation. The process begins by forming a polysilicon or more preferably a polysilicon/silicide conductive layer over a semiconductor substrate. A silicon oxynitride hard mask layer is formed over the conductive layer. The silicon oxynitride hard mask layer is patterned to form a hard mask pattern. The conductive layer is patterned to form a conductive pattern in a three step etch using Cl.sub.2 and HBr chemistry. The silicon oxynitride hard mask releases oxygen during the conductive layer etch resulting in a T-shaped hard mask/conductive pattern profile (e.g. the width of the hard mask is greater than the width of the conductive pattern after etching). In a preferred embodiment, the a T-shaped hard mask/conductive pattern profile is used to form a self-aligned contact for a capacitor over bitline structure.
摘要翻译：本发明提供了一种制造T形硬掩模/导电图案轮廓的方法以及使用T形硬掩模/导电图案轮廓蚀刻自对准接触开口的过程，以改善自对准接触隔离。该过程通过在半导体衬底上形成多晶硅或更优选多晶硅/硅化物导电层开始。在导电层上形成氧氮化硅硬掩模层。将氮氧化硅硬掩模层图案化以形成硬掩模图案。使用Cl2和HBr化学，在三步蚀刻中对导电层进行图案化以形成导电图案。氧氮化硅硬掩模在导电层蚀刻期间释放氧，导致T形硬掩模/导电图案轮廓（例如，硬掩模的宽度大于蚀刻后的导电图案的宽度）。在优选实施例中，T形硬掩模/导电图形轮廓用于通过位线结构形成用于电容器的自对准接触。

4. 发明申请

US20130056837A1 SELF-ALIGNED INSULATED FILM FOR HIGH-K METAL GATE DEVICE 有权
标题翻译：用于高K金属栅极设备的自对准绝缘膜
公开(公告)号：US20130056837A1
公开(公告)日：2013-03-07
申请号：US13244365
申请日：2011-09-24
申请人： Jin-Aun Ng , Maxi Chang , Jen-Sheng Yang , Ta-Wei Lin , Shih-Hao Lo , Chih-Yang Yeh , Hui-Wen Lin , Jung-Hui Kao , Yuan-Tien Tu , Huan-Just Lin , Chih-Tang Peng , Pei-Ren Jeng , Bao-Ru Young , Hak-Lay Chuang
发明人： Jin-Aun Ng , Maxi Chang , Jen-Sheng Yang , Ta-Wei Lin , Shih-Hao Lo , Chih-Yang Yeh , Hui-Wen Lin , Jung-Hui Kao , Yuan-Tien Tu , Huan-Just Lin , Chih-Tang Peng , Pei-Ren Jeng , Bao-Ru Young , Hak-Lay Chuang
IPC分类号： H01L29/772 , H01L21/336 , H01L21/28
CPC分类号： H01L21/28229 , H01L21/28079 , H01L21/28088 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823864 , H01L29/42364 , H01L29/4958 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6659
摘要： A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.
摘要翻译：制造集成电路的方法包括提供半导体衬底并在诸如高k电介质的衬底上形成栅极电介质。在半导体衬底上形成金属栅极结构，并在其上形成一个薄的电介质膜。薄介电膜包括从金属栅极与金属组合的氮氧化合物。该方法还包括在金属栅极结构的两侧提供层间电介质（ILD）。

5. 发明授权

US08222136B2 Method of forming contacts for a semiconductor device 有权
标题翻译：形成半导体器件的触点的方法
公开(公告)号：US08222136B2
公开(公告)日：2012-07-17
申请号：US12906868
申请日：2010-10-18
申请人： Yuan-Tien Tu , Tsai-Chun Li , Huan-Just Lin , Shih-Chang Chen
发明人： Yuan-Tien Tu , Tsai-Chun Li , Huan-Just Lin , Shih-Chang Chen
IPC分类号： H01L21/4763
CPC分类号： H01L21/76814 , H01L21/02063 , H01L21/76816
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a layer over a substrate. The method includes forming a first opening in the layer that exposes a first region of the substrate. The method includes removing a first oxidation layer formed over the first region through a first sputtering process. The method includes filling the first opening with a conductive material. The method includes forming a second opening in the layer that exposes a second region of the substrate, the second region being different from the first region. The method includes removing a second oxidation layer formed over the second region through a second sputtering process. One of the first and second sputtering processes is more powerful than the other.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在衬底上形成层。所述方法包括在所述层中形成暴露所述衬底的第一区域的第一开口。该方法包括通过第一溅射工艺去除在第一区域上形成的第一氧化层。该方法包括用导电材料填充第一开口。所述方法包括在所述层中形成暴露所述衬底的第二区域的第二开口，所述第二区域不同于所述第一区域。该方法包括通过第二溅射工艺除去在第二区域上形成的第二氧化层。第一和第二溅射工艺之一比另一个更强大。

6. 发明授权

US08129279B2 Chemical mechanical polish process control for improvement in within-wafer thickness uniformity 有权
标题翻译：化学机械抛光过程控制，以提高晶片内厚度均匀性
公开(公告)号：US08129279B2
公开(公告)日：2012-03-06
申请号：US12250239
申请日：2008-10-13
申请人： Shen-Nan Lee , Ying-Mei Lin , Yu-Jen Cheng , Keung Hui , Huan-Just Lin
发明人： Shen-Nan Lee , Ying-Mei Lin , Yu-Jen Cheng , Keung Hui , Huan-Just Lin
IPC分类号： H01L21/302
CPC分类号： B24B37/013 , B24B49/12
摘要： A method of performing chemical mechanical polish (CMP) processes on a wafer includes providing the wafer; determining a thickness profile of a feature on a surface of the wafer; and, after the step of determining the thickness profile, performing a high-rate CMP process on the feature using a polish recipe to substantially achieve a within-wafer thickness uniformity of the feature. The polish recipe is determined based on the thickness profile.
摘要翻译：在晶片上进行化学机械抛光（CMP）工艺的方法包括提供晶片; 确定晶片表面上的特征的厚度分布; 并且在确定厚度分布的步骤之后，使用抛光配方对特征进行高速率CMP处理，以基本上实现特征的晶片内厚度均匀性。根据厚度分布确定抛光配方。

7. 发明授权

US07157350B2 Method of forming SOI-like structure in a bulk semiconductor substrate using self-organized atomic migration 有权
公开(公告)号：US07157350B2
公开(公告)日：2007-01-02
申请号：US10847607
申请日：2004-05-17
申请人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
发明人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
IPC分类号： H01L21/76
CPC分类号： H01L21/3247 , H01L21/76232 , H01L21/76283 , H01L27/1203
摘要： Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.

8. 发明授权

US07023042B2 Method of forming a stacked capacitor structure with increased surface area for a DRAM device 有权
标题翻译：形成用于DRAM器件的具有增加的表面积的堆叠电容器结构的方法
公开(公告)号：US07023042B2
公开(公告)日：2006-04-04
申请号：US10755498
申请日：2004-01-12
申请人： Bor-Wen Chan , Huan-Just Lin , Hun-Jan Tao
发明人： Bor-Wen Chan , Huan-Just Lin , Hun-Jan Tao
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L28/88 , H01L27/10814 , H01L27/10852
摘要： A process for forming a DRAM stacked capacitor structure with increased surface area, has been developed. The process features forming lateral grooves in the sides of a polysilicon storage node structure, during a dry etching procedure used to define the storage node structure. The grooves are selectively, and laterally formed in ion implanted veins, which in turn had been placed at various depths in an intrinsic polysilicon layer via a series of ion implantation steps, each performed at a specific implant energy. An isotopic component of the storage node structure, defining dry etch procedure, selectively etches the highly doped, ion implanted veins at a greater rate than the non-ion implanted regions of polysificon, located between the ion implanted veins, resulting in a necked profile, storage node structure, featuring increased surface area as a result of the formation of the lateral grooves.
摘要翻译：已经开发了用于形成具有增加的表面积的DRAM叠层电容器结构的工艺。该工艺在用于限定存储节点结构的干蚀刻过程中，在多晶硅存储节点结构的侧面形成横向凹槽。这些凹槽是选择性地和侧向地形成在离子植入的静脉中，这些静脉又通过一系列离子注入步骤而被放置在本征多晶硅层中的各种深度处，每个离子注入步骤以特定的注入能量进行。存储节点结构的同位素组分定义了干蚀刻过程，选择性地以高于离子植入的静脉之间的聚合物的非离子注入区域的速率以更高的速率蚀刻高度掺杂的离子植入的静脉，产生颈缩轮廓，存储节点结构，由于形成横向槽而具有增加的表面积。

9. 发明申请

US20050253194A1 SOI-like structure in a bulk semiconductor substrate and method of forming same 有权
标题翻译：体半导体衬底中的SOI类结构及其形成方法
公开(公告)号：US20050253194A1
公开(公告)日：2005-11-17
申请号：US10847607
申请日：2004-05-17
申请人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
发明人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
IPC分类号： H01L21/324 , H01L21/762 , H01L27/01 , H01L27/12
CPC分类号： H01L21/3247 , H01L21/76232 , H01L21/76283 , H01L27/1203
摘要： Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.
摘要翻译：通过退火将体硅转变成SOI样结构。沟槽形成在大量衬底中以限定器件位置。沟槽的下部在氢气气氛中在低压下退火。这将下沟槽部分转变成在器件位置下延伸的膨胀的球状空隙。相邻的空洞每个居住在中间位置的一半左右。消耗硅的过程在空隙的壁上形成衬垫，相邻空隙上的衬垫邻接以将介入的器件位置与衬底和其它器件位置隔离。

10. 发明授权

US06235440B1 Method to control gate CD 有权
标题翻译：控制门光盘的方法
公开(公告)号：US06235440B1
公开(公告)日：2001-05-22
申请号：US09434563
申请日：1999-11-12
申请人： Hun-Jan Tao , Huan-Just Lin , Fang-Cheng Chen
发明人： Hun-Jan Tao , Huan-Just Lin , Fang-Cheng Chen
IPC分类号： G03F900
CPC分类号： G03F7/70625 , G03F7/40 , H01L22/20 , Y10S438/949
摘要： The invention is a process for reducing variations in CD from wafer to wafer. It begins by increasing all line widths in the original pattern data file by a fixed amount that is sufficient to ensure that all lines will be wider than the lowest acceptable CD value. Using a reticle generated from this modified data file, the pattern is formed in photoresist and the resulting CD value is determined. If this turns out be outside (above) the acceptable CD range, the amount of deviation from the ideal CD value is determined and fed into suitable software that calculates the control parameters (usually time) for an ashing routine. After ashing, the lines will have been reduced in width by the amount necessary to obtain the correct CD. A fringe benefit of this trimming process is that edge roughness of the photoresist lines is reduced and line feet are removed.
摘要翻译：本发明是减少CD从晶片到晶片的变化的方法。它首先将原始图案数据文件中的所有行宽增加一个固定的量，这足以确保所有行都比最低可接受的CD值宽。使用由该修改的数据文件生成的掩模版，在光致抗蚀剂中形成图案，并确定所得到的CD值。如果事实证明在可接受的CD范围之外（以上），则确定与理想CD值的偏差量，并将其馈送到计算灰化程序的控制参数（通常为时间）的合适软件中。灰化后，线条的宽度减小了获得正确CD所需的量。这种修整过程的附带优点是减少了光致抗蚀剂线的边缘粗糙度并且去除了线脚。

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