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1. 发明授权

US08286114B2 3-dimensional device design layout 有权
标题翻译：三维设备设计布局
公开(公告)号：US08286114B2
公开(公告)日：2012-10-09
申请号：US11833119
申请日：2007-08-02
申请人： Harry Chuang , Kong-Beng Thei , Mong Song Liang , Sheng-Chen Chung , Chih-Tsung Yao , Jung-Hui Kao , Chung Long Cheng , Gary Shen , Gwan Sin Chang
发明人： Harry Chuang , Kong-Beng Thei , Mong Song Liang , Sheng-Chen Chung , Chih-Tsung Yao , Jung-Hui Kao , Chung Long Cheng , Gary Shen , Gwan Sin Chang
IPC分类号： G06F17/50
CPC分类号： H01L29/785 , H01L21/76807 , H01L21/76895 , H01L21/76897 , H01L21/823431 , H01L21/823437 , H01L21/823475 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a circuit design, thereby allowing circuit and layout designers to work at a higher level without the need to specify each individual fin or 3-D structure. Thereafter, the planar design may be converted to a 3-D design by replacing planar active areas with 3-D devices occupying an equivalent area.
摘要翻译：提供了一种用于定义诸如finFET的3-D器件的布局的方法。该方法包括确定期望的3-D设备所需的区域和使用具有等效面积的平面设备来设计电路。对应于期望的3-D器件的平面器件用于布局电路设计，从而允许电路和布局设计者在更高级别工作，而不需要指定每个单独的鳍或3-D结构。此后，平面设计可以通过用占据等同面积的3-D器件代替平面有源区域而被转换成3维设计。

2. 发明申请

US20050118802A1 Method for implementing poly pre-doping in deep sub-micron process 审中-公开
标题翻译：在深亚微米工艺中实施多种预掺杂的方法
公开(公告)号：US20050118802A1
公开(公告)日：2005-06-02
申请号：US10991839
申请日：2004-11-18
申请人： Chang-Sheng Tsao , Yi-Hang Chen , Jung-Hui Kao , Yen-Ming Chen , Pu-Fang Chen , Lin-June Wu
发明人： Chang-Sheng Tsao , Yi-Hang Chen , Jung-Hui Kao , Yen-Ming Chen , Pu-Fang Chen , Lin-June Wu
IPC分类号： H01L21/265 , H01L21/28 , H01L21/324 , H01L21/331 , H01L29/78
CPC分类号： H01L21/28035 , H01L21/265 , H01L21/324 , H01L29/78
摘要： Method for reducing dopant contamination during the fabrication of semiconductor devices is provided. The method includes doping a first layer, such as a polysilicon layer. During a subsequent annealing process, a gas, such as nitrogen, oxygen, a combination thereof, or the like, is introduced. The gas causes a cap layer to be formed over the first layer, preventing or reducing out-diffusing of the dopants and contamination of the process chamber. In a preferred embodiment, the gas is introduced during the ramp-up stage of the annealing process. The cap layer may be removed prior to etching the first layer.
摘要翻译：提供了在制造半导体器件期间减少掺杂剂污染的方法。该方法包括掺杂第一层，例如多晶硅层。在随后的退火过程中，引入气体，例如氮气，氧气，其组合等。气体导致在第一层上形成覆盖层，防止或减少掺杂物的扩散和处理室的污染。在优选实施例中，在退火过程的加速阶段期间引入气体。在蚀刻第一层之前可以去除覆盖层。

3. 发明授权

US06273099B1 Simplified method for cleaning silicon wafers after application of laser marks 失效
标题翻译：在应用激光标记之后清洁硅晶片的简化方法
公开(公告)号：US06273099B1
公开(公告)日：2001-08-14
申请号：US09108412
申请日：1998-07-01
申请人： Chun Chieh Chang , Kuo-Fong Chen , Jung-Hui Kao
发明人： Chun Chieh Chang , Kuo-Fong Chen , Jung-Hui Kao
IPC分类号： B08B304
CPC分类号： H01L21/02052 , B08B3/12 , Y10S134/902
摘要： A simplified cleaning method for the removal of particulates and adherent residues resulting from the incorporation of laser identification marks onto silicon wafers is described. The cleaning method consists of first immersing the wafers in a heated ammoniacal/hydrogen peroxide RCA-SC-1 cleaning solution in the presence of megasonic agitation. This is followed by a immersion rinse in de-ionized water heated to at least 50° C. Finally the wafers are subjected to at least three quick-dump rinses in room temperature de-ionized water and dried. It is found that the hot de-ionized water rinse provides adequate removal of chemical residues remaining after the particle dislodging action of the megasonically agitated RCA SC-1 solution to eliminate the need for application of the acidic/hydrogen peroxide RCA SC-2 treatment.
摘要翻译：描述了通过将激光识别标记结合到硅晶片上而导致的微粒和粘附残留物的简化清洁方法。该清洁方法包括首先将晶片浸入加热的氨/过氧化氢RCA-SC-1清洗溶液中，在这种情况下在超声波搅拌下进行。然后在加热到至少50℃的去离子水中进行浸渍冲洗。最后将晶片在室温去离子水中经受至少三次快速倾倒冲洗并干燥。发现热去离子水漂洗可以充分去除在经典搅拌的RCA SC-1溶液的颗粒脱落作用后残留的化学残留物，以消除对酸/过氧化氢RCA SC-2处理的应用。

4. 发明申请

US20130056837A1 SELF-ALIGNED INSULATED FILM FOR HIGH-K METAL GATE DEVICE 有权
标题翻译：用于高K金属栅极设备的自对准绝缘膜
公开(公告)号：US20130056837A1
公开(公告)日：2013-03-07
申请号：US13244365
申请日：2011-09-24
申请人： Jin-Aun Ng , Maxi Chang , Jen-Sheng Yang , Ta-Wei Lin , Shih-Hao Lo , Chih-Yang Yeh , Hui-Wen Lin , Jung-Hui Kao , Yuan-Tien Tu , Huan-Just Lin , Chih-Tang Peng , Pei-Ren Jeng , Bao-Ru Young , Hak-Lay Chuang
发明人： Jin-Aun Ng , Maxi Chang , Jen-Sheng Yang , Ta-Wei Lin , Shih-Hao Lo , Chih-Yang Yeh , Hui-Wen Lin , Jung-Hui Kao , Yuan-Tien Tu , Huan-Just Lin , Chih-Tang Peng , Pei-Ren Jeng , Bao-Ru Young , Hak-Lay Chuang
IPC分类号： H01L29/772 , H01L21/336 , H01L21/28
CPC分类号： H01L21/28229 , H01L21/28079 , H01L21/28088 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823864 , H01L29/42364 , H01L29/4958 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6659
摘要： A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.
摘要翻译：制造集成电路的方法包括提供半导体衬底并在诸如高k电介质的衬底上形成栅极电介质。在半导体衬底上形成金属栅极结构，并在其上形成一个薄的电介质膜。薄介电膜包括从金属栅极与金属组合的氮氧化合物。该方法还包括在金属栅极结构的两侧提供层间电介质（ILD）。

5. 发明申请

US20080076215A1 Method for semiconductor device performance enhancement 有权
标题翻译：半导体器件性能提高的方法
公开(公告)号：US20080076215A1
公开(公告)日：2008-03-27
申请号：US11527616
申请日：2006-09-27
申请人： Harry Chuang , Kong-Beng Thei , Chung-Long Cheng , Sheng-Chen Chung , Wen-Huei Guo , Jung-Hui Kao , Ryan Chia-Jen Chen , Mong-Song Liang
发明人： Harry Chuang , Kong-Beng Thei , Chung-Long Cheng , Sheng-Chen Chung , Wen-Huei Guo , Jung-Hui Kao , Ryan Chia-Jen Chen , Mong-Song Liang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/7843
摘要： A method of manufacturing a semiconductor device is disclosed. The method provides a semiconductor substrate with at least a PMOS device and at least an NMOS device thereon. A first insulating layer is formed overlying the NMOS and PMOS devices. A second insulating layer is formed overlying the first insulating layer. The second insulating layer overlying the PMOS device is thinned to leave portion of the second insulating layer. A first thermal treatment is performed on the NMOS and PMOS devices. The second insulating layer overlying the NMOS device and the remaining portion of the second insulating layer overlying the PMOS device are removed and the first insulating layer overlying the NMOS and PMOS devices is thinned to leave a remaining portion thereof.
摘要翻译：公开了制造半导体器件的方法。该方法提供具有至少PMOS器件和至少NMOS器件的半导体衬底。在NMOS和PMOS器件上形成第一绝缘层。在第一绝缘层上形成第二绝缘层。覆盖PMOS器件的第二绝缘层变薄以留下第二绝缘层的部分。在NMOS和PMOS器件上进行第一次热处理。去除覆盖NMOS器件的第二绝缘层和覆盖PMOS器件的第二绝缘层的剩余部分，并且覆盖NMOS和PMOS器件的第一绝缘层变薄以留下其余部分。

6. 发明授权

US08822283B2 Self-aligned insulated film for high-k metal gate device 有权
标题翻译：用于高k金属栅极器件的自对准绝缘膜
公开(公告)号：US08822283B2
公开(公告)日：2014-09-02
申请号：US13244365
申请日：2011-09-24
申请人： Jin-Aun Ng , Maxi Chang , Jen-Sheng Yang , Ta-Wei Lin , Shih-Hao Lo , Chih-Yang Yeh , Hui-Wen Lin , Jung-Hui Kao , Yuan-Tien Tu , Huan-Just Lin , Chih-Tang Peng , Pei-Ren Jeng , Bao-Ru Young , Hak-Lay Chuang
发明人： Jin-Aun Ng , Maxi Chang , Jen-Sheng Yang , Ta-Wei Lin , Shih-Hao Lo , Chih-Yang Yeh , Hui-Wen Lin , Jung-Hui Kao , Yuan-Tien Tu , Huan-Just Lin , Chih-Tang Peng , Pei-Ren Jeng , Bao-Ru Young , Hak-Lay Chuang
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/66
CPC分类号： H01L21/28229 , H01L21/28079 , H01L21/28088 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823864 , H01L29/42364 , H01L29/4958 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6659
摘要： A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.
摘要翻译：制造集成电路的方法包括提供半导体衬底并在诸如高k电介质的衬底上形成栅极电介质。在半导体衬底上形成金属栅极结构，并在其上形成一个薄的电介质膜。薄介电膜包括从金属栅极与金属组合的氮氧化合物。该方法还包括在金属栅极结构的两侧提供层间电介质（ILD）。

7. 发明授权

US07632729B2 Method for semiconductor device performance enhancement 有权
标题翻译：半导体器件性能提高的方法
公开(公告)号：US07632729B2
公开(公告)日：2009-12-15
申请号：US11527616
申请日：2006-09-27
申请人： Harry Chuang , Kong-Beng Thei , Chung-Long Cheng , Sheng-Chen Chung , Wen-Huei Guo , Jung-Hui Kao , Ryan Chia-Jen Chen , Mong-Song Liang
发明人： Harry Chuang , Kong-Beng Thei , Chung-Long Cheng , Sheng-Chen Chung , Wen-Huei Guo , Jung-Hui Kao , Ryan Chia-Jen Chen , Mong-Song Liang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/7843
摘要： A method of manufacturing a semiconductor device is disclosed. The method provides a semiconductor substrate with at least a PMOS device and at least an NMOS device thereon. A first insulating layer is formed overlying the NMOS and PMOS devices. A second insulating layer is formed overlying the first insulating layer. The second insulating layer overlying the PMOS device is thinned to leave portion of the second insulating layer. A first thermal treatment is performed on the NMOS and PMOS devices. The second insulating layer overlying the NMOS device and the remaining portion of the second insulating layer overlying the PMOS device are removed and the first insulating layer overlying the NMOS and PMOS devices is thinned to leave a remaining portion thereof.
摘要翻译：公开了制造半导体器件的方法。该方法提供具有至少PMOS器件和至少NMOS器件的半导体衬底。在NMOS和PMOS器件上形成第一绝缘层。在第一绝缘层上形成第二绝缘层。覆盖PMOS器件的第二绝缘层变薄以留下第二绝缘层的部分。在NMOS和PMOS器件上进行第一次热处理。去除覆盖NMOS器件的第二绝缘层和覆盖PMOS器件的第二绝缘层的剩余部分，并且覆盖NMOS和PMOS器件的第一绝缘层变薄以留下其余部分。

8. 发明申请

US20080263492A1 3-Dimensional Device Design Layout 有权
标题翻译：三维设备设计布局
公开(公告)号：US20080263492A1
公开(公告)日：2008-10-23
申请号：US11833119
申请日：2007-08-02
申请人： Harry Chuang , Kong-Beng Thei , Mong Song Liang , Sheng-Chen Chung , Chih-Tsung Yao , Jung-Hui Kao , Chung Long Cheng , Gary Shen , Gwan Sin Chang
发明人： Harry Chuang , Kong-Beng Thei , Mong Song Liang , Sheng-Chen Chung , Chih-Tsung Yao , Jung-Hui Kao , Chung Long Cheng , Gary Shen , Gwan Sin Chang
IPC分类号： G06F17/50
CPC分类号： H01L29/785 , H01L21/76807 , H01L21/76895 , H01L21/76897 , H01L21/823431 , H01L21/823437 , H01L21/823475 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a circuit design, thereby allowing circuit and layout designers to work at a higher level without the need to specify each individual fin or 3-D structure. Thereafter, the planar design may be converted to a 3-D design by replacing planar active areas with 3-D devices occupying an equivalent area.
摘要翻译：提供了一种用于定义诸如finFET的3-D器件的布局的方法。该方法包括确定期望的3-D设备所需的区域和使用具有等效面积的平面设备来设计电路。对应于期望的3-D器件的平面器件用于布局电路设计，从而允许电路和布局设计者在更高级别工作，而不需要指定每个单独的鳍或3-D结构。此后，平面设计可以通过用占据等同面积的3-D器件代替平面有源区域而被转换成3维设计。

9. 发明申请

US20080258228A1 Contact Scheme for MOSFETs 有权
标题翻译： MOSFET的接触方案
公开(公告)号：US20080258228A1
公开(公告)日：2008-10-23
申请号：US11833128
申请日：2007-08-02
申请人： Harry Chuang , Kong-Beng Thei , Mong Song Liang , Jung-Hui Kao , Sheng-Chen Chung , Chung Long Cheng , Shun-Jang Liao
发明人： Harry Chuang , Kong-Beng Thei , Mong Song Liang , Jung-Hui Kao , Sheng-Chen Chung , Chung Long Cheng , Shun-Jang Liao
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L29/785 , H01L21/76807 , H01L21/76895 , H01L21/76897 , H01L21/823431 , H01L21/823437 , H01L21/823475 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first inter-layer dielectric (ILD) over the semiconductor substrate; a contact extending from a top surface of the first ILD into the first ILD; a second ILD over the first ILD; a bottom inter-metal dielectric (IMD) over the second ILD; and a dual damascene structure comprising a metal line in the IMD and a via in the second ILD, wherein the via is connected to the contact.
摘要翻译：提供半导体结构及其形成方法。半导体结构包括半导体衬底; 半导体衬底上的第一层间电介质（ILD）; 从第一ILD的顶表面延伸到第一ILD中的接触; 第一个ILD的第二个ILD; 在第二ILD上的底部金属间电介质（IMD）; 以及包括IMD中的金属线和第二ILD中的通孔的双镶嵌结构，其中所述通孔连接到所述触点。

10. 发明授权

US07157351B2 Ozone vapor clean method 有权
标题翻译：臭氧蒸汽清洁方法
公开(公告)号：US07157351B2
公开(公告)日：2007-01-02
申请号：US10850747
申请日：2004-05-20
申请人： Chung-Long Cheng , Kong-Beng Thei , Jung-Hui Kao
发明人： Chung-Long Cheng , Kong-Beng Thei , Jung-Hui Kao
IPC分类号： H01L21/76
CPC分类号： H01L21/02057 , H01L21/02238 , H01L21/02255 , H01L21/02304 , H01L21/02307 , H01L21/31662 , H01L21/76224
摘要： A method for cleaning and forming an oxide film on a surface, particularly a silicon surface. The surface is initially cleaned and then exposed to ozone vapor, which forms the oxide film on the surface. The method is particularly useful for forming a pre-liner oxide film on trench surfaces in the fabrication of STI (shallow trench isolation) structures.
摘要翻译：一种在表面特别是硅表面上清洗和形成氧化膜的方法。表面最初被清洁，然后暴露于臭氧蒸汽，这在表面上形成氧化膜。该方法在STI（浅沟槽隔离）结构的制造中在沟槽表面上形成预衬垫氧化膜特别有用。

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