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1. 发明授权

US06767783B2 Self-aligned transistor and diode topologies in silicon carbide through the use of selective epitaxy or selective implantation 有权
标题翻译：通过使用选择性外延或选择性注入在碳化硅中自对准晶体管和二极管拓扑
公开(公告)号：US06767783B2
公开(公告)日：2004-07-27
申请号：US10193108
申请日：2002-07-12
申请人： Jeffrey B. Casady , Geoffrey E. Carter , Yaroslav Koshka , Michael S. Mazzola , Igor Sankin
发明人： Jeffrey B. Casady , Geoffrey E. Carter , Yaroslav Koshka , Michael S. Mazzola , Igor Sankin
IPC分类号： H01L218249
CPC分类号： H01L29/6606 , H01L29/1608 , H01L29/66068 , H01L29/732 , H01L29/739
摘要： A method of making vertical diodes and transistors in SiC is provided. The method according to the invention uses a mask (e.g., a mask that has been previously used for etching features into the device) for selective epitaxial growth or selective ion implantation. In this manner, the gate and base regions of static induction transistors and bipolar junction transistors can be formed in a self-aligned process. A method of making planar diodes and planar edge termination structures (e.g., guard rings) is also provided.
摘要翻译：提供了一种在SiC中制造垂直二极管和晶体管的方法。根据本发明的方法使用用于选择性外延生长或选择性离子注入的掩模（例如，先前已经用于蚀刻特征的掩模到设备中）。以这种方式，静态感应晶体管和双极结型晶体管的栅极和基极区域可以以自对准工艺形成。还提供了制造平面二极管和平面边缘终止结构（例如保护环）的方法。

2. 发明授权

US07242040B2 Lateral trench field-effect transistors in wide bandgap semiconductor materials, methods of making, and integrated circuits incorporating the transistors 有权
标题翻译：宽带隙半导体材料中的横向沟槽场效应晶体管，制造方法和结合晶体管的集成电路
公开(公告)号：US07242040B2
公开(公告)日：2007-07-10
申请号：US11505813
申请日：2006-08-18
申请人： Igor Sankin , Jeffrey B. Casady , Joseph N. Merrett
发明人： Igor Sankin , Jeffrey B. Casady , Joseph N. Merrett
IPC分类号： H01L21/8234 , H01L21/336 , H01L29/78
CPC分类号： H01L29/2003 , H01L27/098 , H01L29/1608 , H01L29/47 , H01L29/808 , H01L29/8122
摘要： A junction field effect transistor is described. The transistor is made from a wide bandgap semiconductor material. The device comprises source, channel, drift and drain semiconductor layers, as well as p-type implanted or Schottky gate regions. The source, channel, drift and drain layers can be epitaxially grown. The ohmic contacts to the source, gate, and drain regions can be formed on the same side of the wafer. The devices can have different threshold voltages depending on the vertical channel width and can be implemented for both depletion and enhanced modes of operation for the same channel doping. The devices can be used for digital, analog, and monolithic microwave integrated circuits. Methods for making the transistors and integrated circuits comprising the devices are also described.
摘要翻译：描述了结型场效应晶体管。晶体管由宽带隙半导体材料制成。该器件包括源极，沟道，漂移和漏极半导体层以及p型注入或肖特基栅极区。源极，沟道，漂移和漏极层可以外延生长。到源极，栅极和漏极区域的欧姆接触可以形成在晶片的同一侧上。器件可以具有取决于垂直沟道宽度的不同阈值电压，并且可以针对相同沟道掺杂的耗尽和增强的工作模式实现。该器件可用于数字，模拟和单片微波集成电路。还描述了制造包括这些器件的晶体管和集成电路的方法。

3. 发明授权

US07119380B2 Lateral trench field-effect transistors in wide bandgap semiconductor materials, methods of making, and integrated circuits incorporating the transistors 有权
标题翻译：宽带隙半导体材料中的横向沟槽场效应晶体管，制造方法和结合晶体管的集成电路
公开(公告)号：US07119380B2
公开(公告)日：2006-10-10
申请号：US10999954
申请日：2004-12-01
申请人： Igor Sankin , Jeffrey B. Casady , Joseph N. Merrett
发明人： Igor Sankin , Jeffrey B. Casady , Joseph N. Merrett
IPC分类号： H01L29/74 , H01L29/423 , H01L31/111
CPC分类号： H01L29/2003 , H01L27/098 , H01L29/1608 , H01L29/47 , H01L29/808 , H01L29/8122
摘要： A junction field effect transistor is described. The transistor is made from a wide bandgap semiconductor material. The device comprises source, channel, drift and drain semiconductor layers, as well as p-type implanted or Schottky gate regions. The source, channel, drift and drain layers can be epitaxially grown. The ohmic contacts to the source, gate, and drain regions can be formed on the same side of the wafer. The devices can have different threshold voltages depending on the vertical channel width and can be implemented for both depletion and enhanced modes of operation for the same channel doping. The devices can be used for digital, analog, and monolithic microwave integrated circuits. Methods for making the transistors and integrated circuits comprising the devices are also described.
摘要翻译：描述了结型场效应晶体管。晶体管由宽带隙半导体材料制成。该器件包括源极，沟道，漂移和漏极半导体层以及p型注入或肖特基栅极区。源极，沟道，漂移和漏极层可以外延生长。到源极，栅极和漏极区域的欧姆接触可以形成在晶片的同一侧上。器件可以具有取决于垂直沟道宽度的不同阈值电压，并且可以针对相同沟道掺杂的耗尽和增强的工作模式实现。该器件可用于数字，模拟和单片微波集成电路。还描述了制造包括这些器件的晶体管和集成电路的方法。

4. 发明授权

US07556994B2 Normally-off integrated JFET power switches in wide bandgap semiconductors and methods of making 有权
标题翻译：宽带隙半导体中的常规集成JFET电源开关及其制造方法
公开(公告)号：US07556994B2
公开(公告)日：2009-07-07
申请号：US11783224
申请日：2007-04-06
申请人： Igor Sankin , Joseph N. Merrett
发明人： Igor Sankin , Joseph N. Merrett
IPC分类号： H01L29/72
CPC分类号： H03K17/567 , H01L27/098 , H01L29/1608 , H01L29/2003 , H01L29/808 , H01L29/8083 , H01L29/8086 , H01L29/861 , H01L29/868 , H01L29/872
摘要： Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single-or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature-tolerant and radiation-resistant electronics components. Methods of making the devices are also described.
摘要翻译：描述了包括常闭VJFET集成功率开关的宽带隙半导体器件。功率开关可以单片或混合地实现，并且可以与内置在单芯片或多芯片宽带隙功率半导体模块中的控制电路集成。该器件可用于高功率，耐温和耐辐射电子元件。还描述了制造装置的方法。

5. 发明申请

US20070275527A1 SELF-ALIGNED TRENCH FIELD EFFECT TRANSISTORS WITH REGROWN GATES AND BIPOLAR JUNCTION TRANSISTORS WITH REGROWN BASE CONTACT REGIONS AND METHODS OF MAKING 有权
标题翻译：具有复位栅的自对准TRENCH场效应晶体管和带有基极接触区的双极晶体管晶体管和制造方法
公开(公告)号：US20070275527A1
公开(公告)日：2007-11-29
申请号：US11293261
申请日：2005-12-05
申请人： Joseph Merrett , Igor Sankin
发明人： Joseph Merrett , Igor Sankin
IPC分类号： H01L21/336
CPC分类号： H01L29/66068 , H01L29/732 , H01L29/808
摘要： Junction field-effect transistors with vertical channels and self-aligned regrown gates and methods of making these devices are described. The methods use techniques to selectively grow and/or selectively remove semiconductor material to form a p-n junction gate along the sides of the channel and on the bottom of trenches separating source fingers. Methods of making bipolar junction transistors with self-aligned regrown base contact regions and methods of making these devices are also described. The semiconductor devices can be made in silicon carbide.
摘要翻译：描述了具有垂直沟道和自对准再生栅的结型场效应晶体管和制造这些器件的方法。所述方法使用技术来选择性地生长和/或选择性地去除半导体材料，以沿着沟道的侧面和分离源极指的沟槽的底部形成p-n结栅极。还描述了制造具有自对准重新生长的基极接触区域的双极结型晶体管的方法以及制造这些器件的方法。半导体器件可以制成碳化硅。

6. 发明申请

US20060113561A1 Lateral trench field-effect transistors in wide bandgap semiconductor materials, methods of making, and integrated circuits incorporating the transistors 有权
公开(公告)号：US20060113561A1
公开(公告)日：2006-06-01
申请号：US10999954
申请日：2004-12-01
申请人： Igor Sankin , Jeffrey Casady , Joseph Merrett
发明人： Igor Sankin , Jeffrey Casady , Joseph Merrett
IPC分类号： H01L31/111 , H01L21/332
CPC分类号： H01L29/2003 , H01L27/098 , H01L29/1608 , H01L29/47 , H01L29/808 , H01L29/8122
摘要： A junction field effect transistor is described. The transistor is made from a wide bandgap semiconductor material. The device comprises source, channel, drift and drain semiconductor layers, as well as p-type implanted or Schottky gate regions. The source, channel, drift and drain layers can be epitaxially grown. The ohmic contacts to the source, gate, and drain regions can be formed on the same side of the wafer. The devices can have different threshold voltages depending on the vertical channel width and can be implemented for both depletion and enhanced modes of operation for the same channel doping. The devices can be used for digital, analog, and monolithic microwave integrated circuits. Methods for making the transistors and integrated circuits comprising the devices are also described.

7. 发明授权

US08502282B2 Normally-off integrated JFET power switches in wide bandgap semiconductors and methods of making 有权
标题翻译：宽带隙半导体中的常规集成JFET电源开关及其制造方法
公开(公告)号：US08502282B2
公开(公告)日：2013-08-06
申请号：US13207623
申请日：2011-08-11
申请人： Igor Sankin , Joseph Neil Merrett
发明人： Igor Sankin , Joseph Neil Merrett
IPC分类号： H01L21/337
CPC分类号： H01L29/808 , H01L27/098 , H01L29/0619 , H01L29/1608 , H01L29/2003 , H01L29/8083 , H01L29/8122 , H01L29/8124 , H01L29/861 , H01L29/868 , H01L29/872 , H03K17/08142 , H03K17/08148 , H03K17/567 , H03K17/6871 , H03K2017/6875
摘要： Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single- or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature-tolerant and radiation-resistant electronics components. Methods of making the devices are also described.
摘要翻译：描述了包括常闭VJFET集成功率开关的宽带隙半导体器件。功率开关可以单片或混合地实现，并且可以与内置在单芯片或多芯片宽带隙功率半导体模块中的控制电路集成。该器件可用于高功率，耐温和耐辐射电子元件。还描述了制造装置的方法。

8. 发明授权

US08269262B2 Vertical junction field effect transistor with mesa termination and method of making the same 有权
标题翻译：垂直结场效应晶体管与台面端接及制作方法相同
公开(公告)号：US08269262B2
公开(公告)日：2012-09-18
申请号：US11836994
申请日：2007-08-10
申请人： Igor Sankin , Joseph Neil Merrett
发明人： Igor Sankin , Joseph Neil Merrett
IPC分类号： H01L29/66
CPC分类号： H01L29/868 , H01L29/1608 , H01L29/872
摘要： A vertical junction field effect transistor (VJFET) having a mesa termination and a method of making the device are described. The device includes: an n-type mesa on an n-type substrate; a plurality of raised n-type regions on the mesa comprising an upper n-type layer on a lower n-type layer; p-type regions between and adjacent the raised n-type regions and along a lower sidewall portion of the raised regions; dielectric material on the sidewalls of the raised regions, on the p-type regions and on the sidewalls of the mesa; and electrical contacts to the substrate (drain), p-type regions (gate) and the upper n-type layer (source). The device can be made in a wide-bandgap semiconductor material such as SiC. The method includes selectively etching through an n-type layer using a mask to form the raised regions and implanting p-type dopants into exposed surfaces of an underlying n-type layer using the mask.
摘要翻译：描述具有台面终止的垂直结型场效应晶体管（VJFET）和制造该器件的方法。该装置包括：n型衬底上的n型台面; 在台面上的多个凸起的n型区域，包括在下n型层上的上n型层; 在凸起的n型区域之间和相邻的凸起区域的下侧壁部分之间的p型区域; 介电材料在凸起区域的侧壁上，在p型区域和台面的侧壁上; 和与基板（漏极），p型区域（gate）和上部n型层（源极）的电接触。该器件可以制成诸如SiC的宽带隙半导体材料。该方法包括使用掩模选择性地蚀刻n型层以形成凸起区域，并使用掩模将p型掺杂剂注入到下面的n型层的暴露表面中。

9. 发明申请

US20120025100A1 PHOTOLUMINESCENCE MEASUREMENT 有权
标题翻译：光致发光测量
公开(公告)号：US20120025100A1
公开(公告)日：2012-02-02
申请号：US13195163
申请日：2011-08-01
申请人： Arnold Allenic , Douglas Bacon , Benyamin Buller , John Christiansen , Erel Milshtein , Avner Regev , Igor Sankin
发明人： Arnold Allenic , Douglas Bacon , Benyamin Buller , John Christiansen , Erel Milshtein , Avner Regev , Igor Sankin
IPC分类号： G01J1/58
CPC分类号： H01L22/12 , G01N21/6489 , G01N21/9501 , G01N2021/6419 , G01N2021/6421 , G01N2021/646 , G01N2021/8411 , G01N2021/845
摘要： A photoluminescence measurement system can include an optical source.
摘要翻译：光致发光测量系统可以包括光源。

10. 发明申请

US20050199882A1 Self-aligned silicon carbide semiconductor devices and methods of making the same 有权
标题翻译：自对准碳化硅半导体器件及其制造方法
公开(公告)号：US20050199882A1
公开(公告)日：2005-09-15
申请号：US11076857
申请日：2005-03-11
申请人： Igor Sankin , Janna Casady , Joseph Merrett
发明人： Igor Sankin , Janna Casady , Joseph Merrett
IPC分类号： H01L29/15 , H01L31/0312
CPC分类号： H01L29/66068 , H01L29/1608 , H01L29/2003 , H01L29/42316 , H01L29/45 , H01L29/66863 , H01L29/8128
摘要： A self-aligned silicon carbide power MESFET with improved current stability and a method of making the device are described. The device, which includes raised source and drain regions separated by a gate recess, has improved current stability as a result of reduced surface trapping effects even at low gate biases. The device can be made using a self-aligned process in which a substrate comprising an n+-doped SiC layer on an n-doped SiC channel layer is etched to define raised source and drain regions (e.g., raised fingers) using a metal etch mask. The metal etch mask is then annealed to form source and drain ohmic contacts. A single- or multilayer dielectric film is then grown or deposited and anisotropically etched. A Schottky contact layer and a final metal layer are subsequently deposited using evaporation or another anisotropic deposition technique followed by an optional isotropic etch of dielectric layer or layers.
摘要翻译：描述了具有改善的电流稳定性的自对准碳化硅功率MESFET和制造该器件的方法。包括由栅极凹槽分开的升高的源极和漏极区域的器件由于即使在低栅极偏置处减小的表面俘获效应也具有改善的电流稳定性。可以使用自对准工艺来制造器件，其中蚀刻在n掺杂的SiC沟道层上包括n + +掺杂的SiC层的衬底以限定凸起的源极和漏极区域（例如，使用金属蚀刻掩模。然后将金属蚀刻掩模退火以形成源极和漏极欧姆接触。然后生长或沉积单层或多层介电膜并进行各向异性蚀刻。随后使用蒸发或其他各向异性沉积技术沉积肖特基接触层和最后的金属层，然后对电介质层或层进行任意的各向同性蚀刻。

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