会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 5. 发明申请
    • VERTICAL JUNCTION FIELD EFFECT TRANSISTOR WITH MESA TERMINATION AND METHOD OF MAKING THE SAME
    • 具有MESA终止的垂直连接场效应晶体管及其制造方法
    • US20120309154A1
    • 2012-12-06
    • US13587151
    • 2012-08-16
    • Igor SANKINJoseph Neil MERRETT
    • Igor SANKINJoseph Neil MERRETT
    • H01L21/336
    • H01L29/868H01L29/1608H01L29/872
    • A vertical junction field effect transistor (VJFET) having a mesa termination and a method of making the device are described. The device includes: an n-type mesa on an n-type substrate; a plurality of raised n-type regions on the mesa comprising an upper n-type layer on a lower n-type layer; p-type regions between and adjacent the raised n-type regions and along a lower sidewall portion of the raised regions; dielectric material on the sidewalls of the raised regions, on the p-type regions and on the sidewalls of the mesa; and electrical contacts to the substrate (drain), p-type regions (gate) and the upper n-type layer (source). The device can be made in a wide-bandgap semiconductor material such as SiC. The method includes selectively etching through an n-type layer using a mask to form the raised regions and implanting p-type dopants into exposed surfaces of an underlying n-type layer using the mask.
    • 描述具有台面终止的垂直结型场效应晶体管(VJFET)和制造该器件的方法。 该装置包括:n型衬底上的n型台面; 在台面上的多个凸起的n型区域,包括在下n型层上的上n型层; 在凸起的n型区域之间和相邻的凸起区域的下侧壁部分之间的p型区域; 介电材料在凸起区域的侧壁上,在p型区域和台面的侧壁上; 和与基板(漏极),p型区域(gate)和上部n型层(源极)的电接触。 该器件可以制成诸如SiC的宽带隙半导体材料。 该方法包括使用掩模选择性地蚀刻n型层以形成凸起区域,并使用掩模将p型掺杂剂注入到下面的n型层的暴露表面中。
    • 7. 发明授权
    • Vertical junction field effect transistor with mesa termination and method of making the same
    • 垂直结场效应晶体管与台面端接及制作方法相同
    • US08269262B2
    • 2012-09-18
    • US11836994
    • 2007-08-10
    • Igor SankinJoseph Neil Merrett
    • Igor SankinJoseph Neil Merrett
    • H01L29/66
    • H01L29/868H01L29/1608H01L29/872
    • A vertical junction field effect transistor (VJFET) having a mesa termination and a method of making the device are described. The device includes: an n-type mesa on an n-type substrate; a plurality of raised n-type regions on the mesa comprising an upper n-type layer on a lower n-type layer; p-type regions between and adjacent the raised n-type regions and along a lower sidewall portion of the raised regions; dielectric material on the sidewalls of the raised regions, on the p-type regions and on the sidewalls of the mesa; and electrical contacts to the substrate (drain), p-type regions (gate) and the upper n-type layer (source). The device can be made in a wide-bandgap semiconductor material such as SiC. The method includes selectively etching through an n-type layer using a mask to form the raised regions and implanting p-type dopants into exposed surfaces of an underlying n-type layer using the mask.
    • 描述具有台面终止的垂直结型场效应晶体管(VJFET)和制造该器件的方法。 该装置包括:n型衬底上的n型台面; 在台面上的多个凸起的n型区域,包括在下n型层上的上n型层; 在凸起的n型区域之间和相邻的凸起区域的下侧壁部分之间的p型区域; 介电材料在凸起区域的侧壁上,在p型区域和台面的侧壁上; 和与基板(漏极),p型区域(gate)和上部n型层(源极)的电接触。 该器件可以制成诸如SiC的宽带隙半导体材料。 该方法包括使用掩模选择性地蚀刻n型层以形成凸起区域,并使用掩模将p型掺杂剂注入到下面的n型层的暴露表面中。