会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 4. 发明申请
    • Self-aligned silicon carbide semiconductor devices and methods of making the same
    • 自对准碳化硅半导体器件及其制造方法
    • US20050199882A1
    • 2005-09-15
    • US11076857
    • 2005-03-11
    • Igor SankinJanna CasadyJoseph Merrett
    • Igor SankinJanna CasadyJoseph Merrett
    • H01L29/15H01L31/0312
    • H01L29/66068H01L29/1608H01L29/2003H01L29/42316H01L29/45H01L29/66863H01L29/8128
    • A self-aligned silicon carbide power MESFET with improved current stability and a method of making the device are described. The device, which includes raised source and drain regions separated by a gate recess, has improved current stability as a result of reduced surface trapping effects even at low gate biases. The device can be made using a self-aligned process in which a substrate comprising an n+-doped SiC layer on an n-doped SiC channel layer is etched to define raised source and drain regions (e.g., raised fingers) using a metal etch mask. The metal etch mask is then annealed to form source and drain ohmic contacts. A single- or multilayer dielectric film is then grown or deposited and anisotropically etched. A Schottky contact layer and a final metal layer are subsequently deposited using evaporation or another anisotropic deposition technique followed by an optional isotropic etch of dielectric layer or layers.
    • 描述了具有改善的电流稳定性的自对准碳化硅功率MESFET和制造该器件的方法。 包括由栅极凹槽分开的升高的源极和漏极区域的器件由于即使在低栅极偏置处减小的表面俘获效应也具有改善的电流稳定性。 可以使用自对准工艺来制造器件,其中蚀刻在n掺杂的SiC沟道层上包括n + +掺杂的SiC层的衬底以限定凸起的源极和漏极区域(例如, 使用金属蚀刻掩模。 然后将金属蚀刻掩模退火以形成源极和漏极欧姆接触。 然后生长或沉积单层或多层介电膜并进行各向异性蚀刻。 随后使用蒸发或其他各向异性沉积技术沉积肖特基接触层和最后的金属层,然后对电介质层或层进行任意的各向同性蚀刻。
    • 7. 发明申请
    • Self-aligned silicon carbide semiconductor devices and methods of making the same
    • 自对准碳化硅半导体器件及其制造方法
    • US20070122951A1
    • 2007-05-31
    • US11699509
    • 2007-01-30
    • Igor SankinJanna CasadyJoseph Merrett
    • Igor SankinJanna CasadyJoseph Merrett
    • H01L21/338
    • H01L29/66068H01L29/1608H01L29/2003H01L29/42316H01L29/45H01L29/66863H01L29/8128
    • A self-aligned silicon carbide power MESFET with improved current stability and a method of making the device are described. The device, which includes raised source and drain regions separated by a gate recess, has improved current stability as a result of reduced surface trapping effects even at low gate biases. The device can be made using a self-aligned process in which a substrate comprising an n+-doped SiC layer on an n-doped SiC channel layer is etched to define raised source and drain regions (e.g., raised fingers) using a metal etch mask. The metal etch mask is then annealed to form source and drain ohmic contacts. A single- or multilayer dielectric film is then grown or deposited and anisotropically etched. A Schottky contact layer and a final metal layer are subsequently deposited using evaporation or another anisotropic deposition technique followed by an optional isotropic etch of dielectric layer or layers.
    • 描述了具有改善的电流稳定性的自对准碳化硅功率MESFET和制造该器件的方法。 包括由栅极凹槽分开的升高的源极和漏极区域的器件由于即使在低栅极偏置处减小的表面俘获效应也具有改善的电流稳定性。 可以使用自对准工艺来制造器件,其中蚀刻在n掺杂的SiC沟道层上包括n + +掺杂的SiC层的衬底以限定凸起的源极和漏极区域(例如, 使用金属蚀刻掩模。 然后将金属蚀刻掩模退火以形成源极和漏极欧姆接触。 然后生长或沉积单层或多层介电膜并进行各向异性蚀刻。 随后使用蒸发或其他各向异性沉积技术沉积肖特基接触层和最后的金属层,然后对电介质层或层进行任意的各向同性蚀刻。