专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08102667B2 Method and apparatus for spatially optimizing surface mount pads on a ball grid array package 有权
标题翻译：用于空间优化球栅阵列封装上的表面安装焊盘的方法和装置
公开(公告)号：US08102667B2
公开(公告)日：2012-01-24
申请号：US12259250
申请日：2008-10-27
申请人： Jeffrey A. Underwood , Thomas J. Swirbel , Michael J. Watkins
发明人： Jeffrey A. Underwood , Thomas J. Swirbel , Michael J. Watkins
IPC分类号： H05K7/10 , H05K7/12 , H05K1/02
CPC分类号： G06F17/5072 , G06F2217/40 , H01L23/49816 , H01L23/49838 , H01L2924/0002 , H01L2924/00
摘要： Method and apparatus for spatially optimizing the arrangement of surface mount pads on a ball grid array package. An array containing T surface mount pads with a diameter less than or equal to 0.4 millimeter is arranged in an array of rows and columns less than or equal to 0.5 millimeters center-to-center. The array of pads is subdivided into N groups of pads respectively numbered Gx (for X from 1 to N), each group containing Px pads (for X from 1 to N). Each pad in each group is located so as to maximize the number of empty spaces Sz that are adjacent to each pad, where Sz=(Gx−1). The number of fanout possibilities for each group (Px*Sz) is calculated, and then the total number of fanout possibilities, FP, is calculated using the function Σ1N (Px*Sz). The resulting spatially optimized pattern has a quality score, FP/T, that is equal to or greater than 2.
摘要翻译：用于空间优化球栅阵列封装上的表面安装焊盘布置的方法和装置。具有直径小于或等于0.4毫米的T表面安装焊盘的阵列以小于或等于中心到中心的0.5毫米的行和列的阵列布置。焊盘阵列被细分为N组焊盘，分别编号为Gx（X为1至N），每组包含Px焊盘（X为1至N）。每个组中的每个焊盘被定位成使与每个焊盘相邻的空白空间Sz的数量最大化，其中Sz =（Gx-1）。计算每个组（Px * Sz）的扇出可能性的数量，然后使用函数＆Sgr; 1N（Px * Sz）计算出扇出可能性的总数FP。得到的空间优化图案具有等于或大于2的质量得分FP / T。

2. 发明申请

US20100101846A1 METHOD AND APPARATUS FOR SPATIALLY OPTIMIZING SURFACE MOUNT PADS ON A BALL GRID ARRAY PACKAGE 有权
标题翻译：用于空间优化表面贴装在球网阵列上的方法和装置
公开(公告)号：US20100101846A1
公开(公告)日：2010-04-29
申请号：US12259250
申请日：2008-10-27
申请人： Jeffrey A. Underwood , Thomas J. Swirbel , Michael J. Watkins
发明人： Jeffrey A. Underwood , Thomas J. Swirbel , Michael J. Watkins
IPC分类号： H05K1/16 , G06F17/50
CPC分类号： G06F17/5072 , G06F2217/40 , H01L23/49816 , H01L23/49838 , H01L2924/0002 , H01L2924/00
摘要： Method and apparatus for spatially optimizing the arrangement of surface mount pads on a ball grid array package. An array containing T surface mount pads with a diameter less than or equal to 0.4 millimeter is arranged in an array of rows and columns less than or equal to 0.5 millimeters center-to-center. The array of pads is subdivided into N groups of pads respectively numbered Gx (for X from 1 to N), each group containing Px pads (for X from 1 to N). Each pad in each group is located so as to maximize the number of empty spaces Sz that are adjacent to each pad, where Sz=(Gx−1). The number of fanout possibilities for each group (Px*Sz) is calculated, and then the total number of fanout possibilities, FP, is calculated using the function Σ1N (Px*Sz). The resulting spatially optimized pattern has a quality score, FP/T, that is equal to or greater than 2.
摘要翻译：用于空间优化球栅阵列封装上的表面安装焊盘布置的方法和装置。具有直径小于或等于0.4毫米的T表面安装焊盘的阵列以小于或等于中心到中心的0.5毫米的行和列的阵列布置。焊盘阵列被细分为N组焊盘，分别编号为Gx（X为1至N），每组包含Px焊盘（X为1至N）。每个组中的每个焊盘被定位成使与每个焊盘相邻的空白空间Sz的数量最大化，其中Sz =（Gx-1）。计算每个组（Px * Sz）的扇出可能性的数量，然后使用函数＆Sgr; 1N（Px * Sz）计算出扇出可能性的总数FP。得到的空间优化图案具有等于或大于2的质量得分FP / T。

3. 发明授权

US06990734B2 Methods for shielding one or more circuit of a printed circuit board 有权
标题翻译：屏蔽印刷电路板的一个或多个电路的方法
公开(公告)号：US06990734B2
公开(公告)日：2006-01-31
申请号：US10263006
申请日：2002-10-02
申请人： Jeffrey A. Underwood , John K. Arledge , Thomas J. Swirbel , Joaquin Barreto
发明人： Jeffrey A. Underwood , John K. Arledge , Thomas J. Swirbel , Joaquin Barreto
IPC分类号： H05K3/34
CPC分类号： H05K1/0218 , H01L2223/6622 , H05K1/0221 , H05K1/0222 , H05K1/113 , H05K3/4644 , H05K9/0039 , H05K2201/0715 , H05K2201/09036 , H05K2201/09509 , H05K2201/09809 , H05K2201/09972 , H05K2201/09981 , H05K2201/10553 , H05K2201/10969 , Y10T29/49117 , Y10T29/4913 , Y10T29/49144 , Y10T29/49155 , Y10T29/49156
摘要： Methods for forming a metal shield on a printed circuit board (10) include depositing a first layer of metal (41) on a substrate (22) of the printed circuit board (10), depositing a first layer of dielectric material (42) on the first layer of metal (41), printing one or more circuits (21, 21′) on the first dielectric layer (42), depositing a second layer of dielectric material (43) over the one or more printed circuits (21, 21′), forming a trench-like opening (44) in the two layers of dielectric material (42, 43) surrounding the one or more printed circuits (21, 21′) so that the metal of the first layer (41) is exposed by the trench-like opening (44), depositing a second layer of metal (27) on the second layer of dielectric material (43) such that the second layer of metal (27) plates the trench-like opening (44) and makes electrical contact with the first metal layer (41).
摘要翻译：在印刷电路板（10）上形成金属屏蔽的方法包括在印刷电路板（10）的基板（22）上沉积第一金属层（41），将第一层介电材料（42）沉积在所述第一金属层（41），在所述第一介电层（42）上印刷一个或多个电路（21,21'），在所述一个或多个印刷电路（21,21）上沉积第二介电材料层 '），在围绕所述一个或多个印刷电路（21,21'）的两层介电材料（42,43）中形成沟槽状开口（44），使得第一层（41）的金属暴露通过所述沟槽状开口（44），在所述第二介电材料层（43）上沉积第二金属层（27），使得所述第二金属层（27）平坦化所述沟槽状开口（44）并使与第一金属层（41）电接触。

4. 发明授权

US06653915B1 Coaxial transmission lines having grounding troughs on a printed circuit board 有权
标题翻译：同轴传输线在印刷电路板上具有接地槽
公开(公告)号：US06653915B1
公开(公告)日：2003-11-25
申请号：US09378351
申请日：1999-08-20
申请人： John K. Arledge , Joaquin Barreto , Thomas J. Swirbel , Jeffrey A. Underwood
发明人： John K. Arledge , Joaquin Barreto , Thomas J. Swirbel , Jeffrey A. Underwood
IPC分类号： H01P308
CPC分类号： H05K1/0221 , H01P11/005 , H05K3/0023 , H05K3/4644 , H05K2201/09036 , H05K2201/09809 , H05K2201/09981 , Y10T29/49016 , Y10T29/49117
摘要： A method of forming a coaxial transmission line on a high density PCB. A metal layer (102) on the PCB (104) forms the bottom part of the shield, and is covered by a first dielectric (112). Two parallel trenches (122) are formed in the first dielectric to reveal part (123) of the metal strip. The signal conductor (132) is then formed on the first dielectric. A second dielectric (142) covers the signal conductor and the first dielectric. A second set of two parallel trenches (172) are formed in the second dielectric immediately above the first two trenches. Metal deposit (182) is plated in the parallel trenches to contact the metal strip, and also covers a portion of the second dielectric that lies between the trenches, to create a shield. The resulting coaxial transmission line has a center conductor insulated from the shield by the dielectrics.
摘要翻译：一种在高密度PCB上形成同轴传输线的方法。 PCB（104）上的金属层（102）形成屏蔽的底部并被第一电介质（112）覆盖。在第一电介质中形成两个平行的沟槽（122），以露出金属条的部分（123）。信号导体（132）然后形成在第一电介质上。第二电介质（142）覆盖信号导体和第一电介质。第二组两个平行的沟槽（172）形成在紧邻第一两个沟槽上方的第二电介质中。金属沉积物（182）被电镀在平行的沟槽中以接触金属条，并且还覆盖位于沟槽之间的第二电介质的一部分以形成屏蔽。所得到的同轴传输线具有通过电介质与屏蔽层绝缘的中心导体。

5. 发明授权

US6000120A Method of making coaxial transmission lines on a printed circuit board 失效
标题翻译：在印刷电路板上制造同轴传输线的方法
公开(公告)号：US6000120A
公开(公告)日：1999-12-14
申请号：US61112
申请日：1998-04-16
申请人： John K. Arledge , Joaquin Barreto , Thomas J. Swirbel , Jeffrey A. Underwood
发明人： John K. Arledge , Joaquin Barreto , Thomas J. Swirbel , Jeffrey A. Underwood
IPC分类号： H01P11/00 , H05K1/02 , H05K3/00 , H05K3/46
CPC分类号： H05K1/0221 , H01P11/005 , H05K2201/09036 , H05K2201/09809 , H05K2201/09981 , H05K3/0023 , H05K3/4644 , Y10T29/49016 , Y10T29/49117
摘要： A method of forming a coaxial transmission line on a high density PCB. A metal strip (102) on the PCB (104) forms the bottom part of the shield, and is covered by a first dielectric (112). Two parallel trenches (122) are formed in the first dielectric to reveal part (123) of the metal strip. The signal conductor (132) is then formed on the first dielectric. A second dielectric (142) covers the signal conductor and the first dielectric. A second set of two parallel trenches (172) are formed in the second dielectric immediately above the first two trenches. Metal (182) is plated in the parallel trenches to contact the metal strip, and also covers a portion of the second dielectric that lies between the trenches, to create a shield. The resulting coaxial transmission line has a center conductor insulated from the shield by the dielectrics.
摘要翻译：一种在高密度PCB上形成同轴传输线的方法。 PCB（104）上的金属条（102）形成屏蔽的底部，并被第一电介质（112）覆盖。在第一电介质中形成两个平行的沟槽（122），以露出金属条的部分（123）。信号导体（132）然后形成在第一电介质上。第二电介质（142）覆盖信号导体和第一电介质。第二组两个平行的沟槽（172）形成在紧邻第一两个沟槽上方的第二电介质中。金属（182）电镀在平行的沟槽中以接触金属条，并且还覆盖位于沟槽之间的第二电介质的一部分，以形成屏蔽。所得到的同轴传输线具有通过电介质与屏蔽层绝缘的中心导体。

6. 发明授权

US07132357B2 Method for shielding printed circuit board circuits 有权
公开(公告)号：US07132357B2
公开(公告)日：2006-11-07
申请号：US11238894
申请日：2005-09-29
申请人： Jeffrey A. Underwood , John K. Arledge , Thomas J. Swirbel , Joaquin Barreto
发明人： Jeffrey A. Underwood , John K. Arledge , Thomas J. Swirbel , Joaquin Barreto
IPC分类号： H01L21/44
CPC分类号： H05K1/0218 , H01L2223/6622 , H05K1/0221 , H05K1/0222 , H05K1/113 , H05K3/4644 , H05K9/0039 , H05K2201/0715 , H05K2201/09036 , H05K2201/09509 , H05K2201/09809 , H05K2201/09972 , H05K2201/09981 , H05K2201/10553 , H05K2201/10969 , Y10T29/49117 , Y10T29/4913 , Y10T29/49144 , Y10T29/49155 , Y10T29/49156
摘要： A method for shielding one or more circuits (21, 21′) of a printed circuit board includes depositing a layer of dielectric material (43) over a printed circuit board substrate (22) and the printed circuits (21, 21′), creating a trench-like opening (44) in the dielectric layer (43) such that the trench-like opening (44) surrounds the one or more circuits (21, 21′) to be shielded, depositing a layer of metal (27) over the layer of dielectric material (43) and within the trench-like openings (44), creating a solder pad (24) at each location where an electrical connection is to be made to the printed circuits (21, 21′) by removing a border of the metal layer (27) surrounding each connection location, and providing a microvia (25) through each solder pad (24) penetrating the dielectric layer (43) and terminating at the metal of the printed circuit (21, 21′).

7. 发明授权

US06515222B2 Printed circuit board arrangement 有权
标题翻译：印刷电路板布置
公开(公告)号：US06515222B2
公开(公告)日：2003-02-04
申请号：US09775460
申请日：2001-02-05
申请人： Jeffrey A. Underwood , John K. Arledge , Thomas J. Swirbel , Joaquin Barreto
发明人： Jeffrey A. Underwood , John K. Arledge , Thomas J. Swirbel , Joaquin Barreto
IPC分类号： H05K900
CPC分类号： H05K1/0218 , H01L2223/6622 , H05K1/0221 , H05K1/0222 , H05K1/113 , H05K3/4644 , H05K9/0039 , H05K2201/0715 , H05K2201/09036 , H05K2201/09509 , H05K2201/09809 , H05K2201/09972 , H05K2201/09981 , H05K2201/10553 , H05K2201/10969 , Y10T29/49117 , Y10T29/4913 , Y10T29/49144 , Y10T29/49155 , Y10T29/49156
摘要： Methods and apparatus for forming a metal shield on a printed circuit board (10) include a layer of dielectric material (23) one or more printed circuits (21) on the layer of dielectric material (23), a layer of metal (27) on the layer of dielectric material (23), a metal-clad trench or opening surrounding the printed circuit (44) and electrically connected to the layer of metal(27), a solder pad (24) on the layer of dielectric material (23), a microvia (25) through the solder pad (24) and the layer of dielectric material (23), and electrical components (11) soldered to the solder pads (24) and to the printed circuit (21).
摘要翻译：在印刷电路板（10）上形成金属屏蔽的方法和装置包括介电材料层（23），介电材料层（23）上的一个或多个印刷电路（21），金属层（27）在电介质材料层（23）上，围绕印刷电路（44）并电连接到金属层（27）的金属包覆沟槽或开口，介电材料层（23）上的焊盘（24）），通过焊盘（24）和电介质材料层（23）的微孔（25）以及焊接到焊盘（24）和印刷电路（21）的电气部件（11）。

8. 发明授权

US6091194A Active matrix display 失效
标题翻译：主动矩阵显示
公开(公告)号：US6091194A
公开(公告)日：2000-07-18
申请号：US926627
申请日：1997-09-10
申请人： Thomas J. Swirbel , Patrick M. Dunn
发明人： Thomas J. Swirbel , Patrick M. Dunn
IPC分类号： H01L27/32 , H05B33/14
CPC分类号： H01L27/3253
摘要： A flat panel display (10) uses active matrix addressing. Two parallel substrates (20, 30) have an organic electroluminescent medium (40) that emits visible light in response to an electrical signal, sandwiched between them. The top substrate is transparent to allow emitted light (50) to be discernible to an observer. The bottom substrate does not need to be transparent, as the active matrix display operates in a emissive or reflective mode. An array of electrodes (22) is situated on an inside face of the bottom substrate, and a transparent electrode (32) corresponding to the array is situated on an inside face of the top substrate. The electrodes serve to define an array of pixels. A number of switches (24) are located on the backside of the bottom substrate, and are each connected to respective electrodes (22) by an electrically conductive via (28) in the bottom substrate.
摘要翻译：平板显示器（10）使用有源矩阵寻址。两个平行的基板（20,30）具有有机电致发光介质（40），其响应于电信号发射可见光，夹在它们之间。顶部衬底是透明的，以允许发射光（50）对观察者可辨别。底部衬底不需要是透明的，因为有源矩阵显示器以发射或反射模式工作。电极阵列（22）位于底部基板的内表面上，并且对应于阵列的透明电极（32）位于顶部基板的内表面上。电极用于限定像素阵列。多个开关（24）位于底部基板的背面，并且各自通过底部基板中的导电通孔（28）连接到相应的电极（22）。

9. 发明授权

US5773198A Method of forming high resolution circuitry by depositing a polyvinyl alcohol layer beneath a photosensitive polymer layer 失效
标题翻译：通过在感光聚合物层下沉积聚乙烯醇层形成高分辨率电路的方法
公开(公告)号：US5773198A
公开(公告)日：1998-06-30
申请号：US660384
申请日：1996-06-07
申请人： Thomas J. Swirbel , Anthony B. Suppelsa , Joaquin Barreto
发明人： Thomas J. Swirbel , Anthony B. Suppelsa , Joaquin Barreto
IPC分类号： G03F7/09 , H05K3/10 , G03C5/56
CPC分类号： H05K3/108 , G03F7/092 , H05K2203/0577 , H05K2203/0789 , Y10S438/95 , Y10S438/951
摘要： A method of forming a high resolution metal pattern on a substrate. A temporary polyvinyl alcohol (10) layer underneath the photoresist layer (20) aids in removing the photoresist layer after plating. The photoresist is photodelineated in conventional manner to form a pattern (40). During photodelineation, the developing process for the resist does not completely remove the PVA (45) that lies directly under the removed resist, but instead reveals those portions of the polyvinyl alcohol layer. The substrate is then rinsed in a hot aqueous solution to effect removal of the revealed PVA portions, now exposing portions (40) of the substrate (15). Metal (50) is then electroplated to build up a metal circuitry pattern. The remaining portions of the photoresist and the PVA are then removed by a hot aqueous solution.
摘要翻译：在基板上形成高分辨率金属图案的方法。在光致抗蚀剂层（20）下面的临时聚乙烯醇（10）层有助于在电镀后去除光致抗蚀剂层。光致抗蚀剂以常规方式光线照射以形成图案（40）。在光线照射期间，抗蚀剂的显影过程不能完全去除位于去除的抗蚀剂正下方的PVA（45），而是透露聚乙烯醇层的那些部分。然后将衬底在热水溶液中漂洗以实现所揭露的PVA部分的去除，现在暴露衬底（15）的部分（40）。然后电镀金属（50）以建立金属电路图案。然后通过热水溶液除去光致抗蚀剂和PVA的剩余部分。

10. 发明授权

US5591480A Method for fabricating metallization patterns on an electronic substrate 失效
标题翻译：在电子基板上制造金属化图案的方法
公开(公告)号：US5591480A
公开(公告)日：1997-01-07
申请号：US517392
申请日：1995-08-21
申请人： Douglas H. Weisman , Thomas J. Swirbel , John K. Arledge
发明人： Douglas H. Weisman , Thomas J. Swirbel , John K. Arledge
IPC分类号： G02F1/1345 , H01L21/48 , H03H3/08 , H05K3/06 , H05K3/24 , B05D5/12 , C23C14/00 , C25D5/02 , H01L21/465
CPC分类号： H05K3/243 , H01L21/4846 , H03H3/08 , G02F1/1345 , H05K2201/0326 , H05K2203/0384 , H05K2203/095 , H05K3/062 , H05K3/064
摘要： One method for fabricating solderable pads (406) onto a substrate (220) for direct chip attachment uses a multilayer metallization coating (500). The coating has a bottom layer (202) of indium-tin oxide, with an intermediate layer (204) of copper and a top layer (206) of indium-tin oxide. A masking layer (208) is deposited on the active display area (402) of the substrate, leaving the bonding pads uncovered. The revealed bonding pads are then plasma etched, using the polyimide as an etch resist, and the top layer of ITO is selectively removed to reveal the underlying copper layer. The exposed copper layer (204) is then plated with a solderable metal to the desired thickness to form bonding pads that may be used with direct chip attachment schemes.
摘要翻译：用于将可焊焊盘（406）制造到用于直接芯片附接的基板（220）上的一种方法使用多层金属化涂层（500）。涂层具有铟锡氧化物的底层（202），其中铜的中间层（204）和氧化铟锡的顶层（206）。掩模层（208）沉积在衬底的有源显示区域（402）上，留下焊盘未被覆盖。然后使用聚酰亚胺作为抗蚀剂，然后等离子体蚀刻所揭示的接合焊盘，并且选择性地去除ITO的顶层以露出下面的铜层。然后将暴露的铜层（204）用可焊接金属镀覆至所需厚度，以形成可与直接芯片附接方案一起使用的焊盘。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式