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1. 发明授权

US07000155B2 Redundancy register architecture for soft-error tolerance and methods of making the same 失效
公开(公告)号：US07000155B2
公开(公告)日：2006-02-14
申请号：US10249574
申请日：2003-04-21
申请人： Jeffery H. Oppold , Michael R. Ouellette , Larry Wissel
发明人： Jeffery H. Oppold , Michael R. Ouellette , Larry Wissel
IPC分类号： G11C29/00
CPC分类号： G11C5/005 , G11C11/4125 , G11C29/787
摘要： A redundancy register architecture associated with a RAM provides for soft-error tolerance. An enable register provides soft error rate protection to the registers that contain replacement information for redundant rows and columns. The gate register determines whether a row or column replacement register contains a specific address, and parity protection to the replacement register is activated as necessitated. The register architecture is changed to make the register state a “don't care” state for the majority of the registers. A small number of registers that are critical to the redundancy system are identified and made more robust to upsets. Word-line and column-line substitution is implemented. A ripple parity scheme is implemented when parity checks are activated.

2. 发明授权

US6002633A Performance optimizing compiler for building a compiled SRAM 失效
标题翻译：用于构建编译的SRAM的性能优化编译器
公开(公告)号：US6002633A
公开(公告)日：1999-12-14
申请号：US225075
申请日：1999-01-04
申请人： Jeffery H. Oppold , Michael R. Ouellette , Michael J. Sullivan
发明人： Jeffery H. Oppold , Michael R. Ouellette , Michael J. Sullivan
IPC分类号： G11C8/12 , G11C8/00 , G11C11/00
CPC分类号： G11C8/12
摘要： A compiler for building at least one compilable SRAM including at least one compilable sub-block. A global control clock generation circuit generates a global control signal. At least one local control logic and speed control circuit controls the at least one compilable sub-block. The local control logic and speed control circuit is controlled by the global control signal. An algorithm receives an input capacity and configuration for the sub-block of the SRAM array. An algorithm determines a number of wordlines and bitlines required to create the sub-block of the input capacity. An algorithm optimizes a cycle time of the sub-block by determining global control clock circuits based upon the number of wordlines and bitlines in the sub-block. An algorithm optimizes access time of the sub-block by determining local speed control circuits based upon the number of wordlines and bitlines.
摘要翻译：一种用于构建至少一个可编译SRAM（包括至少一个可编译子块）的编译器。全局控制时钟产生电路产生全局控制信号。至少一个本地控制逻辑和速度控制电路控制该至少一个可编译子块。本地控制逻辑和速度控制电路由全局控制信号控制。算法接收SRAM阵列的子块的输入容量和配置。算法确定创建输入容量的子块所需的字数和位线数。算法通过基于子块中的字线和位线的数量确定全局控制时钟电路来优化子块的周期时间。算法通过基于字线和位线的数量确定本地速度控制电路来优化子块的访问时间。

3. 发明授权

US5737270A Precharged wordline decoder with locally-controlled clock 失效
标题翻译：带本地控制时钟的预充电字线解码器
公开(公告)号：US5737270A
公开(公告)日：1998-04-07
申请号：US680081
申请日：1996-07-15
申请人： Jeffery H. Oppold , Michael R. Ouellette , James A. Svarczkopf , Daved J. Wager
发明人： Jeffery H. Oppold , Michael R. Ouellette , James A. Svarczkopf , Daved J. Wager
IPC分类号： G11C8/10 , G11C8/00
CPC分类号： G11C8/10
摘要： A precharge wordline decoder is disclosed that comprises a first logic circuit that receives a first clock signal from a clock driver for enabling the discharge element within the first logic circuit. The wordline decoder further comprises a delay circuit for generating a predetermined delayed clock signal from the first clock signal, the delayed clock signal being locally-controlled. A second logic circuit of the wordline decoder receives the delayed clock signal for controlling wordline driver elements. The first logic circuit also receives the delayed clock signal for disabling the precharge elements of the decoder.
摘要翻译：公开了一种预充电字线解码器，其包括第一逻辑电路，该第一逻辑电路从时钟驱动器接收第一时钟信号，以使能第一逻辑电路内的放电元件。字线解码器还包括用于从第一时钟信号产生预定延迟时钟信号的延迟电路，延迟的时钟信号被局部控制。字线解码器的第二逻辑电路接收用于控制字线驱动器元件的延迟时钟信号。第一逻辑电路还接收用于禁止解码器的预充电元件的延迟时钟信号。

4. 发明授权

US07098721B2 Low voltage programmable eFuse with differential sensing scheme 有权
标题翻译：低电压可编程eFuse与差分传感方案
公开(公告)号：US07098721B2
公开(公告)日：2006-08-29
申请号：US10711205
申请日：2004-09-01
申请人： Michael R. Ouellette , Larry Wissel
发明人： Michael R. Ouellette , Larry Wissel
IPC分类号： H01H37/76
CPC分类号： G11C29/027 , G11C17/14 , G11C17/16 , G11C17/18 , G11C29/02 , G11C29/50 , H01L2924/0002 , H01L2924/00
摘要： An electronic fuse structure is disclosed for integrated circuits that is programmable with low voltage and incorporates a differential sensing scheme. The programming step is performed at about 1.5 times Vdd while the sense operation is performed at Vdd, which limits the resistance variation through the electronic fuse caused by the sense operation. During the sense operation a gating transistor emulates the voltage drop across a fuse select transistor for the case of an intact fuse. A circuit and method for characterizing the resistance of the electronic fuse is also disclosed.
摘要翻译：公开了一种用于低电压编程的集成电路的电子熔丝结构，并结合了差分感测方案。在Vdd执行感测操作时，以大约1.5倍的Vdd执行编程步骤，这限制了由感测操作引起的电子熔断器的电阻变化。在感测操作期间，门控晶体管模拟保险丝选择晶体管上的电压降，用于完整的熔丝的情况。还公开了用于表征电子熔断器的电阻的电路和方法。

5. 发明授权

US08823491B2 Security-enhanced radio frequency object locator system, method and program storage device 有权
标题翻译：安全增强射频对象定位系统，方法和程序存储设备
公开(公告)号：US08823491B2
公开(公告)日：2014-09-02
申请号：US13348866
申请日：2012-01-12
申请人： Shawn M. Luke , Michael R. Ouellette , Karl V. Swanke , Sebastian T. Ventrone
发明人： Shawn M. Luke , Michael R. Ouellette , Karl V. Swanke , Sebastian T. Ventrone
IPC分类号： G08B5/22 , G08B13/14 , G08B1/08 , G01S13/08 , G01B11/14
CPC分类号： G08B21/24
摘要： Disclosed are an object locator system, a method and a program storage device. In the embodiments, radio frequency identification (RFID) tags are on objects within a defined area and each RFID tag can be activated by an RF activation signal. When a request (e.g., a verbal or keyed-in request) to locate a specific object is received from a specific user, the required permission to locate the object is verified and, optionally, the identity of the specific user is authenticated. Once the required permission is verified and the identity of the specific user is authenticated, one of three RFID readers transmits an RF activation signal. RF response signals received back at the three RFID readers from the specific object's RFID tag are used to triangulate the position of the specific object. Once determined, the position is communicated (e.g., by map display, verbal message, or text message) to the specific user.
摘要翻译：公开了一种对象定位器系统，方法和程序存储装置。在实施例中，射频识别（RFID）标签位于限定区域内的对象上，并且每个RFID标签可由RF激活信号激活。当从特定用户接收到用于定位特定对象的请求（例如，语言或密钥请求）时，验证定位对象的所需许可证，并且可选地，特定用户的身份被认证。一旦验证了所需许可并且认证了特定用户的身份，三个RFID读取器中的一个发送RF激活信号。使用从特定对象的RFID标签在三个RFID读取器处接收的RF响应信号来对特定对象的位置进行三角测量。一旦确定，将位置（例如，通过地图显示，口头消息或文本消息）传达给特定用户。

6. 发明申请

US20140040685A1 BUILT-IN-SELF-TEST (BIST) ORGANIZATIONAL FILE GENERATION 有权
标题翻译：内部自检（BIST）组织文件生成
公开(公告)号：US20140040685A1
公开(公告)日：2014-02-06
申请号：US13567127
申请日：2012-08-06
申请人： Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague
发明人： Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague
IPC分类号： G11C29/12
CPC分类号： G11C29/54 , G11C5/04 , G11C29/12
摘要： Aspects of the invention provide for creating a built-in-self-test (BIST) organizational file for an integrated circuit (IC) chip. In one embodiment, a method includes: receiving a design file including a hierarchy of memory modules, each module including a plurality of memory wrappers; scanning each memory wrapper in each hierarchical level of memory modules for a BIST type; creating, based on the hierarchical level and the BIST type, an ordered list of memory wrappers; adding, based on the BIST type, a BIST engine for each memory wrapper listed in the ordered list; and adding a plurality of references statements to the ordered list to create the BIST organizational file.
摘要翻译：本发明的方面提供了用于为集成电路（IC）芯片创建内置自测（BIST）组织文件。在一个实施例中，一种方法包括：接收包括存储器模块层级的设计文件，每个模块包括多个存储器包装器; 在BIST类型的每个层级的内存模块中扫描每个内存包装器; 基于层次级别和BIST类型创建存储器包装器的有序列表; 根据BIST类型添加一个BIST引擎，用于在有序列表中列出的每个内存包装器; 并将多个引用语句添加到有序列表以创建BIST组织文件。

7. 发明申请

US20130181838A1 SECURITY-ENHANCED RADIO FREQUENCY OBJECT LOCATOR SYSTEM, METHOD AND PROGRAM STORAGE DEVICE 有权
标题翻译：安全增强无线电频率对象定位系统，方法和程序存储设备
公开(公告)号：US20130181838A1
公开(公告)日：2013-07-18
申请号：US13348866
申请日：2012-01-12
申请人： Shawn M. Luke , Michael R. Ouellette , Karl V. Swanke , Sebastian T. Ventrone
发明人： Shawn M. Luke , Michael R. Ouellette , Karl V. Swanke , Sebastian T. Ventrone
IPC分类号： G08B13/14
CPC分类号： G08B21/24
摘要： Disclosed are an object locator system, a method and a program storage device. In the embodiments, radio frequency identification (RFID) tags are on objects within a defined area and each RFID tag can be activated by an RF activation signal. When a request (e.g., a verbal or keyed-in request) to locate a specific object is received from a specific user, the required permission to locate the object is verified and, optionally, the identity of the specific user is authenticated. Once the required permission is verified and the identity of the specific user is authenticated, one of three RFID readers transmits an RF activation signal. RF response signals received back at the three RFID readers from the specific object's RFID tag are used to triangulate the position of the specific object. Once determined, the position is communicated (e.g., by map display, verbal message, or text message) to the specific user.
摘要翻译：公开了一种对象定位器系统，方法和程序存储装置。在实施例中，射频识别（RFID）标签位于限定区域内的对象上，并且每个RFID标签可由RF激活信号激活。当从特定用户接收到用于定位特定对象的请求（例如，语言或密钥请求）时，验证定位对象所需的许可，并且可选地，特定用户的身份被认证。一旦验证了所需许可并且认证了特定用户的身份，三个RFID读取器中的一个发送RF激活信号。使用从特定对象的RFID标签在三个RFID读取器处接收的RF响应信号来对特定对象的位置进行三角测量。一旦确定，将位置（例如，通过地图显示，口头消息或文本消息）传达给特定用户。

8. 发明授权

US08467260B2 Structure and method for storing multiple repair pass data into a fusebay 有权
标题翻译：用于将多个修复传递数据存储到保险丝盒中的结构和方法
公开(公告)号：US08467260B2
公开(公告)日：2013-06-18
申请号：US13198894
申请日：2011-08-05
申请人： Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
发明人： Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
IPC分类号： G11C17/16
CPC分类号： G11C17/16 , G11C29/785 , G11C29/802
摘要： Fuse macros of identical number of pages are serially arranged to form the same number of fusebay pages each having a length equal to the sum of the respective fuse macro page lengths. Each fuse macro has an enable latch configured to allow activation of one fuse macro at a time. A fusebay control device connected to a repair register may store data in and retrieve data from the fusebay. Next available fuse location is determined in programming mode so that data from a next repair pass may start where the last data ended.
摘要翻译：相同页数的保险丝宏串联地形成相同数量的保险丝页，每个保险丝页的长度等于相应的熔丝宏页面长度之和。每个保险丝宏都有一个使能锁存器，配置为允许一次激活一个保险丝宏。连接到维修寄存器的保险丝控制装置可以将数据存储在保险丝盒中并从熔丝座检索数据。在编程模式下确定下一个可用的熔丝位置，以便下一个维修通过的数据可以在最后一个数据结束的地方开始。

9. 发明授权

US07916826B2 Diagnostic method and apparatus for non-destructively observing latch data 有权
标题翻译：用于非破坏性观察锁存数据的诊断方法和装置
公开(公告)号：US07916826B2
公开(公告)日：2011-03-29
申请号：US12175534
申请日：2008-07-18
申请人： Darren L. Anand , John R. Goss , Peter O. Jakobsen , Michael R. Ouellette , Thomas O. Sopchak , Donald L. Wheater
发明人： Darren L. Anand , John R. Goss , Peter O. Jakobsen , Michael R. Ouellette , Thomas O. Sopchak , Donald L. Wheater
IPC分类号： G11C19/00
CPC分类号： G11C19/00 , G11C29/003
摘要： The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit. An observation wire is connected to the wiring loop, and the data passes from the wiring loop to the control device through the observation wire. The control device outputs data appearing on the wiring loop as the data is circulated through the selected shift register to permit data within the selected shift register to be observed outside the circuit without altering the data within the selected shift register.
摘要翻译：本发明提供一种可以观察移位寄存器内的数据而不改变数据的电路。该电路包括连接到移位寄存器的输入和输出的选择器。选择器选择性地将输入与所选移位寄存器的输出连接，以形成所选移位寄存器的布线回路。连接到布线回路的控制装置使用布线回路使得数据从所选择的移位寄存器的输出连续地传送到所选择的移位寄存器的输入端并循环地返回所选择的移位寄存器。控制装置包括用于确定所选择的移位寄存器的长度的计数器和一组寄存器，用于存储当在移位寄存器中旋转数据时将来使用的每个移位寄存器的长度。控制装置还包括从电路外部可访问的数据输出。观察线连接到布线回路，数据通过观察线从布线回路传递到控制装置。当数据通过选定的移位寄存器循环时，控制装置输出出现在布线环路上的数据，以允许在电路外观察所选移位寄存器内的数据，而不改变所选移位寄存器内的数据。

10. 发明授权

US07821294B2 Integrated circuit containing multi-state restore circuitry for restoring state to a power-managed functional block 有权
标题翻译：包含用于将状态恢复到功率管理功能块的多状态恢复电路的集成电路
公开(公告)号：US07821294B2
公开(公告)日：2010-10-26
申请号：US12135249
申请日：2008-06-09
申请人： Susan K. Lichtensteiger , Michael R. Ouellette , Raymond W. M. Schuppe , Sebastian T. Ventrone
发明人： Susan K. Lichtensteiger , Michael R. Ouellette , Raymond W. M. Schuppe , Sebastian T. Ventrone
IPC分类号： H03K19/173
CPC分类号： H03K19/0008 , H03K19/173
摘要： Multi-state restore circuitry that allows storage elements of a power-managed functional block to be loaded when the functional block is repowered up so that the functional block is ready for operation virtually immediately after voltage ramp-up of the functional block. The multi-state restore circuitry includes a restore-state detector for determining which one of a plurality of restore states of the functional block is applicable to a particular repowering-up of the functional block. The multi-state restore circuitry also includes restore logic that loads the storage elements as a function of the restore state determined by the restore-state detector.
摘要翻译：多功能恢复电路，允许在功能块被重新加电时加载功率管理功能块的存储元件，使得功能块在功能块的电压升高之后实际上准备好运行。多状态恢复电路包括恢复状态检测器，用于确定功能块的多个恢复状态中的哪一个可应用于功能块的特定重新启动。多状态恢复电路还包括根据由恢复状态检测器确定的恢复状态来加载存储元件的恢复逻辑。

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