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1. 发明授权

US07821294B2 Integrated circuit containing multi-state restore circuitry for restoring state to a power-managed functional block 有权
标题翻译：包含用于将状态恢复到功率管理功能块的多状态恢复电路的集成电路
公开(公告)号：US07821294B2
公开(公告)日：2010-10-26
申请号：US12135249
申请日：2008-06-09
申请人： Susan K. Lichtensteiger , Michael R. Ouellette , Raymond W. M. Schuppe , Sebastian T. Ventrone
发明人： Susan K. Lichtensteiger , Michael R. Ouellette , Raymond W. M. Schuppe , Sebastian T. Ventrone
IPC分类号： H03K19/173
CPC分类号： H03K19/0008 , H03K19/173
摘要： Multi-state restore circuitry that allows storage elements of a power-managed functional block to be loaded when the functional block is repowered up so that the functional block is ready for operation virtually immediately after voltage ramp-up of the functional block. The multi-state restore circuitry includes a restore-state detector for determining which one of a plurality of restore states of the functional block is applicable to a particular repowering-up of the functional block. The multi-state restore circuitry also includes restore logic that loads the storage elements as a function of the restore state determined by the restore-state detector.
摘要翻译：多功能恢复电路，允许在功能块被重新加电时加载功率管理功能块的存储元件，使得功能块在功能块的电压升高之后实际上准备好运行。多状态恢复电路包括恢复状态检测器，用于确定功能块的多个恢复状态中的哪一个可应用于功能块的特定重新启动。多状态恢复电路还包括根据由恢复状态检测器确定的恢复状态来加载存储元件的恢复逻辑。

2. 发明申请

US20090307637A1 METHOD OF DESIGNING MULTI-STATE RESTORE CIRCUITRY FOR RESTORING STATE TO A POWER-MANAGED FUNCTIONAL BLOCK 有权
标题翻译：设计多状态恢复电路以将状态恢复到功率管理的功能块的方法
公开(公告)号：US20090307637A1
公开(公告)日：2009-12-10
申请号：US12135250
申请日：2008-06-09
申请人： Susan K. Lichtensteiger , Michael R. Ouellette , Raymond W. M. Schuppe , Sebastian T. Ventrone
发明人： Susan K. Lichtensteiger , Michael R. Ouellette , Raymond W. M. Schuppe , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/72
摘要： Methods of designing and testing restore logic for restoring values to storage elements of power-managed logic circuitry. In one implementation, a design method disclosed includes providing a design of the logic circuitry that, when instantiated, will have a number of states it can be returned to upon repowering-up the logic circuitry. Values held by the storage elements are determined and utilized to categorize the storage elements into categories that allow the development of restore logic that will restore the state of the power-managed logic circuitry that is appropriate to the particular powering-up. The restore logic design is tested by modeling it and the power-managed logic circuitry in a hardware description language and simulating the number of states over a number of test cases. If the design and testing are successful, the restore logic can be optimized for instantiation into an actual integrated circuit.
摘要翻译：设计和测试还原逻辑的方法，用于将功能管理逻辑电路的存储元件恢复为值。在一个实施方式中，所公开的设计方法包括提供逻辑电路的设计，当被实例化时，逻辑电路将具有多个状态，可以在重新启动逻辑电路时将其返回。由存储元件保存的值被确定并用于将存储元件分类成允许开发还原逻辑的类别，恢复逻辑将恢复适合于特定供电的功率管理逻辑电路的状态。恢复逻辑设计通过对硬件描述语言进行建模和功耗管理的逻辑电路进行测试，并通过多个测试用例模拟状态数量。如果设计和测试成功，则可以将恢复逻辑优化为实例化为实际的集成电路。

3. 发明授权

US08239791B2 Method of designing multi-state restore circuitry for restoring state to a power managed functional block 有权
标题翻译：设计用于将状态恢复到功率管理功能块的多状态恢复电路的方法
公开(公告)号：US08239791B2
公开(公告)日：2012-08-07
申请号：US12135250
申请日：2008-06-09
申请人： Susan K. Lichtensteiger , Michael R. Ouellette , Raymond W. M. Schuppe , Sebastian T. Ventrone
发明人： Susan K. Lichtensteiger , Michael R. Ouellette , Raymond W. M. Schuppe , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/72
摘要： Methods of designing and testing restore logic for restoring values to storage elements of power-managed logic circuitry. In one implementation, a design method disclosed includes providing a design of the logic circuitry that, when instantiated, will have a number of states it can be returned to upon repowering-up the logic circuitry. Values held by the storage elements are determined and utilized to categorize the storage elements into categories that allow the development of restore logic that will restore the state of the power-managed logic circuitry that is appropriate to the particular powering-up. The restore logic design is tested by modeling it and the power-managed logic circuitry in a hardware description language and simulating the number of states over a number of test cases. If the design and testing are successful, the restore logic can be optimized for instantiation into an actual integrated circuit.
摘要翻译：设计和测试还原逻辑的方法，用于将功能管理逻辑电路的存储元件恢复为值。在一个实施方式中，所公开的设计方法包括提供逻辑电路的设计，当被实例化时，逻辑电路将具有多个状态，可以在重新启动逻辑电路时将其返回。由存储元件保存的值被确定并用于将存储元件分类成允许开发还原逻辑的类别，恢复逻辑将恢复适合于特定供电的功率管理逻辑电路的状态。恢复逻辑设计通过对硬件描述语言进行建模和功耗管理的逻辑电路进行测试，并通过多个测试用例模拟状态数量。如果设计和测试成功，则可以将恢复逻辑优化为实例化为实际的集成电路。

4. 发明申请

US20090302889A1 INTEGRATED CIRCUIT CONTAINING MULTI-STATE RESTORE CIRCUITRY FOR RESTORING STATE TO A POWER-MANAGED FUNCTIONAL BLOCK 有权
标题翻译：包含多状态恢复电路的集成电路，用于将状态恢复到功率管理的功能块
公开(公告)号：US20090302889A1
公开(公告)日：2009-12-10
申请号：US12135249
申请日：2008-06-09
申请人： Susan K. Lichtensteiger , Michael R. Ouellette , Raymond W. M. Schuppe , Sebastian T. Ventrone
发明人： Susan K. Lichtensteiger , Michael R. Ouellette , Raymond W. M. Schuppe , Sebastian T. Ventrone
IPC分类号： H03K19/0175
CPC分类号： H03K19/0008 , H03K19/173
摘要： Multi-state restore circuitry that allows storage elements of a power-managed functional block to be loaded when the functional block is repowered up so that the functional block is ready for operation virtually immediately after voltage ramp-up of the functional block. The multi-state restore circuitry includes a restore-state detector for determining which one of a plurality of restore states of the functional block is applicable to a particular repowering-up of the functional block. The multi-state restore circuitry also includes restore logic that loads the storage elements as a function of the restore state determined by the restore-state detector.
摘要翻译：多功能恢复电路，允许在功能块被重新加电时加载功率管理功能块的存储元件，使得功能块在功能块的电压升高之后实际上准备好运行。多状态恢复电路包括恢复状态检测器，用于确定功能块的多个恢复状态中的哪一个可应用于功能块的特定重新启动。多状态恢复电路还包括根据由恢复状态检测器确定的恢复状态来加载存储元件的恢复逻辑。

5. 发明授权

US08823491B2 Security-enhanced radio frequency object locator system, method and program storage device 有权
标题翻译：安全增强射频对象定位系统，方法和程序存储设备
公开(公告)号：US08823491B2
公开(公告)日：2014-09-02
申请号：US13348866
申请日：2012-01-12
申请人： Shawn M. Luke , Michael R. Ouellette , Karl V. Swanke , Sebastian T. Ventrone
发明人： Shawn M. Luke , Michael R. Ouellette , Karl V. Swanke , Sebastian T. Ventrone
IPC分类号： G08B5/22 , G08B13/14 , G08B1/08 , G01S13/08 , G01B11/14
CPC分类号： G08B21/24
摘要： Disclosed are an object locator system, a method and a program storage device. In the embodiments, radio frequency identification (RFID) tags are on objects within a defined area and each RFID tag can be activated by an RF activation signal. When a request (e.g., a verbal or keyed-in request) to locate a specific object is received from a specific user, the required permission to locate the object is verified and, optionally, the identity of the specific user is authenticated. Once the required permission is verified and the identity of the specific user is authenticated, one of three RFID readers transmits an RF activation signal. RF response signals received back at the three RFID readers from the specific object's RFID tag are used to triangulate the position of the specific object. Once determined, the position is communicated (e.g., by map display, verbal message, or text message) to the specific user.
摘要翻译：公开了一种对象定位器系统，方法和程序存储装置。在实施例中，射频识别（RFID）标签位于限定区域内的对象上，并且每个RFID标签可由RF激活信号激活。当从特定用户接收到用于定位特定对象的请求（例如，语言或密钥请求）时，验证定位对象的所需许可证，并且可选地，特定用户的身份被认证。一旦验证了所需许可并且认证了特定用户的身份，三个RFID读取器中的一个发送RF激活信号。使用从特定对象的RFID标签在三个RFID读取器处接收的RF响应信号来对特定对象的位置进行三角测量。一旦确定，将位置（例如，通过地图显示，口头消息或文本消息）传达给特定用户。

6. 发明申请

US20130181838A1 SECURITY-ENHANCED RADIO FREQUENCY OBJECT LOCATOR SYSTEM, METHOD AND PROGRAM STORAGE DEVICE 有权
标题翻译：安全增强无线电频率对象定位系统，方法和程序存储设备
公开(公告)号：US20130181838A1
公开(公告)日：2013-07-18
申请号：US13348866
申请日：2012-01-12
申请人： Shawn M. Luke , Michael R. Ouellette , Karl V. Swanke , Sebastian T. Ventrone
发明人： Shawn M. Luke , Michael R. Ouellette , Karl V. Swanke , Sebastian T. Ventrone
IPC分类号： G08B13/14
CPC分类号： G08B21/24
摘要： Disclosed are an object locator system, a method and a program storage device. In the embodiments, radio frequency identification (RFID) tags are on objects within a defined area and each RFID tag can be activated by an RF activation signal. When a request (e.g., a verbal or keyed-in request) to locate a specific object is received from a specific user, the required permission to locate the object is verified and, optionally, the identity of the specific user is authenticated. Once the required permission is verified and the identity of the specific user is authenticated, one of three RFID readers transmits an RF activation signal. RF response signals received back at the three RFID readers from the specific object's RFID tag are used to triangulate the position of the specific object. Once determined, the position is communicated (e.g., by map display, verbal message, or text message) to the specific user.
摘要翻译：公开了一种对象定位器系统，方法和程序存储装置。在实施例中，射频识别（RFID）标签位于限定区域内的对象上，并且每个RFID标签可由RF激活信号激活。当从特定用户接收到用于定位特定对象的请求（例如，语言或密钥请求）时，验证定位对象所需的许可，并且可选地，特定用户的身份被认证。一旦验证了所需许可并且认证了特定用户的身份，三个RFID读取器中的一个发送RF激活信号。使用从特定对象的RFID标签在三个RFID读取器处接收的RF响应信号来对特定对象的位置进行三角测量。一旦确定，将位置（例如，通过地图显示，口头消息或文本消息）传达给特定用户。

7. 发明申请

US20120062300A1 CIRCUIT AND METHOD FOR ASYNCHRONOUS PIPELINE PROCESSING WITH VARIABLE REQUEST SIGNAL DELAY 有权
标题翻译：具有可变请求信号延迟的异步管道加工的电路和方法
公开(公告)号：US20120062300A1
公开(公告)日：2012-03-15
申请号：US12882425
申请日：2010-09-15
申请人： Michael R. Ouellette , Faraydon Pakbaz , Jack R. Smith , Sebastian T. Ventrone
发明人： Michael R. Ouellette , Faraydon Pakbaz , Jack R. Smith , Sebastian T. Ventrone
IPC分类号： H03H11/26
CPC分类号： G06F5/10 , G06F2205/104
摘要： Disclosed are embodiments of an asynchronous pipeline circuit. In each stage of the circuit, a variable delay line is incorporated into the request signal path. A tap encoder monitors data entering the stage to detect any state changes occurring in specific data bits. Based on the results of this monitoring (i.e., based on which of the specific data bits, if any, exhibit state changes), the tap encoder enables a specific tap in the variable delay line and, thereby, automatically adjusts the delay of a request signal transmitted along the request signal path. Using a variable request signal delay allows data from a transmitting stage to be captured by a receiving stage prior to the expiration of the maximum possible processing time associated with the transmitting stage, thereby minimizing overall processing time. Also disclosed are embodiments of methods for asynchronous pipeline processing with variable request signal delay and for incorporating variable request signal delay into an asynchronous pipeline circuit design.
摘要翻译：公开了异步管线电路的实施例。在电路的每个阶段，可变延迟线被并入到请求信号路径中。抽头编码器监视进入阶段的数据，以检测在特定数据位中发生的任何状态变化。基于该监视的结果（即，基于特定数据位中的哪一个，如果有的话，表现出状态改变），则分接编码器在可变延迟线中启用特定抽头，从而自动调整请求的延迟信号沿请求信号路径传输。使用可变请求信号延迟允许在与发送级相关联的最大可能处理时间到期之前由接收级捕获来自发送级的数据，从而最小化整个处理时间。还公开了用于具有可变请求信号延迟的异步流水线处理的方法的实施例，并且将可变请求信号延迟并入到异步管线电路设计中。

8. 发明授权

US08188765B2 Circuit and method for asynchronous pipeline processing with variable request signal delay 有权
标题翻译：具有可变请求信号延迟的异步流水线处理的电路和方法
公开(公告)号：US08188765B2
公开(公告)日：2012-05-29
申请号：US12882425
申请日：2010-09-15
申请人： Michael R. Ouellette , Faraydon Pakbaz , Jack R. Smith , Sebastian T. Ventrone
发明人： Michael R. Ouellette , Faraydon Pakbaz , Jack R. Smith , Sebastian T. Ventrone
IPC分类号： H03K19/00 , H03K19/096 , H03K19/094 , H03K19/20
CPC分类号： G06F5/10 , G06F2205/104
摘要： Disclosed are embodiments of an asynchronous pipeline circuit. In each stage of the circuit, a variable delay line is incorporated into the request signal path. A tap encoder monitors data entering the stage to detect any state changes occurring in specific data bits. Based on the results of this monitoring (i.e., based on which of the specific data bits, if any, exhibit state changes), the tap encoder enables a specific tap in the variable delay line and, thereby, automatically adjusts the delay of a request signal transmitted along the request signal path. Using a variable request signal delay allows data from a transmitting stage to be captured by a receiving stage prior to the expiration of the maximum possible processing time associated with the transmitting stage, thereby minimizing overall processing time. Also disclosed are embodiments of methods for asynchronous pipeline processing with variable request signal delay and for incorporating variable request signal delay into an asynchronous pipeline circuit design.
摘要翻译：公开了异步管线电路的实施例。在电路的每个阶段，可变延迟线被并入到请求信号路径中。抽头编码器监视进入阶段的数据，以检测在特定数据位中发生的任何状态变化。基于该监视的结果（即，基于特定数据位中的哪一个，如果有的话，表现出状态改变），则分接编码器在可变延迟线中启用特定抽头，从而自动调整请求的延迟信号沿请求信号路径传输。使用可变请求信号延迟允许在与发送级相关联的最大可能处理时间到期之前由接收级捕获来自发送级的数据，从而最小化整个处理时间。还公开了用于具有可变请求信号延迟的异步流水线处理的方法的实施例，并且将可变请求信号延迟并入到异步管线电路设计中。

9. 发明申请

US20140040685A1 BUILT-IN-SELF-TEST (BIST) ORGANIZATIONAL FILE GENERATION 有权
标题翻译：内部自检（BIST）组织文件生成
公开(公告)号：US20140040685A1
公开(公告)日：2014-02-06
申请号：US13567127
申请日：2012-08-06
申请人： Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague
发明人： Craig M. Monroe , Michael R. Ouellette , Douglas E. Sprague
IPC分类号： G11C29/12
CPC分类号： G11C29/54 , G11C5/04 , G11C29/12
摘要： Aspects of the invention provide for creating a built-in-self-test (BIST) organizational file for an integrated circuit (IC) chip. In one embodiment, a method includes: receiving a design file including a hierarchy of memory modules, each module including a plurality of memory wrappers; scanning each memory wrapper in each hierarchical level of memory modules for a BIST type; creating, based on the hierarchical level and the BIST type, an ordered list of memory wrappers; adding, based on the BIST type, a BIST engine for each memory wrapper listed in the ordered list; and adding a plurality of references statements to the ordered list to create the BIST organizational file.
摘要翻译：本发明的方面提供了用于为集成电路（IC）芯片创建内置自测（BIST）组织文件。在一个实施例中，一种方法包括：接收包括存储器模块层级的设计文件，每个模块包括多个存储器包装器; 在BIST类型的每个层级的内存模块中扫描每个内存包装器; 基于层次级别和BIST类型创建存储器包装器的有序列表; 根据BIST类型添加一个BIST引擎，用于在有序列表中列出的每个内存包装器; 并将多个引用语句添加到有序列表以创建BIST组织文件。

10. 发明授权

US08467260B2 Structure and method for storing multiple repair pass data into a fusebay 有权
标题翻译：用于将多个修复传递数据存储到保险丝盒中的结构和方法
公开(公告)号：US08467260B2
公开(公告)日：2013-06-18
申请号：US13198894
申请日：2011-08-05
申请人： Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
发明人： Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
IPC分类号： G11C17/16
CPC分类号： G11C17/16 , G11C29/785 , G11C29/802
摘要： Fuse macros of identical number of pages are serially arranged to form the same number of fusebay pages each having a length equal to the sum of the respective fuse macro page lengths. Each fuse macro has an enable latch configured to allow activation of one fuse macro at a time. A fusebay control device connected to a repair register may store data in and retrieve data from the fusebay. Next available fuse location is determined in programming mode so that data from a next repair pass may start where the last data ended.
摘要翻译：相同页数的保险丝宏串联地形成相同数量的保险丝页，每个保险丝页的长度等于相应的熔丝宏页面长度之和。每个保险丝宏都有一个使能锁存器，配置为允许一次激活一个保险丝宏。连接到维修寄存器的保险丝控制装置可以将数据存储在保险丝盒中并从熔丝座检索数据。在编程模式下确定下一个可用的熔丝位置，以便下一个维修通过的数据可以在最后一个数据结束的地方开始。

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