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1. 发明申请

US20140024145A1 METHOD AND STRUCTURE FOR MULTI-CORE CHIP PRODUCT TEST AND SELECTIVE VOLTAGE BINNING DISPOSITION 有权
标题翻译：多核芯片产品测试和选择性电压调整处理方法与结构
公开(公告)号：US20140024145A1
公开(公告)日：2014-01-23
申请号：US13553986
申请日：2012-07-20
申请人： JEANNE P. BICKFORD , Vikram Iyengar , Rahul K. Nadkarni , Pascal A. Nsame
发明人： JEANNE P. BICKFORD , Vikram Iyengar , Rahul K. Nadkarni , Pascal A. Nsame
IPC分类号： H01L21/66 , G01R31/02 , G06F19/00
CPC分类号： G01R31/31718 , G01R31/31725 , G06F1/32
摘要： Operating speeds of integrated circuit devices are tested to establish maximum and minimum frequency at maximum and minimum voltage. The devices are sorted into relatively-slow and relatively-fast devices to classify the devices into different voltage bins. A bin-specific voltage limit is established for each of the voltage bins needed for core performance at system use conditions. The bin-specific voltage limit is compared to core minimum chip-level functionality voltage at system maximum and minimum frequency specifications. The method correlates system design evaluation of design maximum and minimum frequency at design maximum and minimum voltage conditions with evaluation of tested maximum and minimum frequency at tested maximum and minimum voltage conditions. A chip-specific functionality voltage limit is established for the device. Initial system voltage for all devices from a voltage bin is set at a greater of the bin-specific voltage limit and the chip-specific functionality voltage limit consistent with the evaluation conditions.
摘要翻译：测试集成电路器件的工作速度，以在最大和最小电压下建立最大和最小频率。将器件分类为相对较慢且相对较快的器件，以将器件分类到不同的电压仓。对于在系统使用条件下核心性能所需的每个电压箱，建立了一个特定于特定电压限制。特定于箱体的电压限制与系统最大和最小频率规格下的核心最小芯片级功能电压进行比较。该方法在设计最大和最小电压条件下将设计最大和最小频率的系统设计评估与测试的最大和最小电压条件下的最大和最小频率进行了评估。为器件建立芯片专用功能电压限制。来自电压仓的所有器件的初始系统电压设置在特定于器件的电压限制和芯片专用功能电压限制的更大值与评估条件一致。

2. 发明授权

US09557378B2 Method and structure for multi-core chip product test and selective voltage binning disposition 有权
标题翻译：多核芯片产品测试和选择性电压组合配置的方法和结构
公开(公告)号：US09557378B2
公开(公告)日：2017-01-31
申请号：US13553986
申请日：2012-07-20
申请人： Jeanne P. Bickford , Vikram Iyengar , Rahul K. Nadkarni , Pascal A. Nsame
发明人： Jeanne P. Bickford , Vikram Iyengar , Rahul K. Nadkarni , Pascal A. Nsame
IPC分类号： H01L21/66 , G01R31/02 , G06F19/00 , G01R31/317 , G06F1/32
CPC分类号： G01R31/31718 , G01R31/31725 , G06F1/32
摘要： Operating speeds of integrated circuit devices are tested to establish maximum and minimum frequency at maximum and minimum voltage. The devices are sorted into relatively-slow and relatively-fast devices to classify the devices into different voltage bins. A bin-specific voltage limit is established for each of the voltage bins needed for core performance at system use conditions. The bin-specific voltage limit is compared to core minimum chip-level functionality voltage at system maximum and minimum frequency specifications. The method correlates system design evaluation of design maximum and minimum frequency at design maximum and minimum voltage conditions with evaluation of tested maximum and minimum frequency at tested maximum and minimum voltage conditions. A chip-specific functionality voltage limit is established for the device. Initial system voltage for all devices from a voltage bin is set at a greater of the bin-specific voltage limit and the chip-specific functionality voltage limit consistent with the evaluation conditions.
摘要翻译：测试集成电路器件的工作速度，以在最大和最小电压下建立最大和最小频率。将器件分类为相对较慢且相对较快的器件，以将器件分类到不同的电压仓。对于在系统使用条件下核心性能所需的每个电压箱，建立了一个特定于特定电压限制。特定于箱体的电压限制与系统最大和最小频率规格下的核心最小芯片级功能电压进行比较。该方法在设计最大和最小电压条件下将设计最大和最小频率的系统设计评估与测试的最大和最小电压条件下的最大和最小频率进行了评估。为器件建立芯片专用功能电压限制。来自电压仓的所有器件的初始系统电压设置在特定于器件的电压限制和芯片专用功能电压限制的更大值与评估条件一致。

3. 发明授权

US09058034B2 Integrated circuit product yield optimization using the results of performance path testing 有权
标题翻译：集成电路产品产量优化使用性能路径测试的结果
公开(公告)号：US09058034B2
公开(公告)日：2015-06-16
申请号：US13570285
申请日：2012-08-09
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , Jinjun Xiong
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , Jinjun Xiong
IPC分类号： G06F17/50 , G05B19/418
CPC分类号： G05B19/41875 , G05B2219/32182 , G05B2219/32187 , G05B2219/32208 , G05B2219/37224 , Y02P80/30 , Y02P90/22
摘要： Disclosed are embodiments of a method, system and computer program product for optimizing integrated circuit product yield by re-centering the manufacturing line and, optionally, adjusting wafer-level chip dispositioning rules based on the results of post-manufacture (e.g., wafer-level or module-level) performance path testing. In the embodiments, a correlation is made between in-line parameter measurements and performance measurements acquired during the post-manufacture performance path testing. Then, based on this correlation, the manufacturing line can be re-centered. Optionally, an additional correlation is made between performance measurements acquired during wafer-level performance testing and performance measurements acquired particularly during module-level performance path testing and, based on this additional correlation, adjustments can be made to the wafer-level chip dispositioning rules to further minimize yield loss.
摘要翻译：公开了用于通过使生产线重新对中来优化集成电路产品产量的方法，系统和计算机程序产品的实施例，并且可选地，基于后期制造的结果调整晶片级芯片布置规则（例如，晶片级或模块级）性能路径测试。在实施例中，在后续制造性能路径测试期间获得的在线参数测量和性能测量之间进行相关。然后，基于这种相关性，生产线可以重新居中。可选地，在晶片级性能测试期间获得的性能测量和特别在模块级性能路径测试期间获得的性能测量之间进行附加的相关性，并且基于该附加相关性，可以对晶片级芯片布置规则进行调整进一步降低产量损失。

4. 发明授权

US08543966B2 Test path selection and test program generation for performance testing integrated circuit chips 有权
标题翻译：测试路径选择和测试程序生成用于性能测试集成电路芯片
公开(公告)号：US08543966B2
公开(公告)日：2013-09-24
申请号：US13294210
申请日：2011-11-11
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
IPC分类号： G06F11/22 , G06F17/50
CPC分类号： G01R31/31726 , G01R31/318541
摘要： A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths.
摘要翻译：一种用于性能测试集成电路的测试路径选择和测试程序生成的方法。该方法包括识别具有具有多个时钟域的集成电路设计的多个数据路径的时钟域; 从数据路径中选择多个时钟域的每个时钟域的关键路径; 使用计算机，对于多个时钟域的每个时钟域，选择关键路径的可敏化路径; 对于多个时钟域的每个时钟域，从敏感关键路径中选择测试路径; 并使用计算机，创建测试程序来测试测试路径。

5. 发明授权

US08490040B2 Disposition of integrated circuits using performance sort ring oscillator and performance path testing 有权
标题翻译：使用性能分类环形振荡器和性能路径测试对集成电路进行处理
公开(公告)号：US08490040B2
公开(公告)日：2013-07-16
申请号：US13294220
申请日：2011-11-11
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G01R31/3016 , G01R31/31725
摘要： A method and system for dispositioning integrated circuit chips. The method includes performing a performance path test on an integrated circuit chip having one or more clock domains, the performance path test based on applying test patterns to selected sensitizable data paths of the integrated circuit chip at different clock frequencies; and dispositioning the integrated circuit chip based on results of the performance path test.
摘要翻译：一种配置集成电路芯片的方法和系统。该方法包括对具有一个或多个时钟域的集成电路芯片执行性能路径测试，该性能路径测试基于将测试图案应用于集成电路芯片的不同时钟频率的选择的可敏化数据路径; 并且基于性能路径测试的结果来布置集成电路芯片。

6. 发明申请

US20130125073A1 TEST PATH SELECTION AND TEST PROGRAM GENERATION FOR PERFORMANCE TESTING INTEGRATED CIRCUIT CHIPS 有权
标题翻译：性能测试集成电路卡的测试路径选择和测试程序生成
公开(公告)号：US20130125073A1
公开(公告)日：2013-05-16
申请号：US13294210
申请日：2011-11-11
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
IPC分类号： G06F17/50
CPC分类号： G01R31/31726 , G01R31/318541
摘要： A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths
摘要翻译：一种用于性能测试集成电路的测试路径选择和测试程序生成的方法。该方法包括识别具有具有多个时钟域的集成电路设计的多个数据路径的时钟域; 从数据路径中选择多个时钟域的每个时钟域的关键路径; 使用计算机，对于多个时钟域的每个时钟域，选择关键路径的可敏化路径; 对于多个时钟域的每个时钟域，从敏感关键路径中选择测试路径; 并使用计算机，创建测试程序来测试测试路径

7. 发明申请

US20130125076A1 DISPOSITION OF INTEGRATED CIRCUITS USING PERFORMANCE SORT RING OSCILLATOR AND PERFORMANCE PATH TESTING 有权
标题翻译：使用性能排序振荡器和性能路径测试处理集成电路
公开(公告)号：US20130125076A1
公开(公告)日：2013-05-16
申请号：US13294220
申请日：2011-11-11
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
IPC分类号： G06F17/50
CPC分类号： G01R31/3016 , G01R31/31725
摘要： A method and system for dispositioning integrated circuit chips. The method includes performing a performance path test on an integrated circuit chip having one or more clock domains, the performance path test based on applying test patterns to selected sensitizable data paths of the integrated circuit chip at different clock frequencies; and dispositioning the integrated circuit chip based on results of the performance path test.
摘要翻译：一种配置集成电路芯片的方法和系统。该方法包括对具有一个或多个时钟域的集成电路芯片执行性能路径测试，该性能路径测试基于将测试图案应用于集成电路芯片的不同时钟频率的选择的可敏化数据路径; 并且基于性能路径测试的结果来布置集成电路芯片。

8. 发明申请

US20140046466A1 INTEGRATED CIRCUIT PRODUCT YIELD OPTIMIZATION USING THE RESULTS OF PERFORMANCE PATH TESTING 有权
标题翻译：使用性能路径测试结果的集成电路产品线优化
公开(公告)号：US20140046466A1
公开(公告)日：2014-02-13
申请号：US13570285
申请日：2012-08-09
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , Jinjun Xiong
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , Jinjun Xiong
IPC分类号： G05B19/18
CPC分类号： G05B19/41875 , G05B2219/32182 , G05B2219/32187 , G05B2219/32208 , G05B2219/37224 , Y02P80/30 , Y02P90/22
摘要： Disclosed are embodiments of a method, system and computer program product for optimizing integrated circuit product yield by re-centering the manufacturing line and, optionally, adjusting wafer-level chip dispositioning rules based on the results of post-manufacture (e.g., wafer-level or module-level) performance path testing. In the embodiments, a correlation is made between in-line parameter measurements and performance measurements acquired during the post-manufacture performance path testing. Then, based on this correlation, the manufacturing line can be re-centered. Optionally, an additional correlation is made between performance measurements acquired during wafer-level performance testing and performance measurements acquired particularly during module-level performance path testing and, based on this additional correlation, adjustments can be made to the wafer-level chip dispositioning rules to further minimize yield loss.
摘要翻译：公开了用于通过使生产线重新对中来优化集成电路产品产量的方法，系统和计算机程序产品的实施例，并且可选地，基于后期制造的结果调整晶片级芯片布置规则（例如，晶片级或模块级）性能路径测试。在实施例中，在后续制造性能路径测试期间获得的在线参数测量和性能测量之间进行相关。然后，基于这种相关性，生产线可以重新居中。可选地，在晶片级性能测试期间获得的性能测量和特别在模块级性能路径测试期间获得的性能测量之间进行附加的相关性，并且基于该附加相关性，可以对晶片级芯片布置规则进行调整进一步降低产量损失。

9. 发明授权

US08539429B1 System yield optimization using the results of integrated circuit chip performance path testing 有权
标题翻译：系统产量优化采用集成电路芯片性能路径测试的结果
公开(公告)号：US08539429B1
公开(公告)日：2013-09-17
申请号：US13572954
申请日：2012-08-13
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar
IPC分类号： G06F17/50
CPC分类号： G01R31/31718 , G01R31/31725
摘要： Disclosed are embodiments of a method, system and computer program for optimizing system yield based on the results of post-manufacture integrated circuit (IC) chip performance path testing. In these embodiments, a correlation is made between IC chip performance measurements, which were acquired from IC chips specifically during post-manufacture (i.e., wafer-level or module-level) performance path testing, and system performance measurements, which were acquired from systems that incorporate those IC chips previously subjected to performance path testing. Based on this correlation and a target system performance value, a post-manufacture (i.e., wafer-level or module-level) chip dispositioning rule can be adjusted to optimize system yield (i.e., to ensure that subsequently manufactured systems which incorporate the IC chip meet the target system performance value). Optionally, simulation of such processing can be performed during design of the IC chip for incorporation into the system in order establish the initial chip dispositioning rule in the first place.
摘要翻译：公开了一种基于后制造集成电路（IC）芯片性能路径测试的结果来优化系统产量的方法，系统和计算机程序的实施例。在这些实施例中，在IC芯片特性在后期制造（即晶片级或模块级）性能路径测试中获得的IC芯片性能测量和从系统获取的系统性能测量之间进行相关其中包含先前经过性能路径测试的那些IC芯片。基于这种相关性和目标系统性能值，可以调整后制造（即晶片级或模块级）芯片布置规则以优化系统产量（即，确保随后制造的并入IC芯片的系统满足目标系统的性能价值）。可选地，可以在用于结合到系统中的IC芯片的设计期间执行这种处理的模拟，以便首先建立初始的芯片布置规则。

10. 发明授权

US08230283B2 Method to test hold path faults using functional clocking 失效
标题翻译：使用功能时钟测试保持路径故障的方法
公开(公告)号：US08230283B2
公开(公告)日：2012-07-24
申请号：US12641456
申请日：2009-12-18
申请人： Pamela S. Gillis , Vikram Iyengar , Steven F. Oakland
发明人： Pamela S. Gillis , Vikram Iyengar , Steven F. Oakland
IPC分类号： G01R31/28
CPC分类号： G01R31/31858 , G01R31/31725
摘要： A system and method for detecting hold path faults in an integrated circuit is provided in exemplary embodiments. These exemplary embodiments introduce a method of identifying data paths within an integrated circuit with statistically the highest timing slack among the data paths within the integrated circuit that cover the entire process space of the circuit. By identifying these paths (i.e., shortest data paths), a robust test pattern can be generated that directly tests for hold path faults on short data paths within the integrated circuit using one functional clock pulse.
摘要翻译：在示例性实施例中提供了用于检测集成电路中的保持路径故障的系统和方法。这些示例性实施例引入了一种识别集成电路内的数据路径的方法，统计上覆盖电路的整个处理空间的集成电路内的数据路径中的最高定时松弛。通过识别这些路径（即，最短数据路径），可以生成鲁棒的测试模式，其使用一个功能时钟脉冲直接测试集成电路内的短数据路径上的保持路径故障。

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