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1. 发明申请

US20140024145A1 METHOD AND STRUCTURE FOR MULTI-CORE CHIP PRODUCT TEST AND SELECTIVE VOLTAGE BINNING DISPOSITION 有权
标题翻译：多核芯片产品测试和选择性电压调整处理方法与结构
公开(公告)号：US20140024145A1
公开(公告)日：2014-01-23
申请号：US13553986
申请日：2012-07-20
申请人： JEANNE P. BICKFORD , Vikram Iyengar , Rahul K. Nadkarni , Pascal A. Nsame
发明人： JEANNE P. BICKFORD , Vikram Iyengar , Rahul K. Nadkarni , Pascal A. Nsame
IPC分类号： H01L21/66 , G01R31/02 , G06F19/00
CPC分类号： G01R31/31718 , G01R31/31725 , G06F1/32
摘要： Operating speeds of integrated circuit devices are tested to establish maximum and minimum frequency at maximum and minimum voltage. The devices are sorted into relatively-slow and relatively-fast devices to classify the devices into different voltage bins. A bin-specific voltage limit is established for each of the voltage bins needed for core performance at system use conditions. The bin-specific voltage limit is compared to core minimum chip-level functionality voltage at system maximum and minimum frequency specifications. The method correlates system design evaluation of design maximum and minimum frequency at design maximum and minimum voltage conditions with evaluation of tested maximum and minimum frequency at tested maximum and minimum voltage conditions. A chip-specific functionality voltage limit is established for the device. Initial system voltage for all devices from a voltage bin is set at a greater of the bin-specific voltage limit and the chip-specific functionality voltage limit consistent with the evaluation conditions.
摘要翻译：测试集成电路器件的工作速度，以在最大和最小电压下建立最大和最小频率。将器件分类为相对较慢且相对较快的器件，以将器件分类到不同的电压仓。对于在系统使用条件下核心性能所需的每个电压箱，建立了一个特定于特定电压限制。特定于箱体的电压限制与系统最大和最小频率规格下的核心最小芯片级功能电压进行比较。该方法在设计最大和最小电压条件下将设计最大和最小频率的系统设计评估与测试的最大和最小电压条件下的最大和最小频率进行了评估。为器件建立芯片专用功能电压限制。来自电压仓的所有器件的初始系统电压设置在特定于器件的电压限制和芯片专用功能电压限制的更大值与评估条件一致。

2. 发明授权

US09557378B2 Method and structure for multi-core chip product test and selective voltage binning disposition 有权
标题翻译：多核芯片产品测试和选择性电压组合配置的方法和结构
公开(公告)号：US09557378B2
公开(公告)日：2017-01-31
申请号：US13553986
申请日：2012-07-20
申请人： Jeanne P. Bickford , Vikram Iyengar , Rahul K. Nadkarni , Pascal A. Nsame
发明人： Jeanne P. Bickford , Vikram Iyengar , Rahul K. Nadkarni , Pascal A. Nsame
IPC分类号： H01L21/66 , G01R31/02 , G06F19/00 , G01R31/317 , G06F1/32
CPC分类号： G01R31/31718 , G01R31/31725 , G06F1/32
摘要： Operating speeds of integrated circuit devices are tested to establish maximum and minimum frequency at maximum and minimum voltage. The devices are sorted into relatively-slow and relatively-fast devices to classify the devices into different voltage bins. A bin-specific voltage limit is established for each of the voltage bins needed for core performance at system use conditions. The bin-specific voltage limit is compared to core minimum chip-level functionality voltage at system maximum and minimum frequency specifications. The method correlates system design evaluation of design maximum and minimum frequency at design maximum and minimum voltage conditions with evaluation of tested maximum and minimum frequency at tested maximum and minimum voltage conditions. A chip-specific functionality voltage limit is established for the device. Initial system voltage for all devices from a voltage bin is set at a greater of the bin-specific voltage limit and the chip-specific functionality voltage limit consistent with the evaluation conditions.
摘要翻译：测试集成电路器件的工作速度，以在最大和最小电压下建立最大和最小频率。将器件分类为相对较慢且相对较快的器件，以将器件分类到不同的电压仓。对于在系统使用条件下核心性能所需的每个电压箱，建立了一个特定于特定电压限制。特定于箱体的电压限制与系统最大和最小频率规格下的核心最小芯片级功能电压进行比较。该方法在设计最大和最小电压条件下将设计最大和最小频率的系统设计评估与测试的最大和最小电压条件下的最大和最小频率进行了评估。为器件建立芯片专用功能电压限制。来自电压仓的所有器件的初始系统电压设置在特定于器件的电压限制和芯片专用功能电压限制的更大值与评估条件一致。

3. 发明授权

US06430072B1 Embedded CAM test structure for fully testing all matchlines 有权
标题翻译：嵌入式CAM测试结构，可全面测试所有匹配线
公开(公告)号：US06430072B1
公开(公告)日：2002-08-06
申请号：US09682638
申请日：2001-10-01
申请人： Thomas B. Chadwick , Rahul K. Nadkarni , Michael R. Ouellette , Jeremy P. Rowland
发明人： Thomas B. Chadwick , Rahul K. Nadkarni , Michael R. Ouellette , Jeremy P. Rowland
IPC分类号： G11C1500
CPC分类号： G11C29/02 , G11C15/00
摘要： A method and structure for content addressable memory structure having a memory array of words, each word having multiple memory bits and a plurality of matchlines. Each of the matchlines is connected to one of the words and a matchline compare circuit is connected to the matchlines and is adapted to test all of the words individually. The matchline compare circuit includes a plurality of comparators equal in number to a number of the words, such that each word is connected to a dedicated comparator to allow each word in the memory array to be individually tested.
摘要翻译：一种用于内容可寻址存储器结构的方法和结构，其具有字的存储器阵列，每个字具有多个存储器位和多个匹配线。每个匹配线连接到一个字，并且匹配线比较电路连接到匹配线，并且适于单独测试所有单词。匹配线比较电路包括多个比较器，其数量与字数相等，使得每个字连接到专用比较器以允许单独测试存储器阵列中的每个字。

4. 发明授权

US07924588B2 Content addressable memory with concurrent two-dimensional search capability in both row and column directions 有权
标题翻译：内容可寻址存储器，具有行和列方向的并行二维搜索功能
公开(公告)号：US07924588B2
公开(公告)日：2011-04-12
申请号：US11949065
申请日：2007-12-03
申请人： Igor Arsovski , Michael T. Fragano , Rahul K. Nadkarni , Reid A. Wistort
发明人： Igor Arsovski , Michael T. Fragano , Rahul K. Nadkarni , Reid A. Wistort
IPC分类号： G11C15/04
CPC分类号： G11C15/04
摘要： A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.
摘要翻译：内容可寻址存储器（CAM）设备包括以行和列布置的存储器单元阵列; 比较电路，被配置为指示呈现给阵列的每一行的搜索数据的匹配结果; 并且比较被配置为指示呈现给阵列的每列的搜索数据的匹配结果的电路，由此导致阵列的二维搜索能力。

5. 发明申请

US20080080223A1 CAM Asynchronous Search-Line Switching 失效
标题翻译： CAM异步搜索线路切换
公开(公告)号：US20080080223A1
公开(公告)日：2008-04-03
申请号：US11532233
申请日：2006-09-15
申请人： Igor Arsovski , Rahul K. Nadkarni , Reid A. Wistort
发明人： Igor Arsovski , Rahul K. Nadkarni , Reid A. Wistort
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C7/02
摘要： This patent describes a method for switching search-lines in a Content Addressable Memory (CAM) asynchronously to improve CAM speed and reduce CAM noise without affecting its power performance. This is accomplished by resetting the match-lines prior to initiating a search and then applying a search word to the search-lines. A reference match-line is provided to generate the timing for the search operation and provide the timing for the asynchronous application of the search data on the SLs. Additional noise reduction is achieved through the staggering of the search data application on the SLs through programmable delay elements
摘要翻译：该专利描述了用于在内容寻址存储器（CAM）中异步地切换搜索线以提高CAM速度并降低CAM噪声而不影响其功率性能的方法。这通过在发起搜索之前重置匹配线，然后将搜索词应用于搜索线来实现。提供参考匹配线以产生用于搜索操作的定时，并为SL上的搜索数据的异步应用提供定时。通过可编程延迟元件在SL上搜索数据应用的交错来实现额外的降噪

6. 发明授权

US06597596B2 Content addressable memory having cascaded sub-entry architecture 有权
公开(公告)号：US06597596B2
公开(公告)日：2003-07-22
申请号：US10286206
申请日：2002-11-01
申请人： Tarl S. Gordon , Rahul K. Nadkarni
发明人： Tarl S. Gordon , Rahul K. Nadkarni
IPC分类号： G11C1500
CPC分类号： G11C15/00
摘要： A growable CAM array and an ASIC-compatible CAM architecture based on modular cascadable CAM blocks, each CAM block containing a sub-entry including a segment of the match line of a CAM entry, each block's output being its match-line segment's voltage gated by a combinatorial logic gate. Each sub-entry's structure is that of a short CAM entry with a short Match Line (a match line segment) with a small capacitance. Each CAM block outputs a signal that can enable or inhibit a CAM search in the sub-entry in the next CAM block. A variety of exemplary circuits for gating match line segments within CAM blocks, and methods of selecting and combining the resulting variety of CAM blocks to obtain power-savings and/or high performance. An ASIC library including library elements having electrical rules that describe devices within and describe interconnections between the devices within a CAM block.

7. 发明申请

US20110096582A1 CONTENT ADDRESSABLE MEMORY WITH CONCURRENT TWO-DIMENSIONAL SEARCH CAPABILITY IN BOTH ROW AND COLUMN DIRECTIONS 有权
标题翻译：内容可寻址的存储器，具有两个二维搜索能力，在两个方向和列方向
公开(公告)号：US20110096582A1
公开(公告)日：2011-04-28
申请号：US12983995
申请日：2011-01-04
申请人： Igor Arsovski , Michael T. Fragano , Rahul K. Nadkarni , Reid A. Wistort
发明人： Igor Arsovski , Michael T. Fragano , Rahul K. Nadkarni , Reid A. Wistort
IPC分类号： G11C15/04 , G11C15/00
CPC分类号： G11C15/04
摘要： A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.
摘要翻译：内容可寻址存储器（CAM）设备包括以行和列布置的存储器单元阵列; 比较电路，被配置为指示呈现给阵列的每一行的搜索数据的匹配结果; 并且比较被配置为指示呈现给阵列的每列的搜索数据的匹配结果的电路，由此导致阵列的二维搜索能力。

8. 发明申请

US20090147590A1 APPARATUS FOR REDUCING LEAKAGE IN GLOBAL BIT-LINE ARCHITECTURES 失效
标题翻译：降低全球排列结构泄漏的装置
公开(公告)号：US20090147590A1
公开(公告)日：2009-06-11
申请号：US11950459
申请日：2007-12-05
申请人： Anthony Correale, JR. , Rahul K. Nadkarni
发明人： Anthony Correale, JR. , Rahul K. Nadkarni
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/1051 , G11C7/1069 , G11C7/18
摘要： A circuit for reducing current leakage in hierarchical bit-line architectures includes a sense amplifier having transistors, the sense amplifier coupled to bit-lines of cells in a memory array, the sense amplifier configured for detecting stored data from one of the cells; an output latch having transistors, the output latch selectively coupled to a global bit-line of the sense amplifier having a logical state, the output latch configured for selectively reading out stored data from one of the cells through the global bit-line; and a transmission gating device coupled between the sense amplifier and the output latch for selectively coupling the sense amplifier to the output latch correspondingly eliminating a first leakage path and forming a second leakage path, the first leakage path being between the sense amplifier and the output latch, the second leakage path formed within the sense amplifier.
摘要翻译：用于降低分级位线架构中的电流泄漏的电路包括具有晶体管的读出放大器，读出放大器耦合到存储器阵列中的单元的位线，该读出放大器配置用于检测来自其中一个单元的存储数据; 具有晶体管的输出锁存器，所述输出锁存器选择性地耦合到具有逻辑状态的所述读出放大器的全局位线，所述输出锁存器被配置为经由所述全局位线选择性地从所述单元之一读出存储的数据; 以及耦合在所述读出放大器和所述输出锁存器之间的传输选通装置，用于选择性地将所述读出放大器耦合到所述输出锁存器，以相应地消除第一泄漏路径并形成第二泄漏路径，所述第一泄漏路径位于所述读出放大器和所述输出锁存器，形成在读出放大器内的第二泄漏路径。

9. 发明申请

US20090141530A1 STRUCTURE FOR IMPLEMENTING ENHANCED CONTENT ADDRESSABLE MEMORY PERFORMANCE CAPABILITY 审中-公开
标题翻译：实现增强内容可寻址记忆性能能力的结构
公开(公告)号：US20090141530A1
公开(公告)日：2009-06-04
申请号：US12110582
申请日：2008-04-28
申请人： Igor Arsovski , Michael T. Fragano , Rahul K. Nadkarni , Reid A. Wisort
发明人： Igor Arsovski , Michael T. Fragano , Rahul K. Nadkarni , Reid A. Wisort
IPC分类号： G11C15/04
CPC分类号： G11C15/04
摘要： A design structure embodied in a machine readable medium used in a design process includes a content addressable memory (CAM) device having an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括具有以行和列排列的存储单元阵列的内容寻址存储器（CAM）设备; 比较电路，被配置为指示呈现给阵列的每一行的搜索数据的匹配结果; 并且比较被配置为指示呈现给阵列的每列的搜索数据的匹配结果的电路，由此导致阵列的二维搜索能力。

10. 发明申请

US20090141528A1 APPARATUS AND METHOD FOR IMPLEMENTING ENHANCED CONTENT ADDRESSABLE MEMORY PERFORMANCE CAPABILITY 有权
标题翻译：实现增强内容可寻址记忆性能能力的装置和方法
公开(公告)号：US20090141528A1
公开(公告)日：2009-06-04
申请号：US11949065
申请日：2007-12-03
申请人： Igor Arsovski , Michael T. Fragano , Rahul K. Nadkarni , Reid A. Wistort
发明人： Igor Arsovski , Michael T. Fragano , Rahul K. Nadkarni , Reid A. Wistort
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： A content addressable memory (CAM) device includes an array of memory cells arranged in rows and columns; compare circuitry configured to indicate match results of search data presented to each row of the array; and compare circuitry configured to indicate match results of search data presented to each column of the array, thereby resulting in a two-dimensional search capability of the array.
摘要翻译：内容可寻址存储器（CAM）设备包括以行和列布置的存储器单元阵列; 比较电路，被配置为指示呈现给阵列的每一行的搜索数据的匹配结果; 并且比较被配置为指示呈现给阵列的每列的搜索数据的匹配结果的电路，由此导致阵列的二维搜索能力。

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