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    • 3. 发明授权
    • System yield optimization using the results of integrated circuit chip performance path testing
    • 系统产量优化采用集成电路芯片性能路径测试的结果
    • US08539429B1
    • 2013-09-17
    • US13572954
    • 2012-08-13
    • Jeanne P. BickfordPeter A. HabitzVikram Iyengar
    • Jeanne P. BickfordPeter A. HabitzVikram Iyengar
    • G06F17/50
    • G01R31/31718G01R31/31725
    • Disclosed are embodiments of a method, system and computer program for optimizing system yield based on the results of post-manufacture integrated circuit (IC) chip performance path testing. In these embodiments, a correlation is made between IC chip performance measurements, which were acquired from IC chips specifically during post-manufacture (i.e., wafer-level or module-level) performance path testing, and system performance measurements, which were acquired from systems that incorporate those IC chips previously subjected to performance path testing. Based on this correlation and a target system performance value, a post-manufacture (i.e., wafer-level or module-level) chip dispositioning rule can be adjusted to optimize system yield (i.e., to ensure that subsequently manufactured systems which incorporate the IC chip meet the target system performance value). Optionally, simulation of such processing can be performed during design of the IC chip for incorporation into the system in order establish the initial chip dispositioning rule in the first place.
    • 公开了一种基于后制造集成电路(IC)芯片性能路径测试的结果来优化系统产量的方法,系统和计算机程序的实施例。 在这些实施例中,在IC芯片特性在后期制造(即晶片级或模块级)性能路径测试中获得的IC芯片性能测量和从系统获取的系统性能测量之间进行相关 其中包含先前经过性能路径测试的那些IC芯片。 基于这种相关性和目标系统性能值,可以调整后制造(即晶片级或模块级)芯片布置规则以优化系统产量(即,确保随后制造的并入IC芯片的系统 满足目标系统的性能价值)。 可选地,可以在用于结合到系统中的IC芯片的设计期间执行这种处理的模拟,以便首先建立初始的芯片布置规则。