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1. 发明申请

US20130125076A1 DISPOSITION OF INTEGRATED CIRCUITS USING PERFORMANCE SORT RING OSCILLATOR AND PERFORMANCE PATH TESTING 有权
标题翻译：使用性能排序振荡器和性能路径测试处理集成电路
公开(公告)号：US20130125076A1
公开(公告)日：2013-05-16
申请号：US13294220
申请日：2011-11-11
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
IPC分类号： G06F17/50
CPC分类号： G01R31/3016 , G01R31/31725
摘要： A method and system for dispositioning integrated circuit chips. The method includes performing a performance path test on an integrated circuit chip having one or more clock domains, the performance path test based on applying test patterns to selected sensitizable data paths of the integrated circuit chip at different clock frequencies; and dispositioning the integrated circuit chip based on results of the performance path test.
摘要翻译：一种配置集成电路芯片的方法和系统。该方法包括对具有一个或多个时钟域的集成电路芯片执行性能路径测试，该性能路径测试基于将测试图案应用于集成电路芯片的不同时钟频率的选择的可敏化数据路径; 并且基于性能路径测试的结果来布置集成电路芯片。

2. 发明授权

US08543966B2 Test path selection and test program generation for performance testing integrated circuit chips 有权
标题翻译：测试路径选择和测试程序生成用于性能测试集成电路芯片
公开(公告)号：US08543966B2
公开(公告)日：2013-09-24
申请号：US13294210
申请日：2011-11-11
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
IPC分类号： G06F11/22 , G06F17/50
CPC分类号： G01R31/31726 , G01R31/318541
摘要： A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths.
摘要翻译：一种用于性能测试集成电路的测试路径选择和测试程序生成的方法。该方法包括识别具有具有多个时钟域的集成电路设计的多个数据路径的时钟域; 从数据路径中选择多个时钟域的每个时钟域的关键路径; 使用计算机，对于多个时钟域的每个时钟域，选择关键路径的可敏化路径; 对于多个时钟域的每个时钟域，从敏感关键路径中选择测试路径; 并使用计算机，创建测试程序来测试测试路径。

3. 发明授权

US08490040B2 Disposition of integrated circuits using performance sort ring oscillator and performance path testing 有权
标题翻译：使用性能分类环形振荡器和性能路径测试对集成电路进行处理
公开(公告)号：US08490040B2
公开(公告)日：2013-07-16
申请号：US13294220
申请日：2011-11-11
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G01R31/3016 , G01R31/31725
摘要： A method and system for dispositioning integrated circuit chips. The method includes performing a performance path test on an integrated circuit chip having one or more clock domains, the performance path test based on applying test patterns to selected sensitizable data paths of the integrated circuit chip at different clock frequencies; and dispositioning the integrated circuit chip based on results of the performance path test.
摘要翻译：一种配置集成电路芯片的方法和系统。该方法包括对具有一个或多个时钟域的集成电路芯片执行性能路径测试，该性能路径测试基于将测试图案应用于集成电路芯片的不同时钟频率的选择的可敏化数据路径; 并且基于性能路径测试的结果来布置集成电路芯片。

4. 发明申请

US20130125073A1 TEST PATH SELECTION AND TEST PROGRAM GENERATION FOR PERFORMANCE TESTING INTEGRATED CIRCUIT CHIPS 有权
标题翻译：性能测试集成电路卡的测试路径选择和测试程序生成
公开(公告)号：US20130125073A1
公开(公告)日：2013-05-16
申请号：US13294210
申请日：2011-11-11
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
IPC分类号： G06F17/50
CPC分类号： G01R31/31726 , G01R31/318541
摘要： A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths
摘要翻译：一种用于性能测试集成电路的测试路径选择和测试程序生成的方法。该方法包括识别具有具有多个时钟域的集成电路设计的多个数据路径的时钟域; 从数据路径中选择多个时钟域的每个时钟域的关键路径; 使用计算机，对于多个时钟域的每个时钟域，选择关键路径的可敏化路径; 对于多个时钟域的每个时钟域，从敏感关键路径中选择测试路径; 并使用计算机，创建测试程序来测试测试路径

5. 发明授权

US09058034B2 Integrated circuit product yield optimization using the results of performance path testing 有权
标题翻译：集成电路产品产量优化使用性能路径测试的结果
公开(公告)号：US09058034B2
公开(公告)日：2015-06-16
申请号：US13570285
申请日：2012-08-09
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , Jinjun Xiong
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , Jinjun Xiong
IPC分类号： G06F17/50 , G05B19/418
CPC分类号： G05B19/41875 , G05B2219/32182 , G05B2219/32187 , G05B2219/32208 , G05B2219/37224 , Y02P80/30 , Y02P90/22
摘要： Disclosed are embodiments of a method, system and computer program product for optimizing integrated circuit product yield by re-centering the manufacturing line and, optionally, adjusting wafer-level chip dispositioning rules based on the results of post-manufacture (e.g., wafer-level or module-level) performance path testing. In the embodiments, a correlation is made between in-line parameter measurements and performance measurements acquired during the post-manufacture performance path testing. Then, based on this correlation, the manufacturing line can be re-centered. Optionally, an additional correlation is made between performance measurements acquired during wafer-level performance testing and performance measurements acquired particularly during module-level performance path testing and, based on this additional correlation, adjustments can be made to the wafer-level chip dispositioning rules to further minimize yield loss.
摘要翻译：公开了用于通过使生产线重新对中来优化集成电路产品产量的方法，系统和计算机程序产品的实施例，并且可选地，基于后期制造的结果调整晶片级芯片布置规则（例如，晶片级或模块级）性能路径测试。在实施例中，在后续制造性能路径测试期间获得的在线参数测量和性能测量之间进行相关。然后，基于这种相关性，生产线可以重新居中。可选地，在晶片级性能测试期间获得的性能测量和特别在模块级性能路径测试期间获得的性能测量之间进行附加的相关性，并且基于该附加相关性，可以对晶片级芯片布置规则进行调整进一步降低产量损失。

6. 发明申请

US20140046466A1 INTEGRATED CIRCUIT PRODUCT YIELD OPTIMIZATION USING THE RESULTS OF PERFORMANCE PATH TESTING 有权
标题翻译：使用性能路径测试结果的集成电路产品线优化
公开(公告)号：US20140046466A1
公开(公告)日：2014-02-13
申请号：US13570285
申请日：2012-08-09
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , Jinjun Xiong
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , Jinjun Xiong
IPC分类号： G05B19/18
CPC分类号： G05B19/41875 , G05B2219/32182 , G05B2219/32187 , G05B2219/32208 , G05B2219/37224 , Y02P80/30 , Y02P90/22
摘要： Disclosed are embodiments of a method, system and computer program product for optimizing integrated circuit product yield by re-centering the manufacturing line and, optionally, adjusting wafer-level chip dispositioning rules based on the results of post-manufacture (e.g., wafer-level or module-level) performance path testing. In the embodiments, a correlation is made between in-line parameter measurements and performance measurements acquired during the post-manufacture performance path testing. Then, based on this correlation, the manufacturing line can be re-centered. Optionally, an additional correlation is made between performance measurements acquired during wafer-level performance testing and performance measurements acquired particularly during module-level performance path testing and, based on this additional correlation, adjustments can be made to the wafer-level chip dispositioning rules to further minimize yield loss.
摘要翻译：公开了用于通过使生产线重新对中来优化集成电路产品产量的方法，系统和计算机程序产品的实施例，并且可选地，基于后期制造的结果调整晶片级芯片布置规则（例如，晶片级或模块级）性能路径测试。在实施例中，在后续制造性能路径测试期间获得的在线参数测量和性能测量之间进行相关。然后，基于这种相关性，生产线可以重新居中。可选地，在晶片级性能测试期间获得的性能测量和特别在模块级性能路径测试期间获得的性能测量之间进行附加的相关性，并且基于该附加相关性，可以对晶片级芯片布置规则进行调整进一步降低产量损失。

7. 发明申请

US20080270953A1 IC CHIP AT-FUNCTIONAL-SPEED TESTING WITH PROCESS COVERAGE EVALUATION 有权
标题翻译： IC芯片功能快速测试与过程覆盖评估
公开(公告)号：US20080270953A1
公开(公告)日：2008-10-30
申请号：US11741164
申请日：2007-04-27
申请人： Eric A. Foreman , Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Eric A. Foreman , Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/10
摘要： Methods, systems and program products for evaluating an IC chip are disclosed. In one embodiment, the method includes running a statistical static timing analysis (SSTA) of a full IC chip design; creating at-functional-speed test (AFST) robust paths for an IC chip, the created robust paths representing a non-comprehensive list of AFST robust paths for the IC chip; and re-running the SSTA with the SSTA delay model setup based on the created robust paths. A process coverage is calculated for evaluation from the SSTA runnings; and a particular IC chip is evaluated based on the process coverage.
摘要翻译：公开了用于评估IC芯片的方法，系统和程序产品。在一个实施例中，该方法包括运行全IC芯片设计的统计静态时序分析（SSTA）; 创建用于IC芯片的功能速度测试（AFST）鲁棒路径，所创建的鲁棒路径表示IC芯片的AFST鲁棒路径的非全面列表; 并基于创建的鲁棒路径，使用SSTA延迟模型设置重新运行SSTA。计算过程覆盖率用于从SSTA运行中进行评估; 并且基于处理覆盖来评估特定的IC芯片。

8. 发明授权

US07620921B2 IC chip at-functional-speed testing with process coverage evaluation 有权
标题翻译： IC芯片在功能速度测试与过程覆盖评估
公开(公告)号：US07620921B2
公开(公告)日：2009-11-17
申请号：US11741164
申请日：2007-04-27
申请人： Eric A. Foreman , Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Eric A. Foreman , Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/10
摘要： Methods, systems and program products for evaluating an IC chip are disclosed. In one embodiment, the method includes running a statistical static timing analysis (SSTA) of a full IC chip design; creating at-functional-speed test (AFST) robust paths for an IC chip, the created robust paths representing a non-comprehensive list of AFST robust paths for the IC chip; and re-running the SSTA with the SSTA delay model setup based on the created robust paths. A process coverage is calculated for evaluation from the SSTA runnings; and a particular IC chip is evaluated based on the process coverage.
摘要翻译：公开了用于评估IC芯片的方法，系统和程序产品。在一个实施例中，该方法包括运行全IC芯片设计的统计静态时序分析（SSTA）; 创建用于IC芯片的功能速度测试（AFST）鲁棒路径，所创建的鲁棒路径表示IC芯片的AFST鲁棒路径的非全面列表; 并基于创建的鲁棒路径，使用SSTA延迟模型设置重新运行SSTA。计算过程覆盖率用于从SSTA运行中进行评估; 并且基于处理覆盖来评估特定的IC芯片。

9. 发明授权

US08539429B1 System yield optimization using the results of integrated circuit chip performance path testing 有权
标题翻译：系统产量优化采用集成电路芯片性能路径测试的结果
公开(公告)号：US08539429B1
公开(公告)日：2013-09-17
申请号：US13572954
申请日：2012-08-13
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar
IPC分类号： G06F17/50
CPC分类号： G01R31/31718 , G01R31/31725
摘要： Disclosed are embodiments of a method, system and computer program for optimizing system yield based on the results of post-manufacture integrated circuit (IC) chip performance path testing. In these embodiments, a correlation is made between IC chip performance measurements, which were acquired from IC chips specifically during post-manufacture (i.e., wafer-level or module-level) performance path testing, and system performance measurements, which were acquired from systems that incorporate those IC chips previously subjected to performance path testing. Based on this correlation and a target system performance value, a post-manufacture (i.e., wafer-level or module-level) chip dispositioning rule can be adjusted to optimize system yield (i.e., to ensure that subsequently manufactured systems which incorporate the IC chip meet the target system performance value). Optionally, simulation of such processing can be performed during design of the IC chip for incorporation into the system in order establish the initial chip dispositioning rule in the first place.
摘要翻译：公开了一种基于后制造集成电路（IC）芯片性能路径测试的结果来优化系统产量的方法，系统和计算机程序的实施例。在这些实施例中，在IC芯片特性在后期制造（即晶片级或模块级）性能路径测试中获得的IC芯片性能测量和从系统获取的系统性能测量之间进行相关其中包含先前经过性能路径测试的那些IC芯片。基于这种相关性和目标系统性能值，可以调整后制造（即晶片级或模块级）芯片布置规则以优化系统产量（即，确保随后制造的并入IC芯片的系统满足目标系统的性能价值）。可选地，可以在用于结合到系统中的IC芯片的设计期间执行这种处理的模拟，以便首先建立初始的芯片布置规则。

10. 发明申请

US20090150844A1 CRITICAL PATH SELECTION FOR AT-SPEED TEST 审中-公开
标题翻译：用于速度测试的关键路径选择
公开(公告)号：US20090150844A1
公开(公告)日：2009-06-11
申请号：US11954138
申请日：2007-12-11
申请人： Vikram Iyengar , David E. Lackey , Subbayyan Venkatesan , Chandramouli Visweswariah , Jinjun Xiong
发明人： Vikram Iyengar , David E. Lackey , Subbayyan Venkatesan , Chandramouli Visweswariah , Jinjun Xiong
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method of critical path selection provides a set of paths that initially contains no paths. A timing tool is used to identify potential critical paths of an integrated circuit design. Each potential critical path is evaluated and the potential critical path is added to the set of paths if logic devices within the potential critical path are shared by less than a predetermined number of critical paths within the set of paths. This evaluating and adding process is repeated for each of the potential critical paths until all of the potential critical paths have been evaluated. Then, the potential critical paths within the set of paths can be output.
摘要翻译：关键路径选择的方法提供了一组最初不包含路径的路径。定时工具用于识别集成电路设计的潜在关键路径。如果潜在的关键路径内的逻辑设备被小于路径集合内预定数量的关键路径共享，则评估每个潜在的关键路径并将潜在的关键路径添加到路径集合。对于每个潜在的关键路径重复该评估和添加过程，直到所有潜在的关键路径都被评估为止。然后，可以输出该组路径内的潜在关键路径。

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