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1. 发明授权

US06563346B2 Phase independent frequency comparator 失效
标题翻译：相位独立频率比较器
公开(公告)号：US06563346B2
公开(公告)日：2003-05-13
申请号：US09683319
申请日：2001-12-13
申请人： Jean-Claude Abbiate , Carl Cederbaum
发明人： Jean-Claude Abbiate , Carl Cederbaum
IPC分类号： H03D300
CPC分类号： H03D13/003
摘要： A method and circuit for comparing the frequencies of two clocks (clock—1 and clock—2), without taking into account their phase, is disclosed. Each clock is associated to a circular counter (100-1 and 100-2) which are initialized to different values, and the contents of the circular counters are compared. When the frequencies of the two clocks (clock—1 and clock—2) are equal, both counters (100-1 and 100-2) are incremented at a common frequency and thus, due to the initialization conditions, the contents of both counters can never be equal. Conversely, when the frequencies of the two clocks are different, the counters (100-1 and 100-2) are not increased at a common frequency and thus, after several clock pulses, the contents of the counters are equal, indicating different clock frequencies. In a preferred embodiment, the circular counters (100-1 and 100-2) are 2-bit circular counters.
摘要翻译：公开了一种用于比较两个时钟（时钟-1和时钟-2）的频率而不考虑它们的相位的方法和电路。每个时钟与循环计数器（100-1和100-2）相关联，其被初始化为不同的值，并且比较圆形计数器的内容。当两个时钟（时钟-1和时钟-2）的频率相等时，两个计数器（100-1和100-2）以公共频率递增，因此，由于初始化条件，两个计数器的内容永远不能平等相反，当两个时钟的频率不同时，计数器（100-1和100-2）不以共同频率增加，因此在几个时钟脉冲之后，计数器的内容相等，表示不同的时钟频率。在优选实施例中，循环计数器（100-1和100-2）是2位循环计数器。

2. 发明授权

US5112765A Method of forming stacked tungsten gate PFET devices and structures resulting therefrom 失效
标题翻译：形成叠层钨栅PFET器件的方法及由此产生的结构
公开(公告)号：US5112765A
公开(公告)日：1992-05-12
申请号：US730736
申请日：1991-07-16
申请人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone , Vincent Vallet
发明人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone , Vincent Vallet
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/822 , H01L21/8238 , H01L21/8244 , H01L23/52 , H01L27/00 , H01L27/092 , H01L27/11
CPC分类号： H01L27/1108 , H01L21/76895 , H01L21/8221 , H01L27/11 , Y10S148/164
摘要： A manufacturing method is provided for producing a stacked semiconductor structure including: depositing a first thick passivating layer onto the base structure; forming first stud openings in the first thick passivating layer exposing at least one active region and/or one of the polysilicon lines; depositing a first layer of a conductive material to fill the first stud openings and define first contact studs, the upper part of some of the first contact studs comprising the gate electrodes of PFET devices; planarizing the structure to make the top surface of the first contact studs coplanar with the surface of the first thick passivating layer; depositing a thick insulating layer to form the gate dielectric of PFET devices and patterning it to define contact openings to expose selected first contact studs at desired locations; depositing a layer of polysilicon; patterning the polysilicon layer to define polysilicon lands containing the first contact studs at the desired locations; selectively implanting to define the source and drain regions of the PFET devices and interconnection conductors; depositing a cap layer; depositing a second thick passivating layer forming second stud openings in the second thick passivating layer to expose desired portions of the polysilicon lands and/or portions of the first contact studs; depositing a second layer of conductive material to define second contact studs; and planarizing the structure to make the top surface of the second contact studs coplanar with the surface of the second thick passivating layer.
摘要翻译：提供一种用于制造堆叠半导体结构的制造方法，包括：将第一厚钝化层沉积到基底结构上; 在所述第一厚钝化层中形成暴露至少一个有源区和/或所述多晶硅线之一的第一螺柱开口; 沉积导电材料的第一层以填充第一螺柱开口并限定第一接触螺柱，一些第一接触柱的上部包括PFET器件的栅电极; 平面化结构以使第一接触柱的顶表面与第一厚钝化层的表面共面; 沉积厚的绝缘层以形成PFET器件的栅极电介质，并将其图形化以限定接触开口，以在期望的位置暴露所选择的第一触头柱; 沉积一层多晶硅; 图案化多晶硅层以限定在期望位置处包含第一接触柱的多晶硅焊盘; 选择性地注入以限定PFET器件和互连导体的源区和漏区; 沉积盖层; 在所述第二厚钝化层中沉积形成第二螺柱孔的第二厚钝化层以暴露所述多晶硅焊盘的所述部分和/或所述第一触头柱的部分; 沉积第二层导电材料以限定第二接触柱; 并且平坦化该结构以使第二接触柱的顶表面与第二厚钝化层的表面共面。

3. 发明授权

US5381046A Stacked conductive resistive polysilicon lands in multilevel semiconductor chips 失效
标题翻译：多层半导体芯片中堆叠的导电电阻式多晶硅焊盘
公开(公告)号：US5381046A
公开(公告)日：1995-01-10
申请号：US160470
申请日：1993-12-01
申请人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone
发明人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60 , H01L21/768 , H01L23/522 , H01L23/532 , H01L27/10 , H01L29/52 , H01L29/54
CPC分类号： H01L21/76897 , H01L21/76802 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/53271 , H01L2924/0002 , Y10S257/904
摘要： A semiconductor structure for making four device SRAMs with stacked polysilicon load resistors (4D/2R SRAM cells) in CMOS FET technology. The structure is formed from a semiconductor substrate with active regions of devices therein and polysilicon lines formed thereupon. A first thick passivating layer is formed of an etch stop layer and a layer of phosphosilicate glass (PSG) above the substrate. A set of first metal contact studs through the first thick passivating layer contacts at least one of the active regions and/or the polysilicon lines. The etch stop layer (26) may be of intrinsic polysilicon or Al.sub.2 O.sub.3. The top surface of the first contact studs is coplanar with the top surface of the first thick passivating layers. A plurality of polysilicon lands formed on the planar structure contact the first contact studs. The polysilicon lands are highly resistive, highly conductive or a mix thereof. A second thick passivating layer is formed above the resulting structure having a set of second metal contact studs therein. The second metal studs contact at least one of the polysilicon lands and/or one of the first contact studs. The top surface of the second contact studs is coplanar with the top surface of the second thick passivating layer. A plurality of metal lands is formed above the second thick passivating layer and in contact with the second contact studs. A final insulating film insulates and passivates the metal lands.
摘要翻译：一种半导体结构，用于在CMOS FET技术中制造具有堆叠多晶硅负载电阻（4D / 2R SRAM单元）的四个器件SRAM。该结构由其中具有器件的有源区的半导体衬底形成，并且在其上形成多晶硅线。第一厚钝化层由衬底上方的蚀刻停止层和磷硅酸盐玻璃（PSG）层形成。通过第一厚钝化层的一组第一金属触头柱接触有源区和/或多晶硅线中的至少一个。蚀刻停止层（26）可以是本征多晶硅或Al 2 O 3。第一接触柱的顶表面与第一厚钝化层的顶表面共面。形成在平面结构上的多个多晶硅焊盘与第一触头柱接触。多晶硅焊盘是高电阻性，高导电性或其混合物。在所得结构之上形成第二厚钝化层，其中具有一组第二金属接触柱。第二金属螺柱接触至少一个多晶硅焊盘和/或第一接触螺柱之一。第二接触柱的顶表面与第二厚钝化层的顶表面共面。多个金属焊盘形成在第二厚钝化层之上并且与第二接触柱接触。最终的绝缘膜绝缘并钝化金属焊盘。

4. 发明授权

US5275963A Method of forming stacked conductive and/or resistive polysilicon lands in multilevel semiconductor chips and structures resulting therefrom 失效
标题翻译：在多层半导体芯片中形成堆叠的导电和/或电阻多晶硅焊盘的方法及由此产生的结构
公开(公告)号：US5275963A
公开(公告)日：1994-01-04
申请号：US728929
申请日：1991-07-12
申请人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone
发明人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60 , H01L21/768 , H01L23/522 , H01L23/532 , H01L27/10 , H01L21/98
CPC分类号： H01L21/76897 , H01L21/76802 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/53271 , H01L2924/0002 , Y10S257/904
摘要： A semiconductor structure including: a semiconductor substrate (18/19) having active regions (21) of devices (T1, . . . ) therein and/or polysilicon lines (23-1, . . .) formedthereupon; a first thick passivating layer (26/27) formed above the substrate having a set of first metal contact studs (30-1, . . .) therein contacting at least one of the active regions (21) and/or the polysilicon lines (23-1, . . . ); the surface of the first contact studs is coplanar with the surface of the first passivating layer; a plurality of polysilicon lands (31-1, . . .) formed on the planar structure in contact with the first contact studs; the polysilicon lands are either highly resistive, highly conductive or a mix thereof; a second thick passivating layer (34/35) formed above the resulting structure having a set of second metal contact-studs (37-1 . . .) therein contacting at least one of the polysilicon lands and/or one of the first contact studs; the surface of the second contact studs is coplanar with the surface of the second thick passivating layer. a plurality of metal lands (38-1, . . . ) formed above the second thick passivating layer (34/35) in contact with the second contact studs; a final insulating film (39).The structure of the present invention may be advantageously used in chips implementing four device SRAM cells with stacked polysilicon load resistors (4D/2R SRAM cells) in CMOS FET technology.The present invention also relates to the method for fabricating the same.
摘要翻译：一种半导体结构，包括：其中形成有器件（T1 ...）的有源区（21）和/或在其上形成的多晶硅线（23-1 ...）的半导体衬底（18/19）形成在衬底上方的第一厚钝化层（26/27），其具有一组第一金属触头柱（30-1 ...），其接触至少一个有源区（21）和/或多晶硅线（ 23-1，...）; 所述第一触头柱的表面与所述第一钝化层的表面共面; 形成在与所述第一触头柱接触的所述平面结构上的多个多晶硅焊盘（31-1 ...）多晶硅焊盘是高电阻性，高导电性或其混合物; 形成在所得结构上方的第二厚钝化层（34/35），其具有一组第二金属触头螺柱（37-1 ...），其接触多晶硅焊盘中的至少一个和/或第一触头螺柱中的一个 ; 第二接触柱的表面与第二厚钝化层的表面共面。形成在与第二接触柱接触的第二厚钝化层（34/35）上方的多个金属焊盘（38-1 ...）最后的绝缘膜（39）。本发明的结构可有利地用于在CMOS FET技术中实现具有堆叠多晶硅负载电阻（4D / 2R SRAM单元）的四个器件SRAM单元的芯片中。本发明还涉及其制造方法。

5. 发明授权

US5320975A Method of forming thin film pseudo-planar FET devices and structures resulting therefrom 失效
标题翻译：形成薄膜伪平面FET器件的方法及由此产生的结构
公开(公告)号：US5320975A
公开(公告)日：1994-06-14
申请号：US34325
申请日：1993-03-22
申请人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone
发明人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone
IPC分类号： H01L21/8249 , H01L21/8244 , H01L27/06 , H01L27/105 , H01L27/11 , H01L29/78 , H01L21/70 , H01L27/00
CPC分类号： H01L27/11 , H01L27/1108 , H01L27/1116 , H01L27/1207 , H01L29/7838 , H01L27/105 , Y10S257/903
摘要： A method of forming thin film pseudo-planar polysilicon gate PFETs (pPFETs) simultaneously with bulk PFET and NFET devices in a CMOS or BiCMOS semiconductor structure, comprising the steps of: providing a P-type silicon substrate having a surface that includes a plurality of isolation regions; delineating polysilicon lands at selected isolation regions; forming N-well regions into the substrate at a location where bulk PFETs are to be subsequently formed; forming insulator encapsulated conductive polysilicon studs to provide gate electrodes at desired locations of the structure; forming self-aligned source/drain regions of the bulk NFETs into the substrate; forming self-aligned source/drain regions of the bulk PFETs and pPFETs into the substrate and into the polysilicon lands, respectively; and forming contact regions to the selected locations that include the source/drain regions. In particular, the method finds application in the formation of polysilicon PFETs which are extensively used as load devices in six device (6D) SRAM cells.
摘要翻译：一种在CMOS或BiCMOS半导体结构中与本体PFET和NFET器件同时形成薄膜伪平面多晶硅栅极PFET（pPFET）的方法，包括以下步骤：提供具有表面的P型硅衬底，所述表面包括多个隔离区; 在选定的隔离区划定多晶硅土地; 在随后形成体PFET的位置处形成N阱区域到衬底中; 形成绝缘体封装的导电多晶硅柱钉，以在结构的期望位置处提供栅电极; 将本体NFET的自对准源极/漏极区域形成到衬底中; 将本体PFET和pPFET的自对准源极/漏极区分别形成到衬底中并进入多晶硅焊盘; 以及将接触区域形成到包括源极/漏极区域的选定位置。特别地，该方法可用于形成多晶硅PFET，其广泛用作六个器件（6D）SRAM单元中的负载器件。

6. 发明授权

US5748125A Digital delay interpolator circuit 失效
标题翻译：数字延迟内插电路
公开(公告)号：US5748125A
公开(公告)日：1998-05-05
申请号：US751286
申请日：1996-11-18
申请人： Carl Cederbaum , Philippe Girard , Patrick Mone
发明人： Carl Cederbaum , Philippe Girard , Patrick Mone
IPC分类号： H03L7/099 , H03K5/00 , H03K5/13 , H03M1/66
CPC分类号： H03K5/133 , H03K2005/00052 , H03L7/099
摘要： Disclosed is a delay interpolator (DI) circuit (or mixer) that can be driven by digital signals. This DI circuit may be incorporated in the loop of a delay interpolator voltage controlled oscillator (DIVCO) circuit. In turn, the digital DIVCO circuit may be inserted in the loop of a phase-locked loop (PLL) circuit for total digitalization thereof. The novel digital delay interpolator circuit (23) has the base structure of the conventional analog delay interpolator circuit except in that, at the first (bottom) level, the two standard NFET input devices which are normally controlled by an analog signal (typically generated by a preceding DAC) are respectively replaced by two arrays (24A, 24B) of smaller NFET devices connected in parallel. The gate of each NFET device of the first array is driven by a bit (c0, c1, . . . ) of the true phase of the digital signal. The gate of each NFET device of the second array is driven by a bit (c0, c1, . . . ) of the complementary phase of the digital signal. For instance, in the loop of a PLL circuit, this digital signal (Sfilt) is generated by the phase detector, then filtered in a digital filter and stored in a thermometer register. As a result, the DAC is no longer necessary thereby saving significant room and energy consumption.
摘要翻译：公开了可以由数字信号驱动的延迟内插器（DI）电路（或混频器）。该DI电路可以并入延迟内插器压控振荡器（DIVCO）电路的回路中。反过来，数字DIVCO电路可以被插入到锁相环（PLL）电路的环路中，用于其数字化。新颖的数字延迟内插器电路（23）具有常规模拟延迟内插器电路的基本结构，除了在第一（底部）电平处，正常由模拟信号控制的两个标准NFET输入装置（通常由前面的DAC）分别由并联连接的较小NFET器件的两个阵列（24A，24B）代替。第一阵列的每个NFET器件的栅极由数字信号真相的位（c0，c1，...）驱动。第二阵列的每个NFET器件的栅极由数字信号的互补相位的位（c0，c1，...）驱动。例如，在PLL电路的环路中，该数字信号（Sfilt）由相位检测器产生，然后在数字滤波器中滤波并存储在温度计寄存器中。因此，DAC不再需要，从而节省大量的房间和能源消耗。

7. 发明授权

US5319262A Low power TTL/CMOS receiver circuit 失效
标题翻译：低功耗TTL / CMOS接收电路
公开(公告)号：US5319262A
公开(公告)日：1994-06-07
申请号：US15193
申请日：1993-02-10
申请人： Carl Cederbaum , Philippe Girard
发明人： Carl Cederbaum , Philippe Girard
IPC分类号： H01L21/8234 , G11C11/419 , H01L21/8238 , H01L27/088 , H01L27/092 , H03K5/151 , H03K19/00 , H03K19/0185 , H03K19/0948
CPC分类号： H03K19/0013 , H03K19/018521 , H03K5/151
摘要： A low power TTL/CMOS receiver circuit consists of four stages, each of which is, respectively, comprised of at least two complementary FET devices connected to each other in series. The various stages control each other by a variety of feedback interconnections. The use of feedback loops permits to significantly decrease the DC current in the input stage of the receiver circuit. It also realizes a substantial decrease in AC current consumption, although less significantly. Finally, delay variations between input and output signals are obtained as well as substantial improvements in the symmetry between the true and complement output signals of the receiver circuit.
摘要翻译：低功率TTL / CMOS接收器电路由四个级组成，分别由串联连接的至少两个互补型FET器件构成。各个阶段通过各种反馈互连来相互控制。反馈回路的使用允许显着降低接收器电路的输入级中的直流电流。它也实现了交流电流消耗的显着降低，尽管不太显着。最后，获得输入和输出信号之间的延迟变化以及接收机电路的真实和补码输出信号之间的对称性的实质性改进。

8. 发明授权

US5100817A Method of forming stacked self-aligned polysilicon PFET devices and structures resulting therefrom 失效
公开(公告)号：US5100817A
公开(公告)日：1992-03-31
申请号：US729250
申请日：1991-07-12
申请人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone
发明人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/822 , H01L21/8244 , H01L27/11 , H01L29/78 , H01L29/786
CPC分类号： H01L27/11 , H01L21/8221 , H01L27/1108
摘要： A stacked semiconductor structure including a base structure (18/19) is comprised of a semiconductor substrate having active regions (21) of devices (N1, . . . ) formed therein and/or a plurality of polysilicon lines (23-1, . . . ) formed thereupon; a first thick passivating layer (26/27) having a set of first metal contact studs (30-1, . . . ) therein contacting at least one of said active regions (21) and/or said polysilicon lines (23-1, . . . ), the surface of said first metal contact studs being coplanar with the surface of said first thick passivating layer; a plurality of first polysilicon lands (31-1, . . . ) formed on the said thick passivating layer, certain portions of said first polysilicon lands defining the source, drain and channel regions forming the body of a PFET device with at least one region (SP1) contacting one of said first metal contact studs; a thin insulating layer (33) forming the gate dielectric layer of said PFET device; a plurality of highly doped second polysilicon lands (35-1A, . . . ) formed over by said thin insulating layer (33); a certain portion of said second polysilicon lands (35-1A, . . . ) forming the gate electrode (GP1) of said PFET device (SP1) which is self-aligned with said source (SP1) and drain (DP1) regions; a second thick passivating layer (37/38) having a set of second metal contact studs (40-1, . . . ) therein contacting at least one of said first or second polysilicon lands (31-1, . . . ; 35-1, . . . ) and/or said first contact studs (30-1, . . . ); the surface of said second metal contact studs is coplanar with the surface of said second thick passivating layer; a first metal interconnection configuration having metal lands (41-1, . . . ) electrically contacting at least one of said second metal contact studs (40-1, . . . ); and, a final insulating film (42).

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