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1. 发明授权

US5112765A Method of forming stacked tungsten gate PFET devices and structures resulting therefrom 失效
标题翻译：形成叠层钨栅PFET器件的方法及由此产生的结构
公开(公告)号：US5112765A
公开(公告)日：1992-05-12
申请号：US730736
申请日：1991-07-16
申请人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone , Vincent Vallet
发明人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone , Vincent Vallet
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/822 , H01L21/8238 , H01L21/8244 , H01L23/52 , H01L27/00 , H01L27/092 , H01L27/11
CPC分类号： H01L27/1108 , H01L21/76895 , H01L21/8221 , H01L27/11 , Y10S148/164
摘要： A manufacturing method is provided for producing a stacked semiconductor structure including: depositing a first thick passivating layer onto the base structure; forming first stud openings in the first thick passivating layer exposing at least one active region and/or one of the polysilicon lines; depositing a first layer of a conductive material to fill the first stud openings and define first contact studs, the upper part of some of the first contact studs comprising the gate electrodes of PFET devices; planarizing the structure to make the top surface of the first contact studs coplanar with the surface of the first thick passivating layer; depositing a thick insulating layer to form the gate dielectric of PFET devices and patterning it to define contact openings to expose selected first contact studs at desired locations; depositing a layer of polysilicon; patterning the polysilicon layer to define polysilicon lands containing the first contact studs at the desired locations; selectively implanting to define the source and drain regions of the PFET devices and interconnection conductors; depositing a cap layer; depositing a second thick passivating layer forming second stud openings in the second thick passivating layer to expose desired portions of the polysilicon lands and/or portions of the first contact studs; depositing a second layer of conductive material to define second contact studs; and planarizing the structure to make the top surface of the second contact studs coplanar with the surface of the second thick passivating layer.
摘要翻译：提供一种用于制造堆叠半导体结构的制造方法，包括：将第一厚钝化层沉积到基底结构上; 在所述第一厚钝化层中形成暴露至少一个有源区和/或所述多晶硅线之一的第一螺柱开口; 沉积导电材料的第一层以填充第一螺柱开口并限定第一接触螺柱，一些第一接触柱的上部包括PFET器件的栅电极; 平面化结构以使第一接触柱的顶表面与第一厚钝化层的表面共面; 沉积厚的绝缘层以形成PFET器件的栅极电介质，并将其图形化以限定接触开口，以在期望的位置暴露所选择的第一触头柱; 沉积一层多晶硅; 图案化多晶硅层以限定在期望位置处包含第一接触柱的多晶硅焊盘; 选择性地注入以限定PFET器件和互连导体的源区和漏区; 沉积盖层; 在所述第二厚钝化层中沉积形成第二螺柱孔的第二厚钝化层以暴露所述多晶硅焊盘的所述部分和/或所述第一触头柱的部分; 沉积第二层导电材料以限定第二接触柱; 并且平坦化该结构以使第二接触柱的顶表面与第二厚钝化层的表面共面。

2. 发明授权

US5275963A Method of forming stacked conductive and/or resistive polysilicon lands in multilevel semiconductor chips and structures resulting therefrom 失效
标题翻译：在多层半导体芯片中形成堆叠的导电和/或电阻多晶硅焊盘的方法及由此产生的结构
公开(公告)号：US5275963A
公开(公告)日：1994-01-04
申请号：US728929
申请日：1991-07-12
申请人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone
发明人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60 , H01L21/768 , H01L23/522 , H01L23/532 , H01L27/10 , H01L21/98
CPC分类号： H01L21/76897 , H01L21/76802 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/53271 , H01L2924/0002 , Y10S257/904
摘要： A semiconductor structure including: a semiconductor substrate (18/19) having active regions (21) of devices (T1, . . . ) therein and/or polysilicon lines (23-1, . . .) formedthereupon; a first thick passivating layer (26/27) formed above the substrate having a set of first metal contact studs (30-1, . . .) therein contacting at least one of the active regions (21) and/or the polysilicon lines (23-1, . . . ); the surface of the first contact studs is coplanar with the surface of the first passivating layer; a plurality of polysilicon lands (31-1, . . .) formed on the planar structure in contact with the first contact studs; the polysilicon lands are either highly resistive, highly conductive or a mix thereof; a second thick passivating layer (34/35) formed above the resulting structure having a set of second metal contact-studs (37-1 . . .) therein contacting at least one of the polysilicon lands and/or one of the first contact studs; the surface of the second contact studs is coplanar with the surface of the second thick passivating layer. a plurality of metal lands (38-1, . . . ) formed above the second thick passivating layer (34/35) in contact with the second contact studs; a final insulating film (39).The structure of the present invention may be advantageously used in chips implementing four device SRAM cells with stacked polysilicon load resistors (4D/2R SRAM cells) in CMOS FET technology.The present invention also relates to the method for fabricating the same.
摘要翻译：一种半导体结构，包括：其中形成有器件（T1 ...）的有源区（21）和/或在其上形成的多晶硅线（23-1 ...）的半导体衬底（18/19）形成在衬底上方的第一厚钝化层（26/27），其具有一组第一金属触头柱（30-1 ...），其接触至少一个有源区（21）和/或多晶硅线（ 23-1，...）; 所述第一触头柱的表面与所述第一钝化层的表面共面; 形成在与所述第一触头柱接触的所述平面结构上的多个多晶硅焊盘（31-1 ...）多晶硅焊盘是高电阻性，高导电性或其混合物; 形成在所得结构上方的第二厚钝化层（34/35），其具有一组第二金属触头螺柱（37-1 ...），其接触多晶硅焊盘中的至少一个和/或第一触头螺柱中的一个 ; 第二接触柱的表面与第二厚钝化层的表面共面。形成在与第二接触柱接触的第二厚钝化层（34/35）上方的多个金属焊盘（38-1 ...）最后的绝缘膜（39）。本发明的结构可有利地用于在CMOS FET技术中实现具有堆叠多晶硅负载电阻（4D / 2R SRAM单元）的四个器件SRAM单元的芯片中。本发明还涉及其制造方法。

3. 发明授权

US5381046A Stacked conductive resistive polysilicon lands in multilevel semiconductor chips 失效
标题翻译：多层半导体芯片中堆叠的导电电阻式多晶硅焊盘
公开(公告)号：US5381046A
公开(公告)日：1995-01-10
申请号：US160470
申请日：1993-12-01
申请人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone
发明人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60 , H01L21/768 , H01L23/522 , H01L23/532 , H01L27/10 , H01L29/52 , H01L29/54
CPC分类号： H01L21/76897 , H01L21/76802 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/53271 , H01L2924/0002 , Y10S257/904
摘要： A semiconductor structure for making four device SRAMs with stacked polysilicon load resistors (4D/2R SRAM cells) in CMOS FET technology. The structure is formed from a semiconductor substrate with active regions of devices therein and polysilicon lines formed thereupon. A first thick passivating layer is formed of an etch stop layer and a layer of phosphosilicate glass (PSG) above the substrate. A set of first metal contact studs through the first thick passivating layer contacts at least one of the active regions and/or the polysilicon lines. The etch stop layer (26) may be of intrinsic polysilicon or Al.sub.2 O.sub.3. The top surface of the first contact studs is coplanar with the top surface of the first thick passivating layers. A plurality of polysilicon lands formed on the planar structure contact the first contact studs. The polysilicon lands are highly resistive, highly conductive or a mix thereof. A second thick passivating layer is formed above the resulting structure having a set of second metal contact studs therein. The second metal studs contact at least one of the polysilicon lands and/or one of the first contact studs. The top surface of the second contact studs is coplanar with the top surface of the second thick passivating layer. A plurality of metal lands is formed above the second thick passivating layer and in contact with the second contact studs. A final insulating film insulates and passivates the metal lands.
摘要翻译：一种半导体结构，用于在CMOS FET技术中制造具有堆叠多晶硅负载电阻（4D / 2R SRAM单元）的四个器件SRAM。该结构由其中具有器件的有源区的半导体衬底形成，并且在其上形成多晶硅线。第一厚钝化层由衬底上方的蚀刻停止层和磷硅酸盐玻璃（PSG）层形成。通过第一厚钝化层的一组第一金属触头柱接触有源区和/或多晶硅线中的至少一个。蚀刻停止层（26）可以是本征多晶硅或Al 2 O 3。第一接触柱的顶表面与第一厚钝化层的顶表面共面。形成在平面结构上的多个多晶硅焊盘与第一触头柱接触。多晶硅焊盘是高电阻性，高导电性或其混合物。在所得结构之上形成第二厚钝化层，其中具有一组第二金属接触柱。第二金属螺柱接触至少一个多晶硅焊盘和/或第一接触螺柱之一。第二接触柱的顶表面与第二厚钝化层的顶表面共面。多个金属焊盘形成在第二厚钝化层之上并且与第二接触柱接触。最终的绝缘膜绝缘并钝化金属焊盘。

4. 发明授权

US5320975A Method of forming thin film pseudo-planar FET devices and structures resulting therefrom 失效
标题翻译：形成薄膜伪平面FET器件的方法及由此产生的结构
公开(公告)号：US5320975A
公开(公告)日：1994-06-14
申请号：US34325
申请日：1993-03-22
申请人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone
发明人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone
IPC分类号： H01L21/8249 , H01L21/8244 , H01L27/06 , H01L27/105 , H01L27/11 , H01L29/78 , H01L21/70 , H01L27/00
CPC分类号： H01L27/11 , H01L27/1108 , H01L27/1116 , H01L27/1207 , H01L29/7838 , H01L27/105 , Y10S257/903
摘要： A method of forming thin film pseudo-planar polysilicon gate PFETs (pPFETs) simultaneously with bulk PFET and NFET devices in a CMOS or BiCMOS semiconductor structure, comprising the steps of: providing a P-type silicon substrate having a surface that includes a plurality of isolation regions; delineating polysilicon lands at selected isolation regions; forming N-well regions into the substrate at a location where bulk PFETs are to be subsequently formed; forming insulator encapsulated conductive polysilicon studs to provide gate electrodes at desired locations of the structure; forming self-aligned source/drain regions of the bulk NFETs into the substrate; forming self-aligned source/drain regions of the bulk PFETs and pPFETs into the substrate and into the polysilicon lands, respectively; and forming contact regions to the selected locations that include the source/drain regions. In particular, the method finds application in the formation of polysilicon PFETs which are extensively used as load devices in six device (6D) SRAM cells.
摘要翻译：一种在CMOS或BiCMOS半导体结构中与本体PFET和NFET器件同时形成薄膜伪平面多晶硅栅极PFET（pPFET）的方法，包括以下步骤：提供具有表面的P型硅衬底，所述表面包括多个隔离区; 在选定的隔离区划定多晶硅土地; 在随后形成体PFET的位置处形成N阱区域到衬底中; 形成绝缘体封装的导电多晶硅柱钉，以在结构的期望位置处提供栅电极; 将本体NFET的自对准源极/漏极区域形成到衬底中; 将本体PFET和pPFET的自对准源极/漏极区分别形成到衬底中并进入多晶硅焊盘; 以及将接触区域形成到包括源极/漏极区域的选定位置。特别地，该方法可用于形成多晶硅PFET，其广泛用作六个器件（6D）SRAM单元中的负载器件。

5. 发明授权

US5100817A Method of forming stacked self-aligned polysilicon PFET devices and structures resulting therefrom 失效
公开(公告)号：US5100817A
公开(公告)日：1992-03-31
申请号：US729250
申请日：1991-07-12
申请人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone
发明人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/822 , H01L21/8244 , H01L27/11 , H01L29/78 , H01L29/786
CPC分类号： H01L27/11 , H01L21/8221 , H01L27/1108
摘要： A stacked semiconductor structure including a base structure (18/19) is comprised of a semiconductor substrate having active regions (21) of devices (N1, . . . ) formed therein and/or a plurality of polysilicon lines (23-1, . . . ) formed thereupon; a first thick passivating layer (26/27) having a set of first metal contact studs (30-1, . . . ) therein contacting at least one of said active regions (21) and/or said polysilicon lines (23-1, . . . ), the surface of said first metal contact studs being coplanar with the surface of said first thick passivating layer; a plurality of first polysilicon lands (31-1, . . . ) formed on the said thick passivating layer, certain portions of said first polysilicon lands defining the source, drain and channel regions forming the body of a PFET device with at least one region (SP1) contacting one of said first metal contact studs; a thin insulating layer (33) forming the gate dielectric layer of said PFET device; a plurality of highly doped second polysilicon lands (35-1A, . . . ) formed over by said thin insulating layer (33); a certain portion of said second polysilicon lands (35-1A, . . . ) forming the gate electrode (GP1) of said PFET device (SP1) which is self-aligned with said source (SP1) and drain (DP1) regions; a second thick passivating layer (37/38) having a set of second metal contact studs (40-1, . . . ) therein contacting at least one of said first or second polysilicon lands (31-1, . . . ; 35-1, . . . ) and/or said first contact studs (30-1, . . . ); the surface of said second metal contact studs is coplanar with the surface of said second thick passivating layer; a first metal interconnection configuration having metal lands (41-1, . . . ) electrically contacting at least one of said second metal contact studs (40-1, . . . ); and, a final insulating film (42).

6. 发明授权

US5223914A Follow-up system for etch process monitoring 失效
标题翻译：用于蚀刻过程监控的后续系统
公开(公告)号：US5223914A
公开(公告)日：1993-06-29
申请号：US821108
申请日：1992-01-15
申请人： Bernard Auda , Roland Chanclou
发明人： Bernard Auda , Roland Chanclou
IPC分类号： G03F7/26 , G03F7/40 , H01L21/027 , H01L21/28 , H01L21/3213
CPC分类号： G03F7/26 , H01L21/0274 , H01L21/28123 , H01L21/32137 , H01L21/32139 , G03F7/40
摘要： A follow-up system for monitoring the etching process in RIE equipment. A spectrometer is used in an interferometric mode for accurate thickness measuring to produce high-resolution and reproducible patterns in a layer of etchable material formed on a substrate.
摘要翻译：用于监测RIE设备中的蚀刻工艺的后续系统。光谱仪以干涉测量模式用于精确的厚度测量，以在形成在基底上的可蚀刻材料层中产生高分辨率和可再现的图案。

7. 发明授权

US5139904A Method of producing high resolution and reproducible patterns 失效
标题翻译：产生高分辨率和可重现图案的方法
公开(公告)号：US5139904A
公开(公告)日：1992-08-18
申请号：US509920
申请日：1990-04-16
申请人： Bernard Auda , Roland Chanclou
发明人： Bernard Auda , Roland Chanclou
IPC分类号： G03F7/26 , G03F7/40 , H01L21/027 , H01L21/28 , H01L21/30 , H01L21/302 , H01L21/3065 , H01L21/3213 , H01L29/78
CPC分类号： G03F7/26 , H01L21/0274 , H01L21/28123 , H01L21/32137 , H01L21/32139 , G03F7/40
摘要： A method of producing high-resolution and reproducible patterns, typically polysilicon ultra-fine lines. According to a preferred embodiment of the method, a layer of a standard radiation-sensitive resist is applied over a polysilicon layer formed on a substrate. The photoresist is delineated as is standard in conventional UV lithography equipment to produce a first resist pattern. The structure is then placed in reactive ion etching (RIE) equipment and the resist pattern is isotropically eroded to reduce overall dimensions. The etched thickness (dTH) is accurately measured by interferometric techniques, so that the corresponding lateral dimension reduction (dW) is continuously monitored. The etching is terminated when the appropriate lateral dimension reduction has been obtained to produce a second resist pattern of the desired final width (LWf). The second resist pattern (17a') is then anisotropically transferred to the underlying polysilicon layer by reactive ion etching. Finally, the second resist pattern is removed to leave the desired polysilicon pattern having the desired final width (LWf).
摘要翻译：一种产生高分辨率和可再现图案的方法，通常是多晶硅超细线。根据该方法的优选实施例，将标准辐射敏感抗蚀剂层施加在形成在基底上的多晶硅层上。如在常规UV光刻设备中标准化的光致抗蚀剂被描绘以产生第一抗蚀剂图案。然后将该结构放置在反应离子蚀刻（RIE）设备中，并且抗蚀剂图案被各向同性地侵蚀以减小总体尺寸。通过干涉技术精确测量蚀刻厚度（dTH），从而连续监测相应的横向尺寸减小（dW）。当获得适当的横向尺寸减小以产生所需最终宽度（LWf）的第二抗蚀剂图案时，蚀刻终止。然后通过反应离子蚀刻将第二抗蚀剂图案（17a'）各向异性地转移到下面的多晶硅层。最后，去除第二抗蚀剂图案以留出具有所需最终宽度（LWf）的所需多晶硅图案。

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