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1. 发明申请

US20120190201A1 MULTI-SELECTIVE POLISHING SLURRY COMPOSITION AND A SEMICONDUCTOR ELEMENT PRODUCTION METHOD USING THE SAME 审中-公开
标题翻译：多选择性抛光浆料组合物和使用其的半导体元件生产方法
公开(公告)号：US20120190201A1
公开(公告)日：2012-07-26
申请号：US13386494
申请日：2010-07-09
申请人： Jea-Gun Park , Un-Gyu Paik , Jin-Hyung Park , Hao Cui , Jong-Young Cho , Hee-Sub Hwang , Jae-Hyung Lim , Ye-Hwan Kim
发明人： Jea-Gun Park , Un-Gyu Paik , Jin-Hyung Park , Hao Cui , Jong-Young Cho , Hee-Sub Hwang , Jae-Hyung Lim , Ye-Hwan Kim
IPC分类号： H01L21/306 , C09K13/00
CPC分类号： H01L21/31056 , C09G1/02 , C09K3/1463 , H01L21/31053 , H01L21/3212
摘要： Provided are a multi-selective polishing slurry composition and a semiconductor element production method using the same. A silicon film provided with element patterns is formed on the uppermost part of a substrate having a first region and a second region. The element pattern density on the first region is higher than the element pattern density on the second region. Formed in sequence on top of the element patterns are a first silicon oxide film, a silicon nitride film and a second silicon oxide film. The substrate is subjected to chemical-mechanical polishing until the silicon film is exposed, by using a polishing slurry composition containing a polishing agent, a silicon nitride film passivation agent and a silicon film passivation agent. The polishing slurry composition may be a mixture of 100 parts by weight of a polishing agent suspension, containing a polishing agent, and from 40 to 120 parts by weight of an additive solution, and the additive solution can contain 100 parts by weight of a solvent, from 0.01 to 5 parts by weight of a silicon nitride film passivation agent and from 0.01 to 5 parts by weight of a silicon film passivation agent.
摘要翻译：提供多选择性研磨浆料组合物和使用其的半导体元件制造方法。具有元件图案的硅膜形成在具有第一区域和第二区域的基板的最上部。第一区域上的元件图案密度高于第二区域上的元件图案密度。在元件图案顶部依次形成第一氧化硅膜，氮化硅膜和第二氧化硅膜。通过使用包含抛光剂，氮化硅膜钝化剂和硅膜钝化剂的抛光浆料组合物，对基材进行化学机械抛光，直到暴露硅膜。抛光浆料组合物可以是100重量份的含有抛光剂的抛光剂悬浮液和40至120重量份的添加剂溶液的混合物，并且添加剂溶液可以包含100重量份的溶剂，0.01〜5重量份的氮化硅膜钝化剂和0.01〜5重量份的硅膜钝化剂。

2. 发明授权

US09163314B2 CMP slurry composition for tungsten 有权
标题翻译：钨的CMP浆料组成
公开(公告)号：US09163314B2
公开(公告)日：2015-10-20
申请号：US13643375
申请日：2012-07-06
申请人： Jea-Gun Park , Jin-Hyung Park , Jae-Hyung Lim , Jong-Young Cho , Ho Choi , Hee-Sub Hwang
发明人： Jea-Gun Park , Jin-Hyung Park , Jae-Hyung Lim , Jong-Young Cho , Ho Choi , Hee-Sub Hwang
IPC分类号： C09K3/14 , C09G1/02 , C23F1/30 , C23F3/06
CPC分类号： C23F1/30 , C09G1/02 , C23F3/06
摘要： The present invention relates to a CMP slurry composition for polishing tungsten comprising a abrasive and a polishing chemical, wherein the abrasive comprises colloidal silica dispersed in ultra-pure water, and the polishing chemical comprises hydrogen peroxide, ammonium persulfate and iron nitrate. The slurry composition is not discolored and has good etching selectivity, so as to be applied to a CMP process.
摘要翻译：本发明涉及一种用于抛光钨的CMP浆料组合物，其包括研磨剂和抛光化学品，其中磨料包含分散在超纯水中的胶体二氧化硅，抛光化学品包括过氧化氢，过硫酸铵和硝酸铁。浆料组合物不变色并且具有良好的蚀刻选择性，从而适用于CMP工艺。

3. 发明申请

US20130214199A1 CMP SLURRY COMPOSITION FOR TUNGSTEN 有权
标题翻译： CMP浆料组合物
公开(公告)号：US20130214199A1
公开(公告)日：2013-08-22
申请号：US13643375
申请日：2012-07-06
申请人： Jea-Gun Park , Jin-Hyung Park , Jae-Hyung Lim , Jong-Young Cho , Ho Choi , Hee-Sub Hwang
发明人： Jea-Gun Park , Jin-Hyung Park , Jae-Hyung Lim , Jong-Young Cho , Ho Choi , Hee-Sub Hwang
IPC分类号： C23F1/30
CPC分类号： C23F1/30 , C09G1/02 , C23F3/06
摘要： The present invention relates to a CMP slurry composition for polishing tungsten comprising a abrasive and a polishing chemical, wherein the abrasive comprises colloidal silica dispersed in ultra-pure water, and the polishing chemical comprises hydrogen peroxide, ammonium persulfate and iron nitrate. The slurry composition is not discolored and has good etching selectivity, so as to be applied to a CMP process.
摘要翻译：本发明涉及一种用于抛光钨的CMP浆料组合物，其包括研磨剂和抛光化学品，其中磨料包含分散在超纯水中的胶体二氧化硅，抛光化学品包括过氧化氢，过硫酸铵和硝酸铁。浆料组合物不变色并且具有良好的蚀刻选择性，从而适用于CMP工艺。

4. 发明申请

US20060207188A1 Ceria abrasive for cmp 审中-公开
标题翻译：二氧化铈磨料为cmp
公开(公告)号：US20060207188A1
公开(公告)日：2006-09-21
申请号：US10550804
申请日：2004-05-14
申请人： Un-Gyu Paik , Jea-Gun Park , Sang-Kyun Kim , Takeo Katoh , Yong-Kook Park
发明人： Un-Gyu Paik , Jea-Gun Park , Sang-Kyun Kim , Takeo Katoh , Yong-Kook Park
IPC分类号： C09K3/14
CPC分类号： C09G1/02 , C09K3/1463 , H01L21/31053
摘要： The present invention relates to a CMP abrasive comprising a ceria slurry and a chemical additive having two or more functional groups by mixing and synthesizing a polymeric molecule and a monomer. Also, the present invention relates to a method for a manufacturing CMP abrasive by providing a ceria slurry, manufacturing a chemical additive having two or more functional groups by mixing and synthesizing of the polymeric molecule and the monomer in a reactor, and mixing said slurry and said chemical additive. Therefore, when the abrasive according to the present invention is used as an STI CMP abrasive, it is possible to apply the abrasive to the patterning process required in the very large scale integration semiconductor process. Furthermore, the CMP abrasive of the present invention has a superior removal rate, superior polishing selectivity, superior within wafer non-uniformity (WIWNU), and minimized occurrence of micro scratches.
摘要翻译：本发明涉及通过混合和合成聚合物分子和单体，其包含二氧化铈浆料和具有两个或更多个官能团的化学添加剂的CMP磨料。另外，本发明涉及通过提供二氧化铈浆料制造CMP研磨剂的方法，通过在反应器中混合和合成聚合物分子和单体制备具有两个或多个官能团的化学添加剂，并将所述浆料和说化学添加剂。因此，当将根据本发明的研磨剂用作STI CMP研磨剂时，可以将磨料施加到非常大规模的集成半导体工艺中所需的图案化工艺。此外，本发明的CMP磨料具有优异的去除速度，优异的抛光选择性，在晶片不均匀性（WIWNU）内优异，并且微小划痕的发生最小化。

5. 发明申请

US20110127580A1 CAPACITOR-LESS MEMORY DEVICE 有权
标题翻译：无电容器存储器件
公开(公告)号：US20110127580A1
公开(公告)日：2011-06-02
申请号：US12990353
申请日：2009-04-30
申请人： Jea-Gun Park , Tae-Hun Shim , Gon-Sub Lee , Seong-Je Kim , Tae-Hyun Kim
发明人： Jea-Gun Park , Tae-Hun Shim , Gon-Sub Lee , Seong-Je Kim , Tae-Hyun Kim
IPC分类号： H01L29/772
CPC分类号： H01L29/4234 , G11C11/404 , G11C16/0466 , G11C2211/4016 , H01L27/10802 , H01L29/7841 , H01L29/78687 , H01L29/78696
摘要： Provided is a capacitorless memory device. The device includes a semiconductor substrate, an insulating layer disposed on the semiconductor substrate, a storage region disposed on a partial region of the insulating layer, a channel region disposed on the storage region to provide a valence band energy offset between the channel region and the storage region, a gate insulating layer and a gate electrode sequentially disposed on the channel region, and source and drain regions connected to the channel region and disposed at both sides of the gate electrode. A storage region having different valence band energy from a channel region is disposed under the channel region unit so that charges trapped in the storage region unit cannot be easily drained. Thus, a charge retention time may be increased to improve data storage capability.
摘要翻译：提供了一种无电容器存储器件。所述器件包括半导体衬底，设置在所述半导体衬底上的绝缘层，设置在所述绝缘层的部分区域上的存储区域，设置在所述存储区域上以在所述沟道区域和所述沟道区域之间提供价带能量偏移的沟道区域顺序地设置在沟道区上的栅极绝缘层和栅电极以及连接到沟道区并设置在栅电极两侧的源极和漏极区。在通道区域单元的下方配置具有与通道区域不同的价带能量的存储区域，使得捕获在存储区域单元中的电荷不容易排出。因此，可以增加电荷保留时间以提高数据存储能力。

6. 发明申请

US20120118366A1 DOUBLE-SIDED LIGHT-COLLECTING ORGANIC SOLAR CELL 审中-公开
标题翻译：双面收集有机太阳能电池
公开(公告)号：US20120118366A1
公开(公告)日：2012-05-17
申请号：US13387613
申请日：2010-07-07
申请人： Jea-Gun Park , Su-Hwan Lee , Ji-Heon Kim , Dal-Ho Kim
发明人： Jea-Gun Park , Su-Hwan Lee , Ji-Heon Kim , Dal-Ho Kim
IPC分类号： H01L51/44
CPC分类号： H01L27/302
摘要： Disclosed is a double-sided light-collecting organic solar cell. The double-sided light-collecting organic solar cell comprises: a first light-transmitting electrode; a first photoactive layer disposed on the first light-transmitting electrode; a reflective electrode disposed on the first photoactive layer; a second photoactive layer disposed on the reflective electrode; and a second light-transmitting electrode disposed on the second photoactive layer. According to the present invention, photoactive layers are formed on both sides of a reflective electrode in the middle, and light-transmitting electrodes are formed to enable light to be absorbed at both sides of a cell, to increase the light absorption of the cell and enable the production of a highly efficient organic solar cell.
摘要翻译：公开了一种双面收光有机太阳能电池。双面收集有机太阳能电池包括：第一透光电极; 设置在第一透光电极上的第一光敏层; 设置在所述第一光活性层上的反射电极; 设置在反射电极上的第二光敏层; 以及设置在所述第二光活性层上的第二透光电极。根据本发明，在中间的反射电极的两侧形成光敏层，并且形成透光电极以使光能够在电池的两侧被吸收，以增加电池的光吸收，能够生产高效的有机太阳能电池。

7. 发明授权

US08233313B2 Conductive organic non-volatile memory device with nanocrystals embedded in an amorphous barrier layer 有权
标题翻译：具有纳米晶体的导电有机非易失性存储器件嵌入在非晶形阻挡层中
公开(公告)号：US08233313B2
公开(公告)日：2012-07-31
申请号：US13286861
申请日：2011-11-01
申请人： Jea-Gun Park , Sung-Ho Seo , Woo-Sik Nam , Young-Hwan Oh , Yool-Guk Kim , Hyun-Min Seung , Jong-Dae Lee
发明人： Jea-Gun Park , Sung-Ho Seo , Woo-Sik Nam , Young-Hwan Oh , Yool-Guk Kim , Hyun-Min Seung , Jong-Dae Lee
IPC分类号： G11C13/02 , H01L27/28
CPC分类号： H01L27/285 , B82Y10/00 , G11C11/5664 , G11C13/0014 , G11C13/0016 , G11C2211/5614 , G11C2213/51 , G11C2216/06 , H01L51/0042 , H01L51/0591 , Y10S977/943
摘要： A non-volatile memory device includes a plurality of unit cells. Each unit cell includes lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive organic material layer, wherein the nanocrystal layer includes a plurality of nanocrystals surrounded by an amorphous barrier. The unit cell receives a plurality of voltage ranges to perform a plurality of operations. A read operation is performed when an input voltage is in a first voltage range. A first write operation is performed when the input voltage is in a second voltage range higher than the first voltage range. A second write operation is performed when the input voltage is in a third voltage range higher than the second voltage range. An erase operation is performed when the input voltage is higher than the third voltage range.
摘要翻译：非易失性存储器件包括多个单元电池。每个单元电池包括在基板上的下电极和上电极，在下电极和上电极之间的导电有机材料层和位于导电有机材料层内的纳米晶体层，其中纳米晶体层包括被非晶形态包围的多个纳米晶体屏障。单元接收多个电压范围以执行多个操作。当输入电压处于第一电压范围时执行读操作。当输入电压处于高于第一电压范围的第二电压范围时，执行第一写入操作。当输入电压处于高于第二电压范围的第三电压范围时，执行第二写入操作。当输入电压高于第三电压范围时，执行擦除操作。

8. 发明授权

US08050081B2 Conductive organic nonvolatile memory device having nanocrystals surrounded by amorphous barrier 有权
标题翻译：具有被无定形屏障包围的纳米晶体的导电有机非易失性存储器件
公开(公告)号：US08050081B2
公开(公告)日：2011-11-01
申请号：US12108465
申请日：2008-04-23
申请人： Jea-Gun Park , Sung-Ho Seo , Woo-Sik Nam , Young-Hwan Oh , Yool-Guk Kim , Hyun-Min Seung , Jong-Dae Lee
发明人： Jea-Gun Park , Sung-Ho Seo , Woo-Sik Nam , Young-Hwan Oh , Yool-Guk Kim , Hyun-Min Seung , Jong-Dae Lee
IPC分类号： G11C13/02 , H01L27/28
CPC分类号： H01L27/285 , B82Y10/00 , G11C11/5664 , G11C13/0014 , G11C13/0016 , G11C2211/5614 , G11C2213/51 , G11C2216/06 , H01L51/0042 , H01L51/0591 , Y10S977/943
摘要： A non-volatile memory device includes lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive organic material layer, wherein the nanocrystal layer includes a plurality of nanocrystals surrounded by an amorphous barrier, wherein the device has a multi-level output current according to a voltage level of an input voltage coupled to the lower and the upper electrodes during a data read operation.
摘要翻译：非易失性存储器件包括衬底上的下电极和上电极，位于下电极和上电极之间的导电有机材料层和位于导电有机材料层内的纳米晶体层，其中纳米晶体层包括多个纳米晶体，通过非晶屏障，其中在数据读取操作期间，器件根据耦合到下电极和上电极的输入电压的电压电平具有多电平输出电流。

9. 发明申请

US20080305574A1 METHOD OF MANUFACTURING NONVOLATILE MEMORY DEVICE USING CONDUCTIVE ORGANIC POLYMER HAVING NANOCRYSTALS EMBEDDED THEREIN 审中-公开
标题翻译：使用具有嵌入的纳米晶体的导电有机聚合物制造非易失性存储器件的方法
公开(公告)号：US20080305574A1
公开(公告)日：2008-12-11
申请号：US12108612
申请日：2008-04-24
申请人： Jea-Gun Park , Gon-Sub Lee , Byeong-Il Han , Jong-Dae Lee
发明人： Jea-Gun Park , Gon-Sub Lee , Byeong-Il Han , Jong-Dae Lee
IPC分类号： H01L51/30
CPC分类号： H01L51/0575 , B82Y10/00 , G11C13/0014 , G11C13/0016 , G11C2211/5614 , H01L51/0042 , H01L51/0591
摘要： The method of manufacturing a nonvolatile memory device includes forming a lower conductive layer on a substrate; forming a first conductive organic layer on the substrate using spin coating; forming a metal layer for forming nanocrystals on the first conductive organic layer, the metal layer partially overlapping the first conductive organic layer; forming a second conductive organic layer on the first conductive organic layer using spin coating; transforming the metal layer into nanocrystals by curing; and forming an upper conductive layer on the second conductive organic layer, the upper conductive layer partially overlapping the nanocrystals. The conductive organic polymer may be poly-N-vinylcarbazole (PVK) or polystyrene (PS).
摘要翻译：非易失性存储器件的制造方法包括在基板上形成下导电层; 使用旋涂在所述基板上形成第一导电有机层; 在所述第一导电有机层上形成用于形成纳米晶体的金属层，所述金属层与所述第一导电有机层部分重叠; 使用旋涂在所述第一导电有机层上形成第二导电有机层; 通过固化将金属层转化为纳米晶体; 以及在所述第二导电有机层上形成上导电层，所述上导电层部分地与所述纳米晶体重叠。导电有机聚合物可以是聚-N-乙烯基咔唑（PVK）或聚苯乙烯（PS）。

10. 发明授权

US08860109B2 Capacitor-less memory device 有权
标题翻译：无电容存储器件
公开(公告)号：US08860109B2
公开(公告)日：2014-10-14
申请号：US12990353
申请日：2009-04-30
申请人： Jea-Gun Park , Tae-Hun Shim , Gon-Sub Lee , Seong-Je Kim , Tae-Hyun Kim
发明人： Jea-Gun Park , Tae-Hun Shim , Gon-Sub Lee , Seong-Je Kim , Tae-Hyun Kim
IPC分类号： H01L27/108 , H01L29/78 , G11C11/404 , H01L29/423 , G11C16/04 , H01L29/786
CPC分类号： H01L29/4234 , G11C11/404 , G11C16/0466 , G11C2211/4016 , H01L27/10802 , H01L29/7841 , H01L29/78687 , H01L29/78696
摘要： Provided is a capacitorless memory device. The device includes a semiconductor substrate, an insulating layer disposed on the semiconductor substrate, a storage region disposed on a partial region of the insulating layer, a channel region disposed on the storage region to provide a valence band energy offset between the channel region and the storage region, a gate insulating layer and a gate electrode sequentially disposed on the channel region, and source and drain regions connected to the channel region and disposed at both sides of the gate electrode. A storage region having different valence band energy from a channel region is disposed under the channel region unit so that charges trapped in the storage region unit cannot be easily drained. Thus, a charge retention time may be increased to improve data storage capability.
摘要翻译：提供了一种无电容器存储器件。所述器件包括半导体衬底，设置在所述半导体衬底上的绝缘层，设置在所述绝缘层的部分区域上的存储区域，设置在所述存储区域上以在所述沟道区域和所述沟道区域之间提供价带能量偏移的沟道区域顺序地设置在沟道区上的栅极绝缘层和栅电极以及连接到沟道区并设置在栅电极两侧的源极和漏极区。在通道区域单元的下方配置具有与通道区域不同的价带能量的存储区域，使得捕获在存储区域单元中的电荷不容易排出。因此，可以增加电荷保留时间以提高数据存储能力。

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